rggen 0.3.0

data/lib/rggen/output_base/verilog_utility/package_definition.rb

@@ -0,0 +1,67 @@
+module RgGen
+  module OutputBase
+    module VerilogUtility
+      class PackageDefinition < StructureDefinition
+        ImportedPackage = Struct.new(:name, :items) do
+          def to_s
+            "import #{import_items.join(', ')};"
+          end
+
+          def import_items
+            (((items.nil? || items.empty?) && [:*]) || items).map do |item|
+              "#{name}::#{item}"
+            end
+          end
+        end
+
+        def import_package(name, items = nil)
+          import_packages << ImportedPackage.new(name, items)
+        end
+
+        def include_file(name)
+          include_files << "`include #{name.to_s.quote}"
+        end
+
+        def to_code
+          bodies.unshift(include_fiels_code ) unless @include_files.nil?
+          bodies.unshift(import_packges_code) unless @import_packages.nil?
+          super
+        end
+
+        private
+
+        def header_code
+          "package #{@name};"
+        end
+
+        def footer_code
+          :endpackage
+        end
+
+        def import_packages
+          @import_packages ||= []
+        end
+
+        def include_files
+          @include_files ||= []
+        end
+
+        def import_packges_code
+          lambda do |code|
+            import_packages.each do |package|
+              code << package << nl
+            end
+          end
+        end
+
+        def include_fiels_code
+          lambda do |code|
+            include_files.each do |file|
+              code << file << nl
+            end
+          end
+        end
+      end
+    end
+  end
+end

data/lib/rggen/output_base/verilog_utility/structure_definition.rb

@@ -0,0 +1,52 @@
+module RgGen
+  module OutputBase
+    module VerilogUtility
+      class StructureDefinition
+        include CodeUtility
+
+        def initialize(name, &body)
+          @name = name
+          body.call(self) if block_given?
+        end
+
+        def body(&block)
+          bodies << block if block_given?
+        end
+
+        def to_code
+          code_block do |code|
+            code << header_code << nl
+            body_code(code) if body_code?
+            code << footer_code << nl
+          end
+        end
+
+        private
+
+        def bodies
+          @bodies ||= []
+        end
+
+        def body_code(code)
+          bodies.each do |body|
+            generate_body_code(code, body)
+          end
+        end
+
+        def generate_body_code(code, body)
+          indent(code, 2) do
+            if body.arity.zero?
+              code << body.call
+            else
+              body.call(code)
+            end
+          end
+        end
+
+        def body_code?
+          @bodies && @bodies.size > 0
+        end
+      end
+    end
+  end
+end

data/lib/rggen/output_base/verilog_utility/subroutine_definition.rb

@@ -0,0 +1,43 @@
+module RgGen
+  module OutputBase
+    module VerilogUtility
+      class SubroutineDefinition < StructureDefinition
+        def initialize(type, name, &body)
+          @type = type
+          super(name, &body)
+        end
+
+        def return_type(data_type_and_width)
+          if [Symbol, String].any?(&data_type_and_width.method(:is_a?))
+            @return_type  = data_type_and_width
+          else
+            data_type     = data_type_and_width[:data_type]
+            width         = data_type_and_width[:width    ] || 1
+            @return_type  =
+              ((width > 1) && "#{data_type} [#{width - 1}:0]") || data_type
+          end
+        end
+
+        attr_setter :arguments
+
+        private
+
+        def function?
+          @type == :function
+        end
+
+        def header_code
+          [
+            (function? && :function   ) || :task,
+            (function? && @return_type) || nil,
+            "#{@name}(#{Array(@arguments).join(', ')});"
+          ].compact.join(' ')
+        end
+
+        def footer_code
+          (function? && :endfunction) || :endtask
+        end
+      end
+    end
+  end
+end

data/lib/rggen/output_base/verilog_utility.rb

@@ -0,0 +1,66 @@
+module RgGen
+  module OutputBase
+    module VerilogUtility
+      private
+
+      def create_identifier(name)
+        Identifier.new(name)
+      end
+
+      def create_declaration(declaration_type, attributes)
+        Declaration.new(declaration_type, attributes)
+      end
+
+      def module_definition(name, &body)
+        ModuleDefinition.new(name, &body).to_code
+      end
+
+      def package_definition(name, &body)
+        PackageDefinition.new(name, &body).to_code
+      end
+
+      def class_definition(name, &body)
+        ClassDefinition.new(name, &body).to_code
+      end
+
+      def function_definition(name, &body)
+        SubroutineDefinition.new(:function, name, &body).to_code
+      end
+
+      def argument(name, attributes)
+        attributes[:name] = name
+        create_declaration(:port, attributes)
+      end
+
+      def assign(lhs, rhs)
+        "assign #{lhs} = #{rhs};"
+      end
+
+      def concat(expression, *other_expressions)
+        expressions = Array[expression, *other_expressions]
+        "{#{expressions.join(', ')}}"
+      end
+
+      def array(expression, *other_expressions)
+        "'#{concat(expression, *other_expressions)}"
+      end
+
+      def string(expression)
+        "\"#{expression}\""
+      end
+
+      def bin(value, width)
+        format("%d'b%0*b", width, width, value)
+      end
+
+      def dec(value, width)
+        format("%d'd%d", width, value)
+      end
+
+      def hex(value, width)
+        print_width = (width + 3) / 4
+        format("%d'h%0*x", width, print_width, value)
+      end
+    end
+  end
+end

data/lib/rggen/version.rb

@@ -0,0 +1,6 @@
+module RgGen
+  MAJOR   = 0
+  MINOR   = 3
+  TEENY   = 0
+  VERSION = "#{MAJOR}.#{MINOR}.#{TEENY}".freeze
+end

data/lib/rggen.rb

@@ -0,0 +1,65 @@
+module RgGen
+  RGGEN_HOME  = File.realpath(File.join(__dir__, '..'))
+
+  require 'forwardable'
+  require 'baby_erubis'
+  require 'fileutils'
+  require 'optparse'
+
+  require_relative 'rggen/version'
+
+  require_relative 'rggen/exceptions'
+
+  require_relative 'rggen/core_extensions/facets'
+  require_relative 'rggen/core_extensions/forwardable'
+  require_relative 'rggen/core_extensions/integer'
+  require_relative 'rggen/core_extensions/math'
+
+  require_relative 'rggen/base/hierarchical_accessors'
+  require_relative 'rggen/base/hierarchical_item_accessors'
+  require_relative 'rggen/base/component'
+  require_relative 'rggen/base/item'
+  require_relative 'rggen/base/component_factory'
+  require_relative 'rggen/base/item_factory'
+
+  require_relative 'rggen/input_base/regexp_patterns'
+  require_relative 'rggen/input_base/component'
+  require_relative 'rggen/input_base/item'
+  require_relative 'rggen/input_base/loader'
+  require_relative 'rggen/input_base/component_factory'
+  require_relative 'rggen/input_base/item_factory'
+
+  require_relative 'rggen/output_base/line'
+  require_relative 'rggen/output_base/code_block'
+  require_relative 'rggen/output_base/code_utility'
+  require_relative 'rggen/output_base/template_utility'
+  require_relative 'rggen/output_base/verilog_utility/identifier'
+  require_relative 'rggen/output_base/verilog_utility/declaration'
+  require_relative 'rggen/output_base/verilog_utility/structure_definition'
+  require_relative 'rggen/output_base/verilog_utility/module_definition'
+  require_relative 'rggen/output_base/verilog_utility/package_definition'
+  require_relative 'rggen/output_base/verilog_utility/class_definition'
+  require_relative 'rggen/output_base/verilog_utility/subroutine_definition'
+  require_relative 'rggen/output_base/verilog_utility'
+  require_relative 'rggen/output_base/component'
+  require_relative 'rggen/output_base/item'
+  require_relative 'rggen/output_base/component_factory'
+  require_relative 'rggen/output_base/item_factory'
+
+  require_relative 'rggen/builder/simple_item_entry'
+  require_relative 'rggen/builder/list_item_entry'
+  require_relative 'rggen/builder/item_store'
+  require_relative 'rggen/builder/component_entry'
+  require_relative 'rggen/builder/component_store'
+  require_relative 'rggen/builder/input_component_store'
+  require_relative 'rggen/builder/output_component_store'
+  require_relative 'rggen/builder/category'
+  require_relative 'rggen/builder/builder'
+
+  require_relative 'rggen/generator'
+
+  require_relative 'rggen/commands'
+
+  require_relative 'rggen/core_components'
+  require_relative 'rggen/builtins'
+end

data/ral/compile.f

@@ -0,0 +1,4 @@
++incdir+${UVM_HOME}/src
++incdir+${RGGEN_HOME}/ral
+${UVM_HOME}/src/uvm_pkg.sv
+${RGGEN_HOME}/ral/rgen_ral_pkg.sv

data/ral/rggen_ral_block.svh

@@ -0,0 +1,84 @@
+`ifndef __RGGEN_RAL_BLOCK_SVH__
+`define __RGGEN_RAL_BLOCK_SVH__
+class rggen_ral_block extends uvm_reg_block;
+  protected uvm_object  cfg;
+
+  extern function new(string name= "rggen_ral_block", int has_coverage = UVM_NO_COVERAGE);
+
+  extern function void configure(uvm_object cfg, uvm_reg_block parent = null, string hdl_path = "");
+
+  extern virtual function uvm_reg_map create_map(
+    string            name,
+    uvm_reg_addr_t    base_addr,
+    int unsigned      n_bytes,
+    uvm_endianness_e  endian,
+    bit               byte_addressing = 1
+  );
+  extern virtual function void lock_model();
+
+  extern protected virtual function void set_cfg(uvm_object cfg);
+  extern protected virtual function uvm_reg_map create_default_map();
+  extern protected virtual function void create_blocks();
+  extern protected virtual function void create_registers();
+endclass
+
+function rggen_ral_block::new(string name, int has_coverage);
+  super.new(name, has_coverage);
+endfunction
+
+function void rggen_ral_block::configure(uvm_object cfg, uvm_reg_block parent, string hdl_path);
+  set_cfg(cfg);
+  super.configure(parent, hdl_path);
+  if (default_map == null) begin
+    default_map = create_default_map();
+  end
+  create_blocks();
+  create_registers();
+endfunction
+
+function uvm_reg_map rggen_ral_block::create_map(
+  string            name,
+  uvm_reg_addr_t    base_addr,
+  int unsigned      n_bytes,
+  uvm_endianness_e  endian,
+  bit               byte_addressing
+);
+  uvm_factory f = uvm_factory::get();
+  f.set_inst_override_by_type(uvm_reg_map::get_type(), rggen_ral_map::get_type(), {get_full_name(), ".", name});
+  return super.create_map(name, base_addr, n_bytes, endian, byte_addressing);
+endfunction
+
+function void rggen_ral_block::lock_model();
+  uvm_reg_block parent_block  = get_parent();
+
+  if (is_locked()) begin
+    return;
+  end
+
+  super.lock_model();
+
+  if (parent_block == null) begin
+    uvm_reg_map maps[$];
+    get_maps(maps);
+    foreach (maps[i]) begin
+      rggen_ral_map rggen_map;
+      if ($cast(rggen_map, maps[i])) begin
+        rggen_map.Xinit_shadow_reg_address_mapX();
+      end
+    end
+  end
+endfunction
+
+function void rggen_ral_block::set_cfg(uvm_object cfg);
+  this.cfg  = cfg;
+endfunction
+
+function uvm_reg_map rggen_ral_block::create_default_map();
+endfunction
+
+function void rggen_ral_block::create_blocks();
+endfunction
+
+function void rggen_ral_block::create_registers();
+endfunction
+`endif

data/ral/rggen_ral_field.svh

@@ -0,0 +1,47 @@
+`ifndef __RGGEN_RAL_FIELD_SVH__
+`define __RGGEN_RAL_FIELD_SVH__
+class rggen_ral_field extends uvm_reg_field;
+  protected uvm_object  cfg;
+
+  extern function new(string name = "rggen_ral_field");
+
+  extern function void configure(
+    uvm_object      cfg,
+    uvm_reg         parent,
+    int unsigned    size,
+    int unsigned    lsb_pos,
+    string          access,
+    bit             volatile,
+    uvm_reg_data_t  reset,
+    bit             has_reset,
+    bit             is_rand,
+    bit             individually_accessible
+  );
+
+  extern protected virtual function void set_cfg(uvm_object cfg);
+endclass
+
+function rggen_ral_field::new(string name);
+  super.new(name);
+endfunction
+
+function void rggen_ral_field::configure(
+  uvm_object      cfg,
+  uvm_reg         parent,
+  int unsigned    size,
+  int unsigned    lsb_pos,
+  string          access,
+  bit             volatile,
+  uvm_reg_data_t  reset,
+  bit             has_reset,
+  bit             is_rand,
+  bit             individually_accessible
+);
+  set_cfg(cfg);
+  super.configure(parent, size, lsb_pos, access, volatile, reset, has_reset, is_rand, individually_accessible);
+endfunction
+
+function void rggen_ral_field::set_cfg(uvm_object cfg);
+  this.cfg  = cfg;
+endfunction
+`endif

data/ral/rggen_ral_macros.svh

@@ -0,0 +1,22 @@
+`ifndef __RGGEN_RAL_MACROS_SVH__
+`define __RGGEN_RAL_MACROS_SVH__
+
+`define rggen_ral_create_field_model(handle, name, width, lsb, access, volatile, reset, has_reset) \
+begin \
+  handle  = new(name); \
+  handle.configure(this.cfg, this, width, lsb, access, volatile, reset, has_reset, 1, 1); \
+end
+
+`define rggen_ral_create_reg_model(handle, base_naem, array_index, offset_address, rights, unmapped) \
+begin \
+  string  __instance_name   = base_naem; \
+  int     __array_index[$]  = array_index; \
+  foreach (__array_index[__i]) begin \
+    $sformat(__instance_name, "%s[%0d]", __instance_name, __array_index[__i]); \
+  end \
+  handle  = new(__instance_name); \
+  handle.configure(this.cfg, this, null, array_index); \
+  default_map.add_reg(handle, offset_address, rights, unmapped); \
+end
+
+`endif

data/ral/rggen_ral_map.svh

@@ -0,0 +1,124 @@
+`ifndef __RGGEN_RAL_MAP_SVH__
+`define __RGGEN_RAL_MAP_SVH__
+class rggen_ral_map extends uvm_reg_map;
+  protected rggen_ral_shadow_reg m_shadow_regs_by_offset[uvm_reg_addr_t][$];
+
+  extern function new(string name = "rggen_ral_map");
+
+  extern virtual function void add_reg(
+    uvm_reg           rg,
+    uvm_reg_addr_t    offset,
+    string            rights    = "RW",
+    bit               unmapped  = 0,
+    uvm_reg_frontdoor frontdoor = null
+  );
+  extern virtual function void set_base_addr(uvm_reg_addr_t offset);
+  extern virtual function void set_submap_offset(uvm_reg_map submap, uvm_reg_addr_t offset);
+
+  extern virtual function uvm_reg get_reg_by_offset(uvm_reg_addr_t offset, bit read = 1);
+
+  extern function void Xinit_shadow_reg_address_mapX();
+
+  `uvm_object_utils(rggen_ral_map)
+endclass
+
+function rggen_ral_map::new(string name);
+  super.new(name);
+endfunction
+
+function void rggen_ral_map::add_reg(
+  uvm_reg           rg,
+  uvm_reg_addr_t    offset,
+  string            rights,
+  bit               unmapped,
+  uvm_reg_frontdoor frontdoor
+);
+  rggen_ral_reg        rggen_reg;
+  rggen_ral_shadow_reg rggen_shadow_reg;
+
+  if ((frontdoor == null) && $cast(rggen_reg, rg)) begin
+    frontdoor = rggen_reg.create_frontdoor();
+  end
+  if ($cast(rggen_shadow_reg, rg)) begin
+    unmapped  = 1;
+  end
+  super.add_reg(rg, offset, rights, unmapped, frontdoor);
+endfunction
+
+function void rggen_ral_map::set_base_addr(uvm_reg_addr_t offset);
+  uvm_reg_block parent_block  = get_parent();
+  uvm_reg_map   parent_map    = get_parent_map();
+  bit           locked        = parent_block.is_locked();
+  super.set_base_addr(offset);
+  if ((parent_map == null) && locked) begin
+    Xinit_shadow_reg_address_mapX();
+  end
+endfunction
+
+function void rggen_ral_map::set_submap_offset(uvm_reg_map submap, uvm_reg_addr_t offset);
+  uvm_reg_block parent_block  = get_parent();
+  bit           locked        = parent_block.is_locked();
+  super.set_submap_offset(submap, offset);
+  if ((submap != null) && locked) begin
+    uvm_reg_map   root_map  = get_root_map();
+    rggen_ral_map  rggen_map;
+    if ($cast(rggen_map, root_map)) begin
+      rggen_map.Xinit_shadow_reg_address_mapX();
+    end
+  end
+endfunction
+
+function uvm_reg rggen_ral_map::get_reg_by_offset(uvm_reg_addr_t offset, bit read);
+  uvm_reg       rg      = super.get_reg_by_offset(offset, read);
+  uvm_reg_block parent  = get_parent();
+  if ((rg == null) && parent.is_locked() && m_shadow_regs_by_offset.exists(offset)) begin
+    foreach (m_shadow_regs_by_offset[offset][i]) begin
+      if (m_shadow_regs_by_offset[offset][i].is_active()) begin
+        rg  = m_shadow_regs_by_offset[offset][i];
+        break;
+      end
+    end
+  end
+  return rg;
+endfunction
+
+function void rggen_ral_map::Xinit_shadow_reg_address_mapX();
+  uvm_reg_map   top_map;
+  rggen_ral_map  top_rggen_map;
+  uvm_reg_map   submaps[$];
+  uvm_reg       regs[$];
+
+  top_map = get_root_map();
+  if (top_map == this) begin
+    m_shadow_regs_by_offset.delete();
+  end
+  if (!$cast(top_rggen_map, top_map)) begin
+    return;
+  end
+
+  get_submaps(submaps, UVM_NO_HIER);
+  foreach (submaps[i]) begin
+    rggen_ral_map  rggen_map;
+    if ($cast(rggen_map, submaps[i])) begin
+      rggen_map.Xinit_shadow_reg_address_mapX();
+    end
+  end
+
+  get_registers(regs, UVM_NO_HIER);
+  foreach (regs[i]) begin
+    rggen_ral_shadow_reg  shadow_reg;
+    uvm_reg_map_info      map_info;
+
+    if (!$cast(shadow_reg, regs[i])) begin
+      continue;
+    end
+
+    map_info          = get_reg_map_info(shadow_reg);
+    map_info.unmapped = 0;
+    void'(get_physical_addresses(map_info.offset, 0, shadow_reg.get_n_bytes(), map_info.addr));
+    foreach (map_info.addr[j]) begin
+      top_rggen_map.m_shadow_regs_by_offset[map_info.addr[j]].push_back(shadow_reg);
+    end
+  end
+endfunction
+`endif

data/ral/rggen_ral_pkg.sv

@@ -0,0 +1,14 @@
+`ifndef __RGGEN_RAL_PKG_SV__
+`define __RGGEN_RAL_PKG_SV__
+package rggen_ral_pkg;
+  import  uvm_pkg::*;
+  `include  "uvm_macros.svh"
+
+  `include  "rggen_ral_macros.svh"
+  `include  "rggen_ral_field.svh"
+  `include  "rggen_ral_reg.svh"
+  `include  "rggen_ral_shadow_reg.svh"
+  `include  "rggen_ral_map.svh"
+  `include  "rggen_ral_block.svh"
+endpackage
+`endif

data/ral/rggen_ral_reg.svh

@@ -0,0 +1,52 @@
+`ifndef __RGGEN_RAL_REG_SVH__
+`define __RGGEN_RAL_REG_SVH__
+class rggen_ral_reg extends uvm_reg;
+  protected int         indexes[$];
+  protected uvm_object  cfg;
+
+  extern function new(string name, int unsigned n_bits, int has_coverage);
+
+  extern function void configure(
+    uvm_object    cfg,
+    uvm_reg_block blk_parent,
+    uvm_reg_file  regfile_parent,
+    int           indexes[$],
+    string        hdl_path = ""
+  );
+
+  extern virtual function uvm_reg_frontdoor create_frontdoor();
+
+  extern protected virtual function void set_cfg(uvm_object cfg);
+  extern protected virtual function void create_fields();
+endclass
+
+function rggen_ral_reg::new(string name, int unsigned n_bits, int has_coverage);
+  super.new(name, n_bits, has_coverage);
+endfunction
+
+function void rggen_ral_reg::configure(
+  uvm_object    cfg,
+  uvm_reg_block blk_parent,
+  uvm_reg_file  regfile_parent,
+  int           indexes[$],
+  string        hdl_path
+);
+  foreach (indexes[i]) begin
+    this.indexes.push_back(indexes[i]);
+  end
+  set_cfg(cfg);
+  super.configure(blk_parent, regfile_parent, hdl_path);
+  create_fields();
+endfunction
+
+function uvm_reg_frontdoor rggen_ral_reg::create_frontdoor();
+  return null;
+endfunction
+
+function void rggen_ral_reg::set_cfg(uvm_object cfg);
+  this.cfg  = cfg;
+endfunction
+
+function void rggen_ral_reg::create_fields();
+endfunction
+`endif