rggen 0.16.0 → 0.20.0

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Files changed (5) hide show
  1. checksums.yaml +4 -4
  2. data/LICENSE +1 -1
  3. data/README.md +54 -4
  4. data/lib/rggen/version.rb +1 -1
  5. metadata +16 -16
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data/LICENSE CHANGED
@@ -1,6 +1,6 @@
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  The MIT License (MIT)
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- Copyright (c) 2019 Taichi Ishitani
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+ Copyright (c) 2019-2020 Taichi Ishitani
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  Permission is hereby granted, free of charge, to any person obtaining a copy
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  of this software and associated documentation files (the "Software"), to deal
data/README.md CHANGED
@@ -1,5 +1,5 @@
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  [![Gem Version](https://badge.fury.io/rb/rggen.svg)](https://badge.fury.io/rb/rggen)
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- [![Build Status](https://travis-ci.com/rggen/rggen.svg?branch=master)](https://travis-ci.com/rggen/rggen)
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+ [![CI](https://github.com/rggen/rggen/workflows/CI/badge.svg)](https://github.com/rggen/rggen/actions?query=workflow%3ACI)
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  [![Maintainability](https://api.codeclimate.com/v1/badges/5ee2248300ec0517e597/maintainability)](https://codeclimate.com/github/rggen/rggen/maintainability)
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  [![codecov](https://codecov.io/gh/rggen/rggen/branch/master/graph/badge.svg)](https://codecov.io/gh/rggen/rggen)
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  [![Quality Gate Status](https://sonarcloud.io/api/project_badges/measure?project=rggen_rggen&metric=alert_status)](https://sonarcloud.io/dashboard?id=rggen_rggen)
@@ -7,7 +7,7 @@
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  # RgGen
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- RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
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+ RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
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  RgGen has following features:
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@@ -28,7 +28,7 @@ RgGen has following features:
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  ### Ruby
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- RgGen is written in the [Ruby](https://www.ruby-lang.org/en/about/) programing language and its required version is 2.3 or later. You need to install any of these versions of Ruby before installing RgGen tool. To install Ruby, see [this page](https://www.ruby-lang.org/en/downloads/).
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+ RgGen is written in the [Ruby](https://www.ruby-lang.org/en/about/) programing language and its required version is 2.4 or later. You need to install any of these versions of Ruby before installing RgGen tool. To install Ruby, see [this page](https://www.ruby-lang.org/en/downloads/).
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  ### Installatin Command
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@@ -68,6 +68,56 @@ To resolve the above error, there are three solutions. See [this page](https://g
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  See [Wiki documents](https://github.com/rggen/rggen/wiki).
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+ ## Supported Tools
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+
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+ Following EDA tools can accept the generated source files.
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+
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+ * Simulation tools
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+ * Synopsys VCS
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+ * Cadence Xcelium
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+ * Xilinx Vivado Simulator
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+ * Confirmed RTL only
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+ * Not sure if RAL models are accepted
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+ * Verilator
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+ * Need `-Wno-fatal` switch
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+ * Synthesis tools
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+ * Synopsys Design Compiler
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+ * Intel Quartus
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+ * Xilinx Vivado
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+
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+ ## Example
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+
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+ You can get example configuration file and register map specification listed below:
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+
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+ * Configuration file
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+ * https://github.com/rggen/rggen-sample/blob/master/config.yml
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+ * Register map specifications
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+ * https://github.com/rggen/rggen-sample/blob/master/block_0.yml
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+ * https://github.com/rggen/rggen-sample/blob/master/block_1.yml
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+
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+ By using these example files, you can try to use RgGen. Hit command below:
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+
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+ ```
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+ $ rggen -c config.yml -o out block_0.yml block_1.yml
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+ ```
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+
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+ * `-c`
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+ * Specify path to your configuration file
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+ * `-o`
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+ * Specify path to the directory where generated files will be written to
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+
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+ Then, generated files listed below will be written to `out` directory.
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+
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+ * SystemVerilog RTL
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+ * https://github.com/rggen/rggen-sample/blob/master/block_0.sv
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+ * https://github.com/rggen/rggen-sample/blob/master/block_1.sv
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+ * UVM RAL model
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+ * https://github.com/rggen/rggen-sample/blob/master/block_0_ral_pkg.sv
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+ * https://github.com/rggen/rggen-sample/blob/master/block_1_ral_pkg.sv
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+ * Markdown document
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+ * https://github.com/rggen/rggen-sample/blob/master/block_0.md
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+ * https://github.com/rggen/rggen-sample/blob/master/block_1.md
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+
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  ## Contact
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  Feedbacks, bug reports, questions and etc. are wellcome! You can post them by using following ways:
@@ -88,7 +138,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
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  ## Copyright & License
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- Copyright © 2019 Taichi Ishitani. RgGen is licensed unther the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher detils.
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+ Copyright © 2019-2020 Taichi Ishitani. RgGen is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher detils.
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  ## Code of Conduct
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data/lib/rggen/version.rb CHANGED
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  # frozen_string_literal: true
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  module RgGen
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- VERSION = '0.16.0'
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+ VERSION = '0.20.0'
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  end
metadata CHANGED
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  --- !ruby/object:Gem::Specification
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  name: rggen
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  version: !ruby/object:Gem::Version
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- version: 0.16.0
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+ version: 0.20.0
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  platform: ruby
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  authors:
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  - Taichi Ishitani
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  autorequire:
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  bindir: bin
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  cert_chain: []
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- date: 2019-10-01 00:00:00.000000000 Z
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+ date: 2020-07-06 00:00:00.000000000 Z
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  dependencies:
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  - !ruby/object:Gem::Dependency
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  name: rggen-core
@@ -16,70 +16,70 @@ dependencies:
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: '0.16'
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+ version: 0.20.0
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: '0.16'
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+ version: 0.20.0
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  - !ruby/object:Gem::Dependency
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  name: rggen-default-register-map
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  requirement: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: '0.16'
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+ version: 0.20.0
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: '0.16'
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+ version: 0.20.0
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  - !ruby/object:Gem::Dependency
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  name: rggen-markdown
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  requirement: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: '0.15'
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+ version: 0.17.0
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: '0.15'
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+ version: 0.17.0
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  - !ruby/object:Gem::Dependency
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  name: rggen-spreadsheet-loader
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  requirement: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: '0.14'
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+ version: 0.16.0
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: '0.14'
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+ version: 0.16.0
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  - !ruby/object:Gem::Dependency
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  name: rggen-systemverilog
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  requirement: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: '0.16'
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+ version: 0.20.0
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: '0.16'
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+ version: 0.20.0
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  - !ruby/object:Gem::Dependency
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  name: bundler
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  requirement: !ruby/object:Gem::Requirement
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  version: '0'
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  description: |
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  RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
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- It will automatically generate soruce code related to control/status registers (CSR),
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+ It will automatically generate soruce code related to configuration and status registers (CSR),
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  e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
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  email:
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  - rggen@googlegroups.com
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  requirements:
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  - - ">="
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  - !ruby/object:Gem::Version
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- version: '2.3'
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+ version: '2.4'
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  required_rubygems_version: !ruby/object:Gem::Requirement
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  requirements:
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  - - ">="
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  - !ruby/object:Gem::Version
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  version: '0'
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  requirements: []
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- rubygems_version: 3.0.3
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+ rubygems_version: 3.1.2
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  signing_key:
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  specification_version: 4
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- summary: Code generation tool for control/status registers
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+ summary: Code generation tool for configuration and status registers
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  test_files: []