rggen 0.16.0 → 0.20.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/LICENSE +1 -1
- data/README.md +54 -4
- data/lib/rggen/version.rb +1 -1
- metadata +16 -16
checksums.yaml
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 4b0ca89bd97b12fadfdc1e78eb91cad417d4faa07b4c61904cbeaef395d52987
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data.tar.gz: 37056eff9ac783741b928a4b45440bd1f23cf49fd4a766175e39113e12bd5fda
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SHA512:
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metadata.gz:
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metadata.gz: 27cdc3cd55728b72d6f9330a9602c63ea705c61b0808031477c822be4a6c6e08015234fc92707e834a82f924e3b29158e1f15259c27d5082a6b6a40c7eda34f5
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data.tar.gz: 343b959bbcab5b6763ee242cf6908f1c0317e3c65c676534ed0963b2961e0bb2261de3a5497a804260ef9144b02f7a0ff6d8e91c5fc0879b91f06c23ee181b78
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data/LICENSE
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data/README.md
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[](https://badge.fury.io/rb/rggen)
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[](https://github.com/rggen/rggen/actions?query=workflow%3ACI)
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[](https://codeclimate.com/github/rggen/rggen/maintainability)
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[](https://codecov.io/gh/rggen/rggen)
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[](https://sonarcloud.io/dashboard?id=rggen_rggen)
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# RgGen
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RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to
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RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
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RgGen has following features:
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### Ruby
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RgGen is written in the [Ruby](https://www.ruby-lang.org/en/about/) programing language and its required version is 2.
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RgGen is written in the [Ruby](https://www.ruby-lang.org/en/about/) programing language and its required version is 2.4 or later. You need to install any of these versions of Ruby before installing RgGen tool. To install Ruby, see [this page](https://www.ruby-lang.org/en/downloads/).
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### Installatin Command
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@@ -68,6 +68,56 @@ To resolve the above error, there are three solutions. See [this page](https://g
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See [Wiki documents](https://github.com/rggen/rggen/wiki).
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## Supported Tools
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Following EDA tools can accept the generated source files.
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* Simulation tools
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* Synopsys VCS
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* Cadence Xcelium
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* Xilinx Vivado Simulator
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* Confirmed RTL only
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* Not sure if RAL models are accepted
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* Verilator
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* Need `-Wno-fatal` switch
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* Synthesis tools
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* Synopsys Design Compiler
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* Intel Quartus
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* Xilinx Vivado
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## Example
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You can get example configuration file and register map specification listed below:
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* Configuration file
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* https://github.com/rggen/rggen-sample/blob/master/config.yml
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* Register map specifications
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* https://github.com/rggen/rggen-sample/blob/master/block_0.yml
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* https://github.com/rggen/rggen-sample/blob/master/block_1.yml
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By using these example files, you can try to use RgGen. Hit command below:
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```
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$ rggen -c config.yml -o out block_0.yml block_1.yml
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```
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* `-c`
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* Specify path to your configuration file
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* `-o`
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* Specify path to the directory where generated files will be written to
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Then, generated files listed below will be written to `out` directory.
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* SystemVerilog RTL
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* https://github.com/rggen/rggen-sample/blob/master/block_0.sv
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* https://github.com/rggen/rggen-sample/blob/master/block_1.sv
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* UVM RAL model
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* https://github.com/rggen/rggen-sample/blob/master/block_0_ral_pkg.sv
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* https://github.com/rggen/rggen-sample/blob/master/block_1_ral_pkg.sv
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* Markdown document
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* https://github.com/rggen/rggen-sample/blob/master/block_0.md
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* https://github.com/rggen/rggen-sample/blob/master/block_1.md
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## Contact
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Feedbacks, bug reports, questions and etc. are wellcome! You can post them by using following ways:
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## Copyright & License
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Copyright © 2019 Taichi Ishitani. RgGen is licensed
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Copyright © 2019-2020 Taichi Ishitani. RgGen is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher detils.
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## Code of Conduct
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data/lib/rggen/version.rb
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metadata
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--- !ruby/object:Gem::Specification
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name: rggen
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version: !ruby/object:Gem::Version
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version: 0.
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version: 0.20.0
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platform: ruby
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authors:
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- Taichi Ishitani
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autorequire:
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bindir: bin
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cert_chain: []
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date:
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date: 2020-07-06 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: rggen-core
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version:
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version: 0.20.0
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type: :runtime
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prerelease: false
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version_requirements: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version:
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version: 0.20.0
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- !ruby/object:Gem::Dependency
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name: rggen-default-register-map
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requirement: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version:
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version: 0.20.0
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type: :runtime
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prerelease: false
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version_requirements: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version:
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version: 0.20.0
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- !ruby/object:Gem::Dependency
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name: rggen-markdown
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requirement: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version:
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version: 0.17.0
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type: :runtime
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prerelease: false
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version_requirements: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version:
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version: 0.17.0
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- !ruby/object:Gem::Dependency
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name: rggen-spreadsheet-loader
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requirement: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version:
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version: 0.16.0
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type: :runtime
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prerelease: false
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version_requirements: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version:
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version: 0.16.0
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- !ruby/object:Gem::Dependency
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name: rggen-systemverilog
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requirement: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version:
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version: 0.20.0
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type: :runtime
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prerelease: false
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version_requirements: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version:
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version: 0.20.0
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- !ruby/object:Gem::Dependency
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name: bundler
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requirement: !ruby/object:Gem::Requirement
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version: '0'
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description: |
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RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
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It will automatically generate soruce code related to
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It will automatically generate soruce code related to configuration and status registers (CSR),
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e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
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email:
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- rggen@googlegroups.com
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requirements:
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- - ">="
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version: '2.
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version: '2.4'
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required_rubygems_version: !ruby/object:Gem::Requirement
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requirements:
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- - ">="
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- !ruby/object:Gem::Version
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version: '0'
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requirements: []
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rubygems_version: 3.
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rubygems_version: 3.1.2
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signing_key:
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specification_version: 4
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summary: Code generation tool for
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summary: Code generation tool for configuration and status registers
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test_files: []
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