rggen-vhdl 0.6.0 → 0.7.0
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- checksums.yaml +4 -4
- data/lib/rggen/vhdl/register/type/external.erb +1 -0
- data/lib/rggen/vhdl/register/type/external.rb +5 -1
- data/lib/rggen/vhdl/register/type/rw.erb +29 -0
- data/lib/rggen/vhdl/register/type/rw.rb +7 -0
- data/lib/rggen/vhdl/register_block/vhdl_top.rb +1 -1
- data/lib/rggen/vhdl/utility.rb +4 -0
- data/lib/rggen/vhdl/version.rb +1 -1
- data/lib/rggen/vhdl.rb +1 -0
- metadata +8 -6
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
|
|
1
1
|
---
|
2
2
|
SHA256:
|
3
|
-
metadata.gz:
|
4
|
-
data.tar.gz:
|
3
|
+
metadata.gz: 4faaef428fbba048c4000898fc4bb25625d9734eec168da0b7e276250fd1458a
|
4
|
+
data.tar.gz: 01b24c92db5237ce7e6e712323b344fc1b99dcac793344d776a1dbe4eef6af25
|
5
5
|
SHA512:
|
6
|
-
metadata.gz:
|
7
|
-
data.tar.gz:
|
6
|
+
metadata.gz: 9a8e30cc40d73c1f74be2c121e4730c8d79fcae51ff9404e8815d16d1e719d5089b418493a973899c8263c0873fe55c5d3139fa0ef3808f083707edd4374d7b9
|
7
|
+
data.tar.gz: 894de4ef4fda8f945455fb1555ff8583abb84cadaf47cdf1552b1e048020de544f4682617ace6cea1979f3d8628ee50fb72c2cbdad483f9216ec9dfb91dd77b3
|
@@ -3,6 +3,10 @@
|
|
3
3
|
RgGen.define_list_item_feature(:register, :type, :external) do
|
4
4
|
vhdl do
|
5
5
|
build do
|
6
|
+
generic :strobe_width, {
|
7
|
+
name: "#{register.name}_STROBE_WIDTH".upcase,
|
8
|
+
type: :positive, default: configuration.bus_width / 8
|
9
|
+
}
|
6
10
|
output :external_valid, {
|
7
11
|
name: "o_#{register.name}_valid"
|
8
12
|
}
|
@@ -16,7 +20,7 @@ RgGen.define_list_item_feature(:register, :type, :external) do
|
|
16
20
|
name: "o_#{register.name}_data", width: bus_width
|
17
21
|
}
|
18
22
|
output :external_strobe, {
|
19
|
-
name: "o_#{register.name}_strobe", width:
|
23
|
+
name: "o_#{register.name}_strobe", width: strobe_width
|
20
24
|
}
|
21
25
|
input :external_ready, {
|
22
26
|
name: "i_#{register.name}_ready"
|
@@ -0,0 +1,29 @@
|
|
1
|
+
u_register: entity work.rggen_default_register
|
2
|
+
generic map (
|
3
|
+
READABLE => true,
|
4
|
+
WRITABLE => true,
|
5
|
+
ADDRESS_WIDTH => <%= address_width %>,
|
6
|
+
OFFSET_ADDRESS => <%= offset_address %>,
|
7
|
+
BUS_WIDTH => <%= bus_width %>,
|
8
|
+
DATA_WIDTH => <%= width %>
|
9
|
+
)
|
10
|
+
port map (
|
11
|
+
i_clk => <%= clock %>,
|
12
|
+
i_rst_n => <%= reset %>,
|
13
|
+
i_register_valid => <%= register_valid %>,
|
14
|
+
i_register_access => <%= register_access %>,
|
15
|
+
i_register_address => <%= register_address %>,
|
16
|
+
i_register_write_data => <%= register_write_data %>,
|
17
|
+
i_register_strobe => <%= register_strobe %>,
|
18
|
+
o_register_active => <%= register_active %>,
|
19
|
+
o_register_ready => <%= register_ready %>,
|
20
|
+
o_register_status => <%= register_status %>,
|
21
|
+
o_register_read_data => <%= register_read_data %>,
|
22
|
+
o_register_value => <%= register_value %>,
|
23
|
+
o_bit_field_valid => <%= bit_field_valid %>,
|
24
|
+
o_bit_field_read_mask => <%= bit_field_read_mask %>,
|
25
|
+
o_bit_field_write_mask => <%= bit_field_write_mask %>,
|
26
|
+
o_bit_field_write_data => <%= bit_field_write_data %>,
|
27
|
+
i_bit_field_read_data => <%= bit_field_read_data %>,
|
28
|
+
i_bit_field_value => <%= bit_field_value %>
|
29
|
+
);
|
data/lib/rggen/vhdl/utility.rb
CHANGED
@@ -20,6 +20,10 @@ module RgGen
|
|
20
20
|
format('x"%0*x"', print_width, value)
|
21
21
|
end
|
22
22
|
|
23
|
+
def width_cast(expression, _width)
|
24
|
+
expression
|
25
|
+
end
|
26
|
+
|
23
27
|
def local_scope(scope_name, attributes = {}, &block)
|
24
28
|
LocalScope.new(attributes.merge(name: scope_name), &block).to_code
|
25
29
|
end
|
data/lib/rggen/vhdl/version.rb
CHANGED
data/lib/rggen/vhdl.rb
CHANGED
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: rggen-vhdl
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 0.
|
4
|
+
version: 0.7.0
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Taichi Ishitani
|
8
8
|
autorequire:
|
9
9
|
bindir: bin
|
10
10
|
cert_chain: []
|
11
|
-
date: 2023-
|
11
|
+
date: 2023-09-12 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: rggen-systemverilog
|
@@ -16,14 +16,14 @@ dependencies:
|
|
16
16
|
requirements:
|
17
17
|
- - ">="
|
18
18
|
- !ruby/object:Gem::Version
|
19
|
-
version: 0.
|
19
|
+
version: 0.31.0
|
20
20
|
type: :runtime
|
21
21
|
prerelease: false
|
22
22
|
version_requirements: !ruby/object:Gem::Requirement
|
23
23
|
requirements:
|
24
24
|
- - ">="
|
25
25
|
- !ruby/object:Gem::Version
|
26
|
-
version: 0.
|
26
|
+
version: 0.31.0
|
27
27
|
- !ruby/object:Gem::Dependency
|
28
28
|
name: bundler
|
29
29
|
requirement: !ruby/object:Gem::Requirement
|
@@ -95,6 +95,8 @@ files:
|
|
95
95
|
- lib/rggen/vhdl/register/type/external.rb
|
96
96
|
- lib/rggen/vhdl/register/type/indirect.erb
|
97
97
|
- lib/rggen/vhdl/register/type/indirect.rb
|
98
|
+
- lib/rggen/vhdl/register/type/rw.erb
|
99
|
+
- lib/rggen/vhdl/register/type/rw.rb
|
98
100
|
- lib/rggen/vhdl/register/vhdl_top.rb
|
99
101
|
- lib/rggen/vhdl/register_block/protocol.rb
|
100
102
|
- lib/rggen/vhdl/register_block/protocol/apb.erb
|
@@ -135,8 +137,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
|
|
135
137
|
- !ruby/object:Gem::Version
|
136
138
|
version: '0'
|
137
139
|
requirements: []
|
138
|
-
rubygems_version: 3.4.
|
140
|
+
rubygems_version: 3.4.17
|
139
141
|
signing_key:
|
140
142
|
specification_version: 4
|
141
|
-
summary: rggen-vhdl-0.
|
143
|
+
summary: rggen-vhdl-0.7.0
|
142
144
|
test_files: []
|