rggen-vhdl 0.6.0 → 0.7.0

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checksums.yaml CHANGED
@@ -1,7 +1,7 @@
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@@ -2,6 +2,7 @@ u_register: entity work.rggen_external_register
2
2
  generic map (
3
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  ADDRESS_WIDTH => <%= address_width %>,
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  BUS_WIDTH => <%= bus_width %>,
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+ STROBE_WIDTH => <%= strobe_width %>,
5
6
  START_ADDRESS => <%= start_address %>,
6
7
  BYTE_SIZE => <%= byte_size %>
7
8
  )
@@ -3,6 +3,10 @@
3
3
  RgGen.define_list_item_feature(:register, :type, :external) do
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  vhdl do
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5
  build do
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+ generic :strobe_width, {
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+ name: "#{register.name}_STROBE_WIDTH".upcase,
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+ type: :positive, default: configuration.bus_width / 8
9
+ }
6
10
  output :external_valid, {
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11
  name: "o_#{register.name}_valid"
8
12
  }
@@ -16,7 +20,7 @@ RgGen.define_list_item_feature(:register, :type, :external) do
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20
  name: "o_#{register.name}_data", width: bus_width
17
21
  }
18
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  output :external_strobe, {
19
- name: "o_#{register.name}_strobe", width: bus_width / 8
23
+ name: "o_#{register.name}_strobe", width: strobe_width
20
24
  }
21
25
  input :external_ready, {
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26
  name: "i_#{register.name}_ready"
@@ -0,0 +1,29 @@
1
+ u_register: entity work.rggen_default_register
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+ generic map (
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+ READABLE => true,
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+ WRITABLE => true,
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+ ADDRESS_WIDTH => <%= address_width %>,
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+ OFFSET_ADDRESS => <%= offset_address %>,
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+ BUS_WIDTH => <%= bus_width %>,
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+ DATA_WIDTH => <%= width %>
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+ )
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+ port map (
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+ i_clk => <%= clock %>,
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+ i_rst_n => <%= reset %>,
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+ i_register_valid => <%= register_valid %>,
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+ i_register_access => <%= register_access %>,
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+ i_register_address => <%= register_address %>,
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+ i_register_write_data => <%= register_write_data %>,
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+ i_register_strobe => <%= register_strobe %>,
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+ o_register_active => <%= register_active %>,
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+ o_register_ready => <%= register_ready %>,
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+ o_register_status => <%= register_status %>,
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+ o_register_read_data => <%= register_read_data %>,
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+ o_register_value => <%= register_value %>,
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+ o_bit_field_valid => <%= bit_field_valid %>,
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+ o_bit_field_read_mask => <%= bit_field_read_mask %>,
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+ o_bit_field_write_mask => <%= bit_field_write_mask %>,
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+ o_bit_field_write_data => <%= bit_field_write_data %>,
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+ i_bit_field_read_data => <%= bit_field_read_data %>,
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+ i_bit_field_value => <%= bit_field_value %>
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+ );
@@ -0,0 +1,7 @@
1
+ # frozen_string_literal: true
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+
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+ RgGen.define_list_item_feature(:register, :type, :rw) do
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+ vhdl do
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+ main_code :register, from_template: true
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+ end
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+ end
@@ -17,7 +17,7 @@ RgGen.define_simple_feature(:register_block, :vhdl_top) do
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  width: bus_width
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  }
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  signal :register_strobe, {
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- width: bus_width / 8
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+ width: bus_width
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  }
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  signal :register_active, {
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  array_size: [total_registers]
@@ -20,6 +20,10 @@ module RgGen
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  format('x"%0*x"', print_width, value)
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  end
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+ def width_cast(expression, _width)
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+ expression
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+ end
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+
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  def local_scope(scope_name, attributes = {}, &block)
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  LocalScope.new(attributes.merge(name: scope_name), &block).to_code
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  end
@@ -2,6 +2,6 @@
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  module RgGen
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  module VHDL
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- VERSION = '0.6.0'
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+ VERSION = '0.7.0'
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6
  end
7
7
  end
data/lib/rggen/vhdl.rb CHANGED
@@ -31,6 +31,7 @@ RgGen.setup_plugin :'rggen-vhdl' do |plugin|
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  'vhdl/register/type',
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  'vhdl/register/type/external',
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  'vhdl/register/type/indirect',
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+ 'vhdl/register/type/rw',
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  'vhdl/bit_field/vhdl_top',
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  'vhdl/bit_field/type',
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  'vhdl/bit_field/type/custom',
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
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  name: rggen-vhdl
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3
  version: !ruby/object:Gem::Version
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- version: 0.6.0
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+ version: 0.7.0
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  platform: ruby
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6
  authors:
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7
  - Taichi Ishitani
8
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  autorequire:
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  bindir: bin
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  cert_chain: []
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- date: 2023-04-28 00:00:00.000000000 Z
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+ date: 2023-09-12 00:00:00.000000000 Z
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  dependencies:
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  - !ruby/object:Gem::Dependency
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  name: rggen-systemverilog
@@ -16,14 +16,14 @@ dependencies:
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  requirements:
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  - - ">="
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  - !ruby/object:Gem::Version
19
- version: 0.30.0
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+ version: 0.31.0
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  type: :runtime
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  prerelease: false
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22
  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - ">="
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  - !ruby/object:Gem::Version
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- version: 0.30.0
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+ version: 0.31.0
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  - !ruby/object:Gem::Dependency
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  name: bundler
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  requirement: !ruby/object:Gem::Requirement
@@ -95,6 +95,8 @@ files:
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95
  - lib/rggen/vhdl/register/type/external.rb
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  - lib/rggen/vhdl/register/type/indirect.erb
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  - lib/rggen/vhdl/register/type/indirect.rb
98
+ - lib/rggen/vhdl/register/type/rw.erb
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+ - lib/rggen/vhdl/register/type/rw.rb
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100
  - lib/rggen/vhdl/register/vhdl_top.rb
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101
  - lib/rggen/vhdl/register_block/protocol.rb
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102
  - lib/rggen/vhdl/register_block/protocol/apb.erb
@@ -135,8 +137,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
135
137
  - !ruby/object:Gem::Version
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  version: '0'
137
139
  requirements: []
138
- rubygems_version: 3.4.10
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+ rubygems_version: 3.4.17
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  signing_key:
140
142
  specification_version: 4
141
- summary: rggen-vhdl-0.6.0
143
+ summary: rggen-vhdl-0.7.0
142
144
  test_files: []