rggen-systemverilog 0.33.1 → 0.35.0

data/lib/rggen/systemverilog/rtl.rb

@@ -1,6 +1,7 @@
 # frozen_string_literal: true
 
 require_relative 'common'
+require_relative 'register_map/keyword_checker'
 require_relative 'rtl/feature'
 require_relative 'rtl/partial_sum'
 require_relative 'rtl/register_index'
@@ -20,12 +21,13 @@ RgGen.setup_plugin :'rggen-sv-rtl' do |plugin|
   end
 
   plugin.files [
-    'rtl/global/array_port_format',
     'rtl/register_block/sv_rtl_top',
     'rtl/register_block/protocol',
     'rtl/register_block/protocol/apb',
     'rtl/register_block/protocol/axi4lite',
+    'rtl/register_block/protocol/avalon',
     'rtl/register_block/protocol/wishbone',
+    'rtl/register_block/protocol/native',
     'rtl/register_file/sv_rtl_top',
     'rtl/register/sv_rtl_top',
     'rtl/register/type',
@@ -66,4 +68,8 @@ RgGen.setup_plugin :'rggen-sv-rtl' do |plugin|
     'rtl_package/register/sv_rtl_package',
     'rtl_package/register_block/sv_rtl_package'
   ]
+
+  plugin.files [
+    'register_map/name'
+  ]
 end

data/lib/rggen/systemverilog/rtl_package/feature.rb

@@ -10,14 +10,14 @@ module RgGen
           component.full_name(separator)
         end
 
-        def create_parameter(parameter_type, attributes, &block)
+        def create_parameter(parameter_type, attributes, &)
           attributes =
             attributes.merge(
-              parameter_type: parameter_type, array_format: :unpacked,
+              parameter_type:, array_format: :unpacked,
               name: attributes[:name].upcase
             )
           DataObject.new(
-            :parameter, attributes, &block
+            :parameter, attributes, &
           )
         end
 

data/lib/rggen/systemverilog/rtl_package/register/sv_rtl_package.rb

@@ -41,7 +41,7 @@ RgGen.define_simple_feature(:register, :sv_rtl_package) do
       value_list = group_address_list(address_list, size_list).first
       localparam :__offset, {
         name: "#{full_name}_byte_offset",
-        data_type: :bit, width: width, array_size: size_list, default: value_list
+        data_type: :bit, width:, array_size: size_list, default: value_list
       }
     end
 
@@ -68,7 +68,7 @@ RgGen.define_simple_feature(:register, :sv_rtl_package) do
       value = address_list.first
       localparam :__offset, {
         name: "#{full_name}_byte_offset",
-        data_type: :bit, width: width, default: value
+        data_type: :bit, width:, default: value
       }
     end
 

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.33.1'
+    VERSION = '0.35.0'
   end
 end

metadata

@@ -1,14 +1,13 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.33.1
+  version: 0.35.0
 platform: ruby
 authors:
 - Taichi Ishitani
-autorequire: 
 bindir: bin
 cert_chain: []
-date: 2024-11-28 00:00:00.000000000 Z
+date: 2025-02-19 00:00:00.000000000 Z
 dependencies: []
 description: 'SystemVerilog RTL and UVM RAL model generators for RgGen.
 
@@ -60,6 +59,8 @@ files:
 - lib/rggen/systemverilog/ral/register_common.rb
 - lib/rggen/systemverilog/ral/register_file/sv_ral_model.erb
 - lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb
+- lib/rggen/systemverilog/register_map/keyword_checker.rb
+- lib/rggen/systemverilog/register_map/name.rb
 - lib/rggen/systemverilog/rtl.rb
 - lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/bit_field/type.rb
@@ -101,7 +102,6 @@ files:
 - lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb
 - lib/rggen/systemverilog/rtl/bit_field_index.rb
 - lib/rggen/systemverilog/rtl/feature.rb
-- lib/rggen/systemverilog/rtl/global/array_port_format.rb
 - lib/rggen/systemverilog/rtl/indirect_index.rb
 - lib/rggen/systemverilog/rtl/partial_sum.rb
 - lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb
@@ -116,8 +116,12 @@ files:
 - lib/rggen/systemverilog/rtl/register_block/protocol.rb
 - lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb
 - lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb
+- lib/rggen/systemverilog/rtl/register_block/protocol/avalon.erb
+- lib/rggen/systemverilog/rtl/register_block/protocol/avalon.rb
 - lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb
 - lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb
+- lib/rggen/systemverilog/rtl/register_block/protocol/native.erb
+- lib/rggen/systemverilog/rtl/register_block/protocol/native.rb
 - lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.erb
 - lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.rb
 - lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb
@@ -139,7 +143,6 @@ metadata:
   rubygems_mfa_required: 'true'
   source_code_uri: https://github.com/rggen/rggen-systemverilog
   wiki_uri: https://github.com/rggen/rggen/wiki
-post_install_message: 
 rdoc_options: []
 require_paths:
 - lib
@@ -147,15 +150,14 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: '3.0'
+      version: '3.1'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.5.16
-signing_key: 
+rubygems_version: 3.6.2
 specification_version: 4
-summary: rggen-systemverilog-0.33.1
+summary: rggen-systemverilog-0.35.0
 test_files: []

data/lib/rggen/systemverilog/rtl/global/array_port_format.rb

@@ -1,21 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_simple_feature(:global, :array_port_format) do
-  configuration do
-    property :array_port_format, default: :packed
-
-    input_pattern /(packed|unpacked|serialized)/i
-    ignore_empty_value false
-
-    build do |value|
-      @array_port_format =
-        if pattern_matched?
-          match_data[1].downcase.to_sym
-        else
-          error "illegal input value for array port format: #{value.inspect}"
-        end
-    end
-
-    printable :array_port_format
-  end
-end