rggen-systemverilog 0.33.1 → 0.35.0

data/lib/rggen/systemverilog/rtl/bit_field/type/rw_rwtrg_w1.rb

@@ -4,17 +4,14 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rw, :rwtrg, :w1]) do
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:, array_size:
       }
       if rwtrg?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger", width: 1,
-          array_size: array_size, array_format: array_port_format
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger", width: 1,
-          array_size: array_size, array_format: array_port_format
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb

@@ -5,13 +5,11 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
     build do
       unless bit_field.reference?
         input :clear, {
-          name: "i_#{full_name}_clear", width: 1,
-          array_size: array_size, array_format: array_port_format
+          name: "i_#{full_name}_clear", width: 1, array_size:
         }
       end
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb

@@ -5,13 +5,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
     build do
       unless bit_field.reference?
         input :control, {
-          name: "i_#{full_name}_#{enable_or_lock}", width: 1,
-          array_size: array_size, array_format: array_port_format
+          name: "i_#{full_name}_#{enable_or_lock}", width: 1, array_size:
         }
       end
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/rwhw.rb

@@ -5,17 +5,14 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwhw) do
     build do
       unless bit_field.reference?
         input :valid, {
-          name: "i_#{full_name}_valid", width: 1,
-          array_size: array_size, array_format: array_port_format
+          name: "i_#{full_name}_valid", width: 1, array_size:
         }
       end
       input :value_in, {
-        name: "i_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "i_#{full_name}", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb

@@ -5,13 +5,11 @@ RgGen.define_list_item_feature(:bit_field, :type, :rws) do
     build do
       unless bit_field.reference?
         input :set, {
-          name: "i_#{full_name}_set", width: 1,
-          array_size: array_size, array_format: array_port_format
+          name: "i_#{full_name}_set", width: 1, array_size:
         }
       end
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb

@@ -6,8 +6,7 @@ RgGen.define_list_item_feature(
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb

@@ -4,8 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0t, :w1t]) do
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb

@@ -4,8 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
   sv_rtl do
     build do
       output :trigger, {
-        name: "o_#{full_name}_trigger", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}_trigger", width:, array_size:
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.rb

@@ -4,13 +4,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:wo, :wo1, :wotrg]) do
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:, array_size:
       }
       if wotrg?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger", width: 1,
-          array_size: array_size, array_format: array_port_format
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
       end
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb

@@ -4,8 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:wrc, :wrs]) do
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type.rb

@@ -9,10 +9,6 @@ RgGen.define_list_feature(:bit_field, :type) do
 
       private
 
-      def array_port_format
-        configuration.array_port_format
-      end
-
       def full_name
         bit_field.full_name('_')
       end
@@ -38,7 +34,7 @@ RgGen.define_list_feature(:bit_field, :type) do
       end
 
       def initial_value
-        index = bit_field.initial_value_array? && bit_field.local_index || nil
+        index = bit_field.initial_value_array? && loop_variables || nil
         bit_field.initial_value[index]
       end
 
@@ -50,7 +46,7 @@ RgGen.define_list_feature(:bit_field, :type) do
         bit_field.reference? &&
           bit_field
             .find_reference(register_block.bit_fields)
-            .value(bit_field.local_indices, bit_field.reference_width)
+            .value(bit_field.local_indexes, bit_field.reference_width)
       end
 
       def bit_field_if

data/lib/rggen/systemverilog/rtl/bit_field_index.rb

@@ -5,7 +5,7 @@ module RgGen
     module RTL
       module BitFieldIndex
         EXPORTED_METHODS = [
-          :local_index, :local_indices, :loop_variables, :array_size
+          :local_index, :local_indexes, :loop_variables, :flat_loop_index, :array_size
         ].freeze
 
         def self.included(feature)
@@ -18,8 +18,8 @@ module RgGen
           create_identifier(local_index_name)
         end
 
-        def local_indices
-          [*register.local_indices, local_index_name]
+        def local_indexes
+          [*register.local_indexes, local_index_name]
         end
 
         def loop_variables
@@ -27,13 +27,22 @@ module RgGen
             [*register.loop_variables, local_index].compact
         end
 
+        def flat_loop_index
+          return unless inside_loop?
+
+          size = array_size
+          factors =
+            Array.new(size.size) { |i| size[(i + 1)..].inject(1, :*) }
+          factors
+            .zip(loop_variables)
+            .map { |f, v| f == 1 && v || "#{f}*#{v}" }
+            .join('+')
+        end
+
         def array_size
-          (inside_loop? || nil) &&
-            [
-              *register_files.flat_map(&:array_size),
-              *register.array_size,
-              *bit_field.sequence_size
-            ].compact
+          return unless inside_loop?
+
+          [*register.array_size(hierarchical: true), *bit_field.sequence_size]
         end
 
         private

data/lib/rggen/systemverilog/rtl/feature.rb

@@ -6,32 +6,28 @@ module RgGen
       class Feature < Common::Feature
         private
 
-        def create_variable(data_type, attributes, &block)
-          DataObject.new(
-            :variable, attributes.merge(data_type: data_type), &block
-          )
+        def create_variable(data_type, attributes, &)
+          DataObject.new(:variable, attributes.merge(data_type:), &)
         end
 
-        def create_if_instance(_, attributes, &block)
-          InterfaceInstance.new(attributes, &block)
+        def create_if_instance(_, attributes, &)
+          InterfaceInstance.new(attributes, &)
         end
 
-        def create_port(direction, attributes, &block)
+        def create_port(direction, attributes, &)
           attributes =
             { data_type: 'logic' }
               .merge(attributes)
-              .merge(direction: direction)
-          DataObject.new(:argument, attributes, &block)
+              .merge(direction:)
+          DataObject.new(:argument, attributes, &)
         end
 
-        def create_if_port(_, attributes, &block)
-          InterfacePort.new(attributes, &block)
+        def create_if_port(_, attributes, &)
+          InterfacePort.new(attributes, &)
         end
 
-        def create_parameter(parameter_type, attributes, &block)
-          DataObject.new(
-            :parameter, attributes.merge(parameter_type: parameter_type), &block
-          )
+        def create_parameter(parameter_type, attributes, &)
+          DataObject.new(:parameter, attributes.merge(parameter_type:), &)
         end
 
         define_entity :logic, :create_variable, :variable, -> { component }

data/lib/rggen/systemverilog/rtl/register/type/external.rb

@@ -5,7 +5,7 @@ RgGen.define_list_item_feature(:register, :type, :external) do
     build do
       parameter :strobe_width, {
         name: "#{register.name}_strobe_width".upcase,
-        data_type: :int, default: configuration.bus_width / 8
+        data_type: :int, default: bus_width / 8
       }
       interface_port :bus_if, {
         name: "#{register.name}_bus_if",

data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb

@@ -1,21 +1,27 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
-  configuration do
+  register_map do
     verify(:component) do
-      error_condition { configuration.bus_width > 32 }
+      error_condition { register_block.bus_width > 32 }
       message do
-        'bus width over 32 bit is not supported: ' \
-        "#{configuration.bus_width}"
+        'bus width over 32 bits is not supported: ' \
+        "#{register_block.bus_width}"
+      end
+      position do
+        register_block.feature(:bus_width).position
       end
     end
 
     verify(:component) do
       error_condition { configuration.address_width > 32 }
       message do
-        'address width over 32 bit is not supported: ' \
+        'address width over 32 bits is not supported: ' \
         "#{configuration.address_width}"
       end
+      position do
+        configuration.feature(:address_width).position
+      end
     end
   end
 

data/lib/rggen/systemverilog/rtl/register_block/protocol/avalon.erb

@@ -0,0 +1,17 @@
+rggen_avalon_adapter #(
+  .ADDRESS_WIDTH        (<%= address_width %>),
+  .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
+  .BUS_WIDTH            (<%= bus_width %>),
+  .REGISTERS            (<%= total_registers %>),
+  .PRE_DECODE           (<%= pre_decode %>),
+  .BASE_ADDRESS         (<%= base_address %>),
+  .BYTE_SIZE            (<%= byte_size %>),
+  .ERROR_STATUS         (<%= error_status %>),
+  .DEFAULT_READ_DATA    (<%= default_read_data %>),
+  .INSERT_SLICER        (<%= insert_slicer %>)
+) u_adapter (
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
+  .avalon_if    (<%= avalon_if %>),
+  .register_if  (<%= register_if %>)
+);

data/lib/rggen/systemverilog/rtl/register_block/protocol/avalon.rb

@@ -0,0 +1,37 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :avalon) do
+  register_map do
+    verify(:component) do
+      error_condition { configuration.address_width > 64 }
+      message do
+        'address width over 64 bits is not supported: ' \
+        "#{configuration.address_width}"
+      end
+      position do
+        configuration.feature(:address_width).position
+      end
+    end
+
+    verify(:component) do
+      error_condition { register_block.bus_width > 1024 }
+      message do
+        'bus width over 1024 bits is not supported: ' \
+        "#{register_block.bus_width}"
+      end
+      position do
+        register_block.feature(:bus_width).position
+      end
+    end
+  end
+
+  sv_rtl do
+    build do
+      interface_port :avalon_if, {
+        name: 'avalon_if', interface_type: 'rggen_avalon_if', modport: 'agent'
+      }
+    end
+
+    main_code :register_block, from_template: true
+  end
+end

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb

@@ -1,12 +1,15 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
-  configuration do
+  register_map do
     verify(:component) do
-      error_condition { ![32, 64].include?(configuration.bus_width) }
+      error_condition { ![32, 64].include?(register_block.bus_width) }
       message do
         'bus width either 32 bit or 64 bit is only supported: ' \
-        "#{configuration.bus_width}"
+        "#{register_block.bus_width}"
+      end
+      position do
+        register_block.feature(:bus_width).position
       end
     end
   end

data/lib/rggen/systemverilog/rtl/register_block/protocol/native.erb

@@ -0,0 +1,19 @@
+rggen_native_adapter #(
+  .ADDRESS_WIDTH        (<%= address_width %>),
+  .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
+  .BUS_WIDTH            (<%= bus_width %>),
+  .STROBE_WIDTH         (<%= strobe_width %>),
+  .REGISTERS            (<%= total_registers %>),
+  .PRE_DECODE           (<%= pre_decode %>),
+  .BASE_ADDRESS         (<%= base_address %>),
+  .BYTE_SIZE            (<%= byte_size %>),
+  .USE_READ_STROBE      (<%= use_read_strobe %>),
+  .ERROR_STATUS         (<%= error_status %>),
+  .DEFAULT_READ_DATA    (<%= default_read_data %>),
+  .INSERT_SLICER        (<%= insert_slicer %>)
+) u_adapter (
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
+  .csrbus_if    (<%= csrbus_if %>),
+  .register_if  (<%= register_if %>)
+);

data/lib/rggen/systemverilog/rtl/register_block/protocol/native.rb

@@ -0,0 +1,19 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :native) do
+  sv_rtl do
+    build do
+      parameter :strobe_width, {
+        name: 'STROBE_WIDTH', data_type: :int, default: bus_width / 8
+      }
+      parameter :use_read_strobe, {
+        name: 'USE_READ_STROBE', data_type: :bit, default: 0
+      }
+      interface_port :csrbus_if, {
+        name: 'csrbus_if', interface_type: 'rggen_bus_if', modport: 'slave'
+      }
+    end
+
+    main_code :register_block, from_template: true
+  end
+end

data/lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.rb

@@ -1,12 +1,15 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:register_block, :protocol, :wishbone) do
-  configuration do
+  register_map do
     verify(:component) do
-      error_condition { configuration.bus_width > 64 }
+      error_condition { register_block.bus_width > 64 }
       message do
-        'bus width over 64 bit is not supported: ' \
-        "#{configuration.bus_width}"
+        'bus width over 64 bits is not supported: ' \
+        "#{register_block.bus_width}"
+      end
+      position do
+        register_block.feature(:bus_width).position
       end
     end
   end

data/lib/rggen/systemverilog/rtl/register_block/protocol.rb

@@ -6,57 +6,76 @@ RgGen.define_list_feature(:register_block, :protocol) do
       feature_registries << registry
     end
 
+    def default_protocol
+      available_protocols.first
+    end
+
+    def find_protocol(value)
+      available_protocols
+        .find { value.to_sym.casecmp?(_1) }
+    end
+
+    private
+
+    def feature_registries
+      @feature_registries ||= []
+    end
+
     def available_protocols
       feature_registries
         .map { |registry| registry.enabled_features(:protocol) }
         .inject(:&)
     end
+  end
 
-    private
+  [:configuration, :register_map].each do |component_type|
+    component(component_type) do
+      base_feature do
+        build { |protocol| @protocol = protocol }
+      end
 
-    def feature_registries
-      @feature_registries ||= []
+      default_feature do
+      end
+
+      factory do
+        convert_value do |value, position|
+          shared_context.find_protocol(value) ||
+            (error "unknown protocol: #{value.inspect}", position)
+        end
+      end
     end
   end
 
   configuration do
     base_feature do
       property :protocol
-      build { |protocol| @protocol = protocol }
       printable :protocol
     end
 
-    default_feature do
-    end
-
     factory do
-      convert_value do |value, position|
-        protocol = find_protocol(value)
-        protocol ||
-          (error "unknown protocol: #{value.inspect}", position)
-      end
-
       default_value do |position|
-        default_protocol ||
+        shared_context.default_protocol ||
           (error 'no protocols are available', position)
       end
 
       def target_feature_key(data)
         data.value
       end
+    end
+  end
 
-      private
-
-      def find_protocol(value)
-        available_protocols.find(&value.to_sym.method(:casecmp?))
-      end
+  register_map do
+    base_feature do
+      property :protocol, default: -> { configuration.protocol }
 
-      def default_protocol
-        available_protocols.first
+      def position
+        super || configuration.feature(:protocol).position
       end
+    end
 
-      def available_protocols
-        @available_protocols ||= shared_context.available_protocols
+    factory do
+      def target_feature_key(configuration, data)
+        data&.value || configuration.protocol
       end
     end
   end
@@ -91,7 +110,7 @@ RgGen.define_list_feature(:register_block, :protocol) do
       private
 
       def bus_width
-        configuration.bus_width
+        register_block.bus_width
       end
 
       def local_address_width
@@ -120,8 +139,8 @@ RgGen.define_list_feature(:register_block, :protocol) do
     end
 
     factory do
-      def target_feature_key(configuration, _register_block)
-        configuration.protocol
+      def target_feature_key(_configuration, register_block)
+        register_block.protocol
       end
     end
   end

data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb

@@ -34,7 +34,7 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
     end
 
     def bus_width
-      configuration.bus_width
+      register_block.bus_width
     end
 
     def body_code(code)

data/lib/rggen/systemverilog/rtl/register_index.rb

@@ -8,7 +8,7 @@ module RgGen
 
         EXPORTED_METHODS = [
           :loop_variables, :local_loop_variables,
-          :local_index, :local_indices,
+          :local_index, :local_indexes,
           :index, :inside_loop?
         ].freeze
 
@@ -45,15 +45,15 @@ module RgGen
               .join('+')
         end
 
-        def local_indices
-          [*upper_register_file&.local_indices, local_index]
+        def local_indexes
+          [*upper_register_file&.local_indexes, local_index]
         end
 
         def index(offset_or_offsets = nil)
           offset_or_offsets
             .then(&method(:index_operands))
             .then(&method(:partial_sums))
-            .then(&method(:reduce_indices))
+            .then(&method(:reduce_indexes))
         end
 
         def inside_loop?
@@ -84,11 +84,11 @@ module RgGen
           ]
         end
 
-        def reduce_indices(indices)
-          if indices.empty? || indices.all?(&method(:integer?))
-            indices.sum
+        def reduce_indexes(indexes)
+          if indexes.empty? || indexes.all?(&method(:integer?))
+            indexes.sum
           else
-            indices.join('+')
+            indexes.join('+')
           end
         end
 

data/lib/rggen/systemverilog/rtl/register_type.rb

@@ -21,7 +21,7 @@ module RgGen
         end
 
         def bus_width
-          configuration.bus_width
+          register_block.bus_width
         end
 
         def value_width