rggen-systemverilog 0.32.0 → 0.33.0

checksums.yaml

@@ -1,7 +1,7 @@
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 SHA256:
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-  data.tar.gz: a38e7790669fe49a736076383a627f87e6468e38635376f2a07e79ca1a372884
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+  data.tar.gz: cc255cc91600d54a8481b733fc80350b9b43a7d5f3dd9ea39cc4679bd9c1b6ab
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+  data.tar.gz: eb80eba307d0d6c3ee3c94f9e45cf2ca9b7dd19709b69868b2616851bfda3ea5848f96291742e990e135397e2e7d170a2fb420712d4ac226231b54a6a447a2dc

data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2019-2023 Taichi Ishitani
+Copyright (c) 2019-2024 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -34,7 +34,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
 
 ## Copyright & License
 
-Copyright © 2019-2023 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2019-2024 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/systemverilog/ral/bit_field/type/rof_rohw.rb

@@ -0,0 +1,5 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rof, :rohw]) do
+  sv_ral { access 'RO' }
+end

data/lib/rggen/systemverilog/ral/bit_field/type/rwc_rwhw_rws.rb

@@ -0,0 +1,5 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rwc, :rwhw, :rws]) do
+  sv_ral { access 'RW' }
+end

data/lib/rggen/systemverilog/ral.rb

@@ -23,11 +23,11 @@ RgGen.setup_plugin :'rggen-sv-ral' do |plugin|
     'ral/register/type/indirect',
     'ral/bit_field/type',
     'ral/bit_field/type/custom',
-    'ral/bit_field/type/rof_rol',
+    'ral/bit_field/type/rof_rohw',
     'ral/bit_field/type/rotrg_rwtrg_wotrg',
     'ral/bit_field/type/row0trg_row1trg_w0trg_w1trg',
     'ral/bit_field/type/rowo_rowotrg',
-    'ral/bit_field/type/rwc_rws',
+    'ral/bit_field/type/rwc_rwhw_rws',
     'ral/bit_field/type/rwe_rwl'
   ]
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/{rol.erb → rohw.erb}

@@ -9,7 +9,7 @@ rggen_bit_field #(
   .o_write_trigger    (),
   .o_read_trigger     (),
   .i_sw_write_enable  ('1),
-  .i_hw_write_enable  (<%= latch_signal %>),
+  .i_hw_write_enable  (<%= valid_signal %>),
   .i_hw_write_data    (<%= value_in[loop_variables] %>),
   .i_hw_set           ('0),
   .i_hw_clear         ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/{rol.rb → rohw.rb}

@@ -1,11 +1,11 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, :rol) do
+RgGen.define_list_item_feature(:bit_field, :type, :rohw) do
   sv_rtl do
     build do
       unless bit_field.reference?
-        input :latch, {
-          name: "i_#{full_name}_latch", width: 1,
+        input :valid, {
+          name: "i_#{full_name}_valid", width: 1,
           array_size: array_size, array_format: array_port_format
         }
       end
@@ -23,8 +23,8 @@ RgGen.define_list_item_feature(:bit_field, :type, :rol) do
 
     private
 
-    def latch_signal
-      reference_bit_field || latch[loop_variables]
+    def valid_signal
+      reference_bit_field || valid[loop_variables]
     end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/rwhw.erb

@@ -0,0 +1,19 @@
+rggen_bit_field #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  (<%= valid_signal %>),
+  .i_hw_write_data    (<%= value_in[loop_variables] %>),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/rwhw.rb

@@ -0,0 +1,30 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rwhw) do
+  sv_rtl do
+    build do
+      unless bit_field.reference?
+        input :valid, {
+          name: "i_#{full_name}_valid", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      input :value_in, {
+        name: "i_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+      output :value_out, {
+        name: "o_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def valid_signal
+      reference_bit_field || valid[loop_variables]
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb

@@ -1,6 +1,7 @@
 rggen_bit_field #(
   .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
+  .INITIAL_VALUE  (<%= initial_value %>),
+  .HW_SET_WIDTH   (1)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
@@ -8,9 +9,9 @@ rggen_bit_field #(
   .o_write_trigger    (),
   .o_read_trigger     (),
   .i_sw_write_enable  ('1),
-  .i_hw_write_enable  (<%= set_signal %>),
-  .i_hw_write_data    (<%= value_in[loop_variables] %>),
-  .i_hw_set           ('0),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           (<%= set_signal %>),
   .i_hw_clear         ('0),
   .i_value            ('0),
   .i_mask             ('1),

data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb

@@ -9,10 +9,6 @@ RgGen.define_list_item_feature(:bit_field, :type, :rws) do
           array_size: array_size, array_format: array_port_format
         }
       end
-      input :value_in, {
-        name: "i_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
-      }
       output :value_out, {
         name: "o_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format

data/lib/rggen/systemverilog/rtl.rb

@@ -38,13 +38,14 @@ RgGen.setup_plugin :'rggen-sv-rtl' do |plugin|
     'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
     'rtl/bit_field/type/ro_rotrg',
     'rtl/bit_field/type/rof',
-    'rtl/bit_field/type/rol',
+    'rtl/bit_field/type/rohw',
     'rtl/bit_field/type/row0trg_row1trg',
     'rtl/bit_field/type/rowo_rowotrg',
     'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
     'rtl/bit_field/type/rw_rwtrg_w1',
     'rtl/bit_field/type/rwc',
     'rtl/bit_field/type/rwe_rwl',
+    'rtl/bit_field/type/rwhw',
     'rtl/bit_field/type/rws',
     'rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
     'rtl/bit_field/type/w0t_w1t',

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.32.0'
+    VERSION = '0.33.0'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.32.0
+  version: 0.33.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2023-12-28 00:00:00.000000000 Z
+date: 2024-01-22 00:00:00.000000000 Z
 dependencies: []
 description: 'SystemVerilog RTL and UVM RAL model generators for RgGen.
 
@@ -42,11 +42,11 @@ files:
 - lib/rggen/systemverilog/ral.rb
 - lib/rggen/systemverilog/ral/bit_field/type.rb
 - lib/rggen/systemverilog/ral/bit_field/type/custom.rb
-- lib/rggen/systemverilog/ral/bit_field/type/rof_rol.rb
+- lib/rggen/systemverilog/ral/bit_field/type/rof_rohw.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rotrg_rwtrg_wotrg.rb
 - lib/rggen/systemverilog/ral/bit_field/type/row0trg_row1trg_w0trg_w1trg.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rowo_rowotrg.rb
-- lib/rggen/systemverilog/ral/bit_field/type/rwc_rws.rb
+- lib/rggen/systemverilog/ral/bit_field/type/rwc_rwhw_rws.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb
 - lib/rggen/systemverilog/ral/feature.rb
 - lib/rggen/systemverilog/ral/register/type.rb
@@ -71,8 +71,8 @@ files:
 - lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/rol.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/rol.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rohw.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rohw.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.erb
@@ -85,6 +85,8 @@ files:
 - lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rwhw.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rwhw.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rws.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rws.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb
@@ -155,5 +157,5 @@ requirements: []
 rubygems_version: 3.5.3
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.32.0
+summary: rggen-systemverilog-0.33.0
 test_files: []

data/lib/rggen/systemverilog/ral/bit_field/type/rof_rol.rb

@@ -1,5 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, [:rof, :rol]) do
-  sv_ral { access 'RO' }
-end

data/lib/rggen/systemverilog/ral/bit_field/type/rwc_rws.rb

@@ -1,5 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, [:rwc, :rws]) do
-  sv_ral { access 'RW' }
-end