rggen-systemverilog 0.32.0 → 0.33.0

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
checksums.yaml CHANGED
@@ -1,7 +1,7 @@
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data/LICENSE CHANGED
@@ -1,6 +1,6 @@
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  The MIT License (MIT)
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- Copyright (c) 2019-2023 Taichi Ishitani
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+ Copyright (c) 2019-2024 Taichi Ishitani
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  Permission is hereby granted, free of charge, to any person obtaining a copy
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  of this software and associated documentation files (the "Software"), to deal
data/README.md CHANGED
@@ -34,7 +34,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
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  ## Copyright & License
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- Copyright © 2019-2023 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
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+ Copyright © 2019-2024 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
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  ## Code of Conduct
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@@ -0,0 +1,5 @@
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+ # frozen_string_literal: true
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+
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+ RgGen.define_list_item_feature(:bit_field, :type, [:rof, :rohw]) do
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+ sv_ral { access 'RO' }
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+ end
@@ -0,0 +1,5 @@
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+ # frozen_string_literal: true
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+
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+ RgGen.define_list_item_feature(:bit_field, :type, [:rwc, :rwhw, :rws]) do
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+ sv_ral { access 'RW' }
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+ end
@@ -23,11 +23,11 @@ RgGen.setup_plugin :'rggen-sv-ral' do |plugin|
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  'ral/register/type/indirect',
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  'ral/bit_field/type',
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  'ral/bit_field/type/custom',
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- 'ral/bit_field/type/rof_rol',
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+ 'ral/bit_field/type/rof_rohw',
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  'ral/bit_field/type/rotrg_rwtrg_wotrg',
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  'ral/bit_field/type/row0trg_row1trg_w0trg_w1trg',
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  'ral/bit_field/type/rowo_rowotrg',
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- 'ral/bit_field/type/rwc_rws',
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+ 'ral/bit_field/type/rwc_rwhw_rws',
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  'ral/bit_field/type/rwe_rwl'
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  ]
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  end
@@ -9,7 +9,7 @@ rggen_bit_field #(
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  .o_write_trigger (),
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  .o_read_trigger (),
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  .i_sw_write_enable ('1),
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- .i_hw_write_enable (<%= latch_signal %>),
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+ .i_hw_write_enable (<%= valid_signal %>),
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  .i_hw_write_data (<%= value_in[loop_variables] %>),
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  .i_hw_set ('0),
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  .i_hw_clear ('0),
@@ -1,11 +1,11 @@
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  # frozen_string_literal: true
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- RgGen.define_list_item_feature(:bit_field, :type, :rol) do
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+ RgGen.define_list_item_feature(:bit_field, :type, :rohw) do
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  sv_rtl do
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  build do
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  unless bit_field.reference?
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- input :latch, {
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- name: "i_#{full_name}_latch", width: 1,
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+ input :valid, {
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+ name: "i_#{full_name}_valid", width: 1,
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  array_size: array_size, array_format: array_port_format
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  }
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  end
@@ -23,8 +23,8 @@ RgGen.define_list_item_feature(:bit_field, :type, :rol) do
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  private
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- def latch_signal
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- reference_bit_field || latch[loop_variables]
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+ def valid_signal
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+ reference_bit_field || valid[loop_variables]
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  end
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  end
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  end
@@ -0,0 +1,19 @@
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+ rggen_bit_field #(
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+ .WIDTH (<%= width %>),
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+ .INITIAL_VALUE (<%= initial_value %>)
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+ ) u_bit_field (
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+ .i_clk (<%= clock %>),
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+ .i_rst_n (<%= reset %>),
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+ .bit_field_if (<%= bit_field_if %>),
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+ .o_write_trigger (),
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+ .o_read_trigger (),
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+ .i_sw_write_enable ('1),
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+ .i_hw_write_enable (<%= valid_signal %>),
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+ .i_hw_write_data (<%= value_in[loop_variables] %>),
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+ .i_hw_set ('0),
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+ .i_hw_clear ('0),
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+ .i_value ('0),
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+ .i_mask ('1),
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+ .o_value (<%= value_out[loop_variables] %>),
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+ .o_value_unmasked ()
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+ );
@@ -0,0 +1,30 @@
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+ # frozen_string_literal: true
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+
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+ RgGen.define_list_item_feature(:bit_field, :type, :rwhw) do
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+ sv_rtl do
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+ build do
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+ unless bit_field.reference?
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+ input :valid, {
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+ name: "i_#{full_name}_valid", width: 1,
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+ array_size: array_size, array_format: array_port_format
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+ }
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+ end
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+ input :value_in, {
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+ name: "i_#{full_name}", width: width,
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+ array_size: array_size, array_format: array_port_format
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+ }
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+ output :value_out, {
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+ name: "o_#{full_name}", width: width,
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+ array_size: array_size, array_format: array_port_format
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+ }
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+ end
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+
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+ main_code :bit_field, from_template: true
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+
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+ private
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+
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+ def valid_signal
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+ reference_bit_field || valid[loop_variables]
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+ end
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+ end
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+ end
@@ -1,6 +1,7 @@
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  rggen_bit_field #(
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  .WIDTH (<%= width %>),
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- .INITIAL_VALUE (<%= initial_value %>)
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+ .INITIAL_VALUE (<%= initial_value %>),
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+ .HW_SET_WIDTH (1)
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  ) u_bit_field (
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  .i_clk (<%= clock %>),
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  .i_rst_n (<%= reset %>),
@@ -8,9 +9,9 @@ rggen_bit_field #(
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  .o_write_trigger (),
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  .o_read_trigger (),
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  .i_sw_write_enable ('1),
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- .i_hw_write_enable (<%= set_signal %>),
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- .i_hw_write_data (<%= value_in[loop_variables] %>),
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- .i_hw_set ('0),
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+ .i_hw_write_enable ('0),
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+ .i_hw_write_data ('0),
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+ .i_hw_set (<%= set_signal %>),
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  .i_hw_clear ('0),
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  .i_value ('0),
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  .i_mask ('1),
@@ -9,10 +9,6 @@ RgGen.define_list_item_feature(:bit_field, :type, :rws) do
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  array_size: array_size, array_format: array_port_format
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  }
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  end
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- input :value_in, {
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- name: "i_#{full_name}", width: width,
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- array_size: array_size, array_format: array_port_format
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- }
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  output :value_out, {
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  name: "o_#{full_name}", width: width,
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  array_size: array_size, array_format: array_port_format
@@ -38,13 +38,14 @@ RgGen.setup_plugin :'rggen-sv-rtl' do |plugin|
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  'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
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  'rtl/bit_field/type/ro_rotrg',
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  'rtl/bit_field/type/rof',
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- 'rtl/bit_field/type/rol',
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+ 'rtl/bit_field/type/rohw',
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  'rtl/bit_field/type/row0trg_row1trg',
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  'rtl/bit_field/type/rowo_rowotrg',
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  'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
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  'rtl/bit_field/type/rw_rwtrg_w1',
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  'rtl/bit_field/type/rwc',
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  'rtl/bit_field/type/rwe_rwl',
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+ 'rtl/bit_field/type/rwhw',
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  'rtl/bit_field/type/rws',
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  'rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
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  'rtl/bit_field/type/w0t_w1t',
@@ -2,6 +2,6 @@
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  module RgGen
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  module SystemVerilog
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- VERSION = '0.32.0'
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+ VERSION = '0.33.0'
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  end
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  end
metadata CHANGED
@@ -1,14 +1,14 @@
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  --- !ruby/object:Gem::Specification
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  name: rggen-systemverilog
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  version: !ruby/object:Gem::Version
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- version: 0.32.0
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+ version: 0.33.0
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  platform: ruby
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  authors:
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  - Taichi Ishitani
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  autorequire:
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  bindir: bin
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  cert_chain: []
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- date: 2023-12-28 00:00:00.000000000 Z
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+ date: 2024-01-22 00:00:00.000000000 Z
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  dependencies: []
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  description: 'SystemVerilog RTL and UVM RAL model generators for RgGen.
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@@ -42,11 +42,11 @@ files:
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  - lib/rggen/systemverilog/ral.rb
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  - lib/rggen/systemverilog/ral/bit_field/type.rb
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  - lib/rggen/systemverilog/ral/bit_field/type/custom.rb
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- - lib/rggen/systemverilog/ral/bit_field/type/rof_rol.rb
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+ - lib/rggen/systemverilog/ral/bit_field/type/rof_rohw.rb
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  - lib/rggen/systemverilog/ral/bit_field/type/rotrg_rwtrg_wotrg.rb
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  - lib/rggen/systemverilog/ral/bit_field/type/row0trg_row1trg_w0trg_w1trg.rb
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  - lib/rggen/systemverilog/ral/bit_field/type/rowo_rowotrg.rb
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- - lib/rggen/systemverilog/ral/bit_field/type/rwc_rws.rb
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+ - lib/rggen/systemverilog/ral/bit_field/type/rwc_rwhw_rws.rb
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  - lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb
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  - lib/rggen/systemverilog/ral/feature.rb
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  - lib/rggen/systemverilog/ral/register/type.rb
@@ -71,8 +71,8 @@ files:
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  - lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb
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  - lib/rggen/systemverilog/rtl/bit_field/type/rof.erb
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  - lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
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- - lib/rggen/systemverilog/rtl/bit_field/type/rol.erb
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- - lib/rggen/systemverilog/rtl/bit_field/type/rol.rb
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+ - lib/rggen/systemverilog/rtl/bit_field/type/rohw.erb
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+ - lib/rggen/systemverilog/rtl/bit_field/type/rohw.rb
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  - lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.erb
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  - lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.rb
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  - lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.erb
@@ -85,6 +85,8 @@ files:
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  - lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb
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  - lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.erb
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  - lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb
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+ - lib/rggen/systemverilog/rtl/bit_field/type/rwhw.erb
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+ - lib/rggen/systemverilog/rtl/bit_field/type/rwhw.rb
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  - lib/rggen/systemverilog/rtl/bit_field/type/rws.erb
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  - lib/rggen/systemverilog/rtl/bit_field/type/rws.rb
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  - lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb
@@ -155,5 +157,5 @@ requirements: []
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  rubygems_version: 3.5.3
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  signing_key:
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  specification_version: 4
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- summary: rggen-systemverilog-0.32.0
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+ summary: rggen-systemverilog-0.33.0
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  test_files: []
@@ -1,5 +0,0 @@
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- # frozen_string_literal: true
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-
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- RgGen.define_list_item_feature(:bit_field, :type, [:rof, :rol]) do
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- sv_ral { access 'RO' }
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- end
@@ -1,5 +0,0 @@
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- # frozen_string_literal: true
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-
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- RgGen.define_list_item_feature(:bit_field, :type, [:rwc, :rws]) do
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- sv_ral { access 'RW' }
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- end