rggen-systemverilog 0.28.0 → 0.30.0
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- checksums.yaml +4 -4
- data/LICENSE +1 -1
- data/README.md +1 -1
- data/lib/rggen/systemverilog/common/utility/package_definition.rb +12 -4
- data/lib/rggen/systemverilog/ral/register_common.rb +1 -1
- data/lib/rggen/systemverilog/rtl/partial_sum.rb +5 -1
- data/lib/rggen/systemverilog/rtl/register/type/default.erb +1 -2
- data/lib/rggen/systemverilog/rtl/register/type/external.rb +2 -3
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb +2 -1
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb +1 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.erb +1 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +3 -0
- data/lib/rggen/systemverilog/rtl/register_index.rb +7 -1
- data/lib/rggen/systemverilog/rtl/register_type.rb +16 -6
- data/lib/rggen/systemverilog/rtl.rb +14 -0
- data/lib/rggen/systemverilog/rtl_package/bit_field/sv_rtl_package.rb +65 -0
- data/lib/rggen/systemverilog/rtl_package/feature.rb +28 -0
- data/lib/rggen/systemverilog/rtl_package/register/sv_rtl_package.rb +83 -0
- data/lib/rggen/systemverilog/rtl_package/register_block/sv_rtl_package.rb +25 -0
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +9 -5
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA256:
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-
metadata.gz:
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data.tar.gz:
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+
metadata.gz: 3485ee878c14865b7457588e96b43fb62e07e7a699204fe5b5f2e4082b143296
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data.tar.gz: e4b82e5b367666fe0f1d9f62dd4d647348363bcee8f6749032010cc1ee20bd53
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 960d4b3469f87ab1d75c74790a56ded92dfc4e12d38a9dadd6a97cb01ea5c4a003cdf9fd347ab998aa9d72d631fc039cfb9a7aa34e76e6445ad11a80e768f231
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+
data.tar.gz: b27c8a3e1a6ae7c3e10f4031cf486b57654c6d62df379908cb0e72c9d6a2c069ab66009e6f8dc649be9e3f0119ddab79ad26d7993a621c44271548eccf7265bb
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data/LICENSE
CHANGED
@@ -1,6 +1,6 @@
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1
1
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The MIT License (MIT)
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2
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-
Copyright (c) 2019-
|
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+
Copyright (c) 2019-2023 Taichi Ishitani
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5
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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data/README.md
CHANGED
@@ -35,7 +35,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
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## Copyright & License
|
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-
Copyright © 2019-
|
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+
Copyright © 2019-2023 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
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## Code of Conduct
|
41
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@@ -8,6 +8,7 @@ module RgGen
|
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8
8
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define_attribute :name
|
9
9
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define_attribute :package_imports
|
10
10
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define_attribute :include_files
|
11
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+
define_attribute :parameters
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12
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def package_imports(packages)
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@package_imports ||= []
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@@ -36,21 +37,28 @@ module RgGen
|
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36
37
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def pre_body_code(code)
|
37
38
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package_import_declaration(code)
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38
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file_include_directives(code)
|
40
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+
parameter_declarations(code)
|
39
41
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end
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def package_import_declaration(code)
|
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declarations =
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-
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-
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-
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+
@package_imports
|
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+
&.map { |package| ['import', space, package, '::*'] }
|
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+
declarations &&
|
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+
add_declarations_to_body(code, declarations)
|
46
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end
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|
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def file_include_directives(code)
|
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-
|
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+
@include_files&.each do |file|
|
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code << ['`include', space, string(file), nl]
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end
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end
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+
def parameter_declarations(code)
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+
parameters &&
|
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add_declarations_to_body(code, parameters)
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+
end
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+
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def footer_code
|
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'endpackage'
|
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end
|
@@ -10,7 +10,7 @@ module RgGen
|
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operands
|
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.chunk(&method(:integer?))
|
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.flat_map(&method(:calc_partial_sum))
|
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-
.reject
|
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+
.reject(&method(:integer_zero?))
|
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.tap { |sums| sums.empty? && (sums << 0) }
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end
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@@ -22,6 +22,10 @@ module RgGen
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def integer?(value)
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value.is_a?(Integer)
|
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end
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+
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+
def integer_zero?(value)
|
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integer?(value) && value.zero?
|
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+
end
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end
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end
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end
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@@ -4,8 +4,7 @@ rggen_default_register #(
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4
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.ADDRESS_WIDTH (<%= address_width %>),
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.OFFSET_ADDRESS (<%= offset_address %>),
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.BUS_WIDTH (<%= bus_width %>),
|
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-
.DATA_WIDTH (<%= width %>)
|
8
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-
.REGISTER_INDEX (<%= register_index %>)
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+
.DATA_WIDTH (<%= width %>)
|
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8
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) u_register (
|
10
9
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.i_clk (<%= register_block.clock %>),
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10
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.i_rst_n (<%= register_block.reset %>),
|
@@ -19,12 +19,11 @@ RgGen.define_list_item_feature(:register, :type, :external) do
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end
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def start_address
|
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-
hex(register.
|
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+
hex(register.address_range.begin, address_width)
|
23
23
|
end
|
24
24
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|
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25
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def end_address
|
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-
|
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-
hex(address, address_width)
|
26
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+
hex(register.address_range.last, address_width)
|
28
27
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end
|
29
28
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end
|
30
29
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end
|
@@ -7,7 +7,8 @@ rggen_apb_adapter #(
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7
7
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.BASE_ADDRESS (<%= base_address %>),
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8
8
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.BYTE_SIZE (<%= byte_size %>),
|
9
9
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.ERROR_STATUS (<%= error_status %>),
|
10
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-
.DEFAULT_READ_DATA (<%= default_read_data %>)
|
10
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+
.DEFAULT_READ_DATA (<%= default_read_data %>),
|
11
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+
.INSERT_SLICER (<%= insert_slicer %>)
|
11
12
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) u_adapter (
|
12
13
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.i_clk (<%= clock %>),
|
13
14
|
.i_rst_n (<%= reset %>),
|
@@ -9,6 +9,7 @@ rggen_axi4lite_adapter #(
|
|
9
9
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.BYTE_SIZE (<%= byte_size %>),
|
10
10
|
.ERROR_STATUS (<%= error_status %>),
|
11
11
|
.DEFAULT_READ_DATA (<%= default_read_data %>),
|
12
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+
.INSERT_SLICER (<%= insert_slicer %>),
|
12
13
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.WRITE_FIRST (<%= write_first %>)
|
13
14
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) u_adapter (
|
14
15
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.i_clk (<%= clock %>),
|
@@ -89,6 +89,9 @@ RgGen.define_list_feature(:register_block, :protocol) do
|
|
89
89
|
name: 'DEFAULT_READ_DATA', data_type: :bit, width: bus_width,
|
90
90
|
default: all_bits_0
|
91
91
|
}
|
92
|
+
parameter :insert_slicer, {
|
93
|
+
name: 'INSERT_SLICER', data_type: :bit, width: 1, default: 0
|
94
|
+
}
|
92
95
|
end
|
93
96
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|
94
97
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private
|
@@ -102,7 +102,13 @@ module RgGen
|
|
102
102
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operands.reduce(:*)
|
103
103
|
elsif operands.first == 1
|
104
104
|
operands.last
|
105
|
-
|
105
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+
else
|
106
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+
product_expression(operands, need_bracket)
|
107
|
+
end
|
108
|
+
end
|
109
|
+
|
110
|
+
def product_expression(operands, need_bracket)
|
111
|
+
if need_bracket && /[+\-*\/]/ =~ operands.last
|
106
112
|
"#{operands.first}*(#{operands.last})"
|
107
113
|
else
|
108
114
|
operands.join('*')
|
@@ -32,15 +32,29 @@ module RgGen
|
|
32
32
|
end
|
33
33
|
|
34
34
|
def collect_offsets(component)
|
35
|
-
if
|
35
|
+
if need_byte_offset?(component)
|
36
36
|
[component.offset_address, byte_offset(component)]
|
37
37
|
else
|
38
38
|
component.offset_address
|
39
39
|
end
|
40
40
|
end
|
41
41
|
|
42
|
+
def need_byte_offset?(component)
|
43
|
+
if component.register_file?
|
44
|
+
component.array?
|
45
|
+
else
|
46
|
+
component.array? && !component.settings[:support_shared_address]
|
47
|
+
end
|
48
|
+
end
|
49
|
+
|
42
50
|
def byte_offset(component)
|
43
|
-
|
51
|
+
byte_size = component.entry_byte_size
|
52
|
+
local_index = component.local_index
|
53
|
+
if /[+\-*\/]/ =~ local_index
|
54
|
+
"#{byte_size}*(#{local_index})"
|
55
|
+
else
|
56
|
+
"#{byte_size}*#{local_index}"
|
57
|
+
end
|
44
58
|
end
|
45
59
|
|
46
60
|
def format_offsets(offsets)
|
@@ -59,10 +73,6 @@ module RgGen
|
|
59
73
|
bits = register.bit_fields.map(&:bit_map).inject(:|)
|
60
74
|
hex(bits, register.width)
|
61
75
|
end
|
62
|
-
|
63
|
-
def register_index
|
64
|
-
register.local_index || 0
|
65
|
-
end
|
66
76
|
end
|
67
77
|
end
|
68
78
|
end
|
@@ -7,6 +7,7 @@ require_relative 'rtl/register_index'
|
|
7
7
|
require_relative 'rtl/register_type'
|
8
8
|
require_relative 'rtl/indirect_index'
|
9
9
|
require_relative 'rtl/bit_field_index'
|
10
|
+
require_relative 'rtl_package/feature'
|
10
11
|
|
11
12
|
RgGen.setup_plugin :'rggen-sv-rtl' do |plugin|
|
12
13
|
plugin.version RgGen::SystemVerilog::VERSION
|
@@ -50,4 +51,17 @@ RgGen.setup_plugin :'rggen-sv-rtl' do |plugin|
|
|
50
51
|
'rtl/bit_field/type/wo_wo1_wotrg',
|
51
52
|
'rtl/bit_field/type/wrc_wrs'
|
52
53
|
]
|
54
|
+
|
55
|
+
plugin.register_component :sv_rtl_package do
|
56
|
+
component RgGen::SystemVerilog::Common::Component,
|
57
|
+
RgGen::SystemVerilog::Common::ComponentFactory
|
58
|
+
feature RgGen::SystemVerilog::RTLPackage::Feature,
|
59
|
+
RgGen::SystemVerilog::Common::FeatureFactory
|
60
|
+
end
|
61
|
+
|
62
|
+
plugin.files [
|
63
|
+
'rtl_package/bit_field/sv_rtl_package',
|
64
|
+
'rtl_package/register/sv_rtl_package',
|
65
|
+
'rtl_package/register_block/sv_rtl_package'
|
66
|
+
]
|
53
67
|
end
|
@@ -0,0 +1,65 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
RgGen.define_simple_feature(:bit_field, :sv_rtl_package) do
|
4
|
+
sv_rtl_package do
|
5
|
+
build do
|
6
|
+
localparam :__width, {
|
7
|
+
name: "#{full_name}_bit_width",
|
8
|
+
data_type: :int, default: bit_field.width
|
9
|
+
}
|
10
|
+
localparam :__mask, {
|
11
|
+
name: "#{full_name}_bit_mask",
|
12
|
+
data_type: :bit, width: bit_field.width, default: mask_value
|
13
|
+
}
|
14
|
+
define_offset_localparam
|
15
|
+
define_label_localparams
|
16
|
+
end
|
17
|
+
|
18
|
+
private
|
19
|
+
|
20
|
+
def mask_value
|
21
|
+
hex((1 << bit_field.width) - 1, bit_field.width)
|
22
|
+
end
|
23
|
+
|
24
|
+
def define_offset_localparam
|
25
|
+
if bit_field.sequential?
|
26
|
+
define_sequential_offset_localparam
|
27
|
+
else
|
28
|
+
define_single_offset_localparam
|
29
|
+
end
|
30
|
+
end
|
31
|
+
|
32
|
+
def define_sequential_offset_localparam
|
33
|
+
size = bit_field.sequence_size
|
34
|
+
localparam :__offset, {
|
35
|
+
name: "#{full_name}_bit_offset",
|
36
|
+
data_type: :int, array_size: [size], default: offset_value(size)
|
37
|
+
}
|
38
|
+
end
|
39
|
+
|
40
|
+
def offset_value(size)
|
41
|
+
array(Array.new(size, &bit_field.method(:lsb)))
|
42
|
+
end
|
43
|
+
|
44
|
+
def define_single_offset_localparam
|
45
|
+
localparam :__offset, {
|
46
|
+
name: "#{full_name}_bit_offset",
|
47
|
+
data_type: :int, default: bit_field.lsb
|
48
|
+
}
|
49
|
+
end
|
50
|
+
|
51
|
+
def define_label_localparams
|
52
|
+
bit_field.labels
|
53
|
+
.each { |label| define_label_localparam(label) }
|
54
|
+
end
|
55
|
+
|
56
|
+
def define_label_localparam(label)
|
57
|
+
identifier = "label_#{label.name}".downcase.to_sym
|
58
|
+
value = hex(label.value, bit_field.width)
|
59
|
+
localparam identifier, {
|
60
|
+
name: "#{full_name}_#{label.name}",
|
61
|
+
data_type: :bit, width: bit_field.width, default: value
|
62
|
+
}
|
63
|
+
end
|
64
|
+
end
|
65
|
+
end
|
@@ -0,0 +1,28 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
module RgGen
|
4
|
+
module SystemVerilog
|
5
|
+
module RTLPackage
|
6
|
+
class Feature < Common::Feature
|
7
|
+
private
|
8
|
+
|
9
|
+
def full_name(separator = '_')
|
10
|
+
component.full_name(separator)
|
11
|
+
end
|
12
|
+
|
13
|
+
def create_parameter(parameter_type, attributes, &block)
|
14
|
+
attributes =
|
15
|
+
attributes.merge(
|
16
|
+
parameter_type: parameter_type, array_format: :unpacked,
|
17
|
+
name: attributes[:name].upcase
|
18
|
+
)
|
19
|
+
DataObject.new(
|
20
|
+
:parameter, attributes, &block
|
21
|
+
)
|
22
|
+
end
|
23
|
+
|
24
|
+
define_entity :localparam, :create_parameter, :parameter, -> { register_block }
|
25
|
+
end
|
26
|
+
end
|
27
|
+
end
|
28
|
+
end
|
@@ -0,0 +1,83 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
RgGen.define_simple_feature(:register, :sv_rtl_package) do
|
4
|
+
sv_rtl_package do
|
5
|
+
build do
|
6
|
+
localparam :__byte_width, {
|
7
|
+
name: "#{full_name}_byte_width",
|
8
|
+
data_type: :int, default: register.byte_width
|
9
|
+
}
|
10
|
+
localparam :__byte_size, {
|
11
|
+
name: "#{full_name}_byte_size",
|
12
|
+
data_type: :int, default: register.total_byte_size(hierarchical: true)
|
13
|
+
}
|
14
|
+
define_array_size_localparam
|
15
|
+
define_offset_localparams
|
16
|
+
end
|
17
|
+
|
18
|
+
private
|
19
|
+
|
20
|
+
def define_array_size_localparam
|
21
|
+
return unless array?
|
22
|
+
|
23
|
+
list = array_size_list
|
24
|
+
localparam :__array_size, {
|
25
|
+
name: "#{full_name}_array_size",
|
26
|
+
data_type: :int, array_size: [list.size], default: array(list)
|
27
|
+
}
|
28
|
+
end
|
29
|
+
|
30
|
+
def define_offset_localparams
|
31
|
+
if array?
|
32
|
+
define_array_offset_localparams
|
33
|
+
else
|
34
|
+
define_single_offset_localparam
|
35
|
+
end
|
36
|
+
end
|
37
|
+
|
38
|
+
def define_array_offset_localparams
|
39
|
+
width = register_block.local_address_width
|
40
|
+
size_list = array_size_list
|
41
|
+
value_list = group_address_list(address_list, size_list).first
|
42
|
+
localparam :__offset, {
|
43
|
+
name: "#{full_name}_byte_offset",
|
44
|
+
data_type: :bit, width: width, array_size: size_list, default: value_list
|
45
|
+
}
|
46
|
+
end
|
47
|
+
|
48
|
+
def address_list
|
49
|
+
register
|
50
|
+
.expanded_offset_addresses
|
51
|
+
.map { |address| hex(address, register_block.local_address_width) }
|
52
|
+
end
|
53
|
+
|
54
|
+
def group_address_list(address_list, size_list)
|
55
|
+
list =
|
56
|
+
if size_list.size > 1
|
57
|
+
group_address_list(address_list, size_list[1..])
|
58
|
+
else
|
59
|
+
address_list
|
60
|
+
end
|
61
|
+
list
|
62
|
+
.each_slice(size_list.first)
|
63
|
+
.map(&method(:array))
|
64
|
+
end
|
65
|
+
|
66
|
+
def define_single_offset_localparam
|
67
|
+
width = register_block.local_address_width
|
68
|
+
value = address_list.first
|
69
|
+
localparam :__offset, {
|
70
|
+
name: "#{full_name}_byte_offset",
|
71
|
+
data_type: :bit, width: width, default: value
|
72
|
+
}
|
73
|
+
end
|
74
|
+
|
75
|
+
def array?
|
76
|
+
register.array?(hierarchical: true)
|
77
|
+
end
|
78
|
+
|
79
|
+
def array_size_list
|
80
|
+
register.array_size(hierarchical: true)
|
81
|
+
end
|
82
|
+
end
|
83
|
+
end
|
@@ -0,0 +1,25 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
RgGen.define_simple_feature(:register_block, :sv_rtl_package) do
|
4
|
+
sv_rtl_package do
|
5
|
+
write_file '<%= package_name %>.sv' do |file|
|
6
|
+
file.body { sv_rtl_package_definition }
|
7
|
+
end
|
8
|
+
|
9
|
+
private
|
10
|
+
|
11
|
+
def sv_rtl_package_definition
|
12
|
+
package_definition(package_name) do |package|
|
13
|
+
package.parameters parameters
|
14
|
+
end
|
15
|
+
end
|
16
|
+
|
17
|
+
def package_name
|
18
|
+
"#{register_block.name}_rtl_pkg"
|
19
|
+
end
|
20
|
+
|
21
|
+
def parameters
|
22
|
+
register_block.declarations[:parameter]
|
23
|
+
end
|
24
|
+
end
|
25
|
+
end
|
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: rggen-systemverilog
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 0.
|
4
|
+
version: 0.30.0
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Taichi Ishitani
|
8
8
|
autorequire:
|
9
9
|
bindir: bin
|
10
10
|
cert_chain: []
|
11
|
-
date:
|
11
|
+
date: 2023-04-28 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: bundler
|
@@ -135,6 +135,10 @@ files:
|
|
135
135
|
- lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb
|
136
136
|
- lib/rggen/systemverilog/rtl/register_index.rb
|
137
137
|
- lib/rggen/systemverilog/rtl/register_type.rb
|
138
|
+
- lib/rggen/systemverilog/rtl_package/bit_field/sv_rtl_package.rb
|
139
|
+
- lib/rggen/systemverilog/rtl_package/feature.rb
|
140
|
+
- lib/rggen/systemverilog/rtl_package/register/sv_rtl_package.rb
|
141
|
+
- lib/rggen/systemverilog/rtl_package/register_block/sv_rtl_package.rb
|
138
142
|
- lib/rggen/systemverilog/version.rb
|
139
143
|
homepage: https://github.com/rggen/rggen-systemverilog
|
140
144
|
licenses:
|
@@ -153,15 +157,15 @@ required_ruby_version: !ruby/object:Gem::Requirement
|
|
153
157
|
requirements:
|
154
158
|
- - ">="
|
155
159
|
- !ruby/object:Gem::Version
|
156
|
-
version: '2.
|
160
|
+
version: '2.7'
|
157
161
|
required_rubygems_version: !ruby/object:Gem::Requirement
|
158
162
|
requirements:
|
159
163
|
- - ">="
|
160
164
|
- !ruby/object:Gem::Version
|
161
165
|
version: '0'
|
162
166
|
requirements: []
|
163
|
-
rubygems_version: 3.
|
167
|
+
rubygems_version: 3.4.10
|
164
168
|
signing_key:
|
165
169
|
specification_version: 4
|
166
|
-
summary: rggen-systemverilog-0.
|
170
|
+
summary: rggen-systemverilog-0.30.0
|
167
171
|
test_files: []
|