rggen-systemverilog 0.28.0 → 0.30.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2019-2022 Taichi Ishitani
+Copyright (c) 2019-2023 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -35,7 +35,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
 
 ## Copyright & License
 
-Copyright © 2019-2022 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2019-2023 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/systemverilog/common/utility/package_definition.rb

@@ -8,6 +8,7 @@ module RgGen
           define_attribute :name
           define_attribute :package_imports
           define_attribute :include_files
+          define_attribute :parameters
 
           def package_imports(packages)
             @package_imports ||= []
@@ -36,21 +37,28 @@ module RgGen
           def pre_body_code(code)
             package_import_declaration(code)
             file_include_directives(code)
+            parameter_declarations(code)
           end
 
           def package_import_declaration(code)
             declarations =
-              Array(@package_imports)
-                .map { |package| ['import', space, package, '::*'] }
-            add_declarations_to_body(code, declarations)
+              @package_imports
+                &.map { |package| ['import', space, package, '::*'] }
+            declarations &&
+              add_declarations_to_body(code, declarations)
           end
 
           def file_include_directives(code)
-            Array(@include_files).each do |file|
+            @include_files&.each do |file|
               code << ['`include', space, string(file), nl]
             end
           end
 
+          def parameter_declarations(code)
+            parameters &&
+              add_declarations_to_body(code, parameters)
+          end
+
           def footer_code
             'endpackage'
           end

data/lib/rggen/systemverilog/ral/register_common.rb

@@ -26,7 +26,7 @@ module RgGen
         end
 
         def default_offset_address(index)
-          component.offset_address + component.byte_size(false) * index
+          component.offset_address + component.entry_byte_size * index
         end
 
         def hdl_path(array_index)

data/lib/rggen/systemverilog/rtl/partial_sum.rb

@@ -10,7 +10,7 @@ module RgGen
           operands
             .chunk(&method(:integer?))
             .flat_map(&method(:calc_partial_sum))
-            .reject { |value| integer?(value) && value.zero? }
+            .reject(&method(:integer_zero?))
             .tap { |sums| sums.empty? && (sums << 0) }
         end
 
@@ -22,6 +22,10 @@ module RgGen
         def integer?(value)
           value.is_a?(Integer)
         end
+
+        def integer_zero?(value)
+          integer?(value) && value.zero?
+        end
       end
     end
   end

data/lib/rggen/systemverilog/rtl/register/type/default.erb

@@ -4,8 +4,7 @@ rggen_default_register #(
   .ADDRESS_WIDTH  (<%= address_width %>),
   .OFFSET_ADDRESS (<%= offset_address %>),
   .BUS_WIDTH      (<%= bus_width %>),
-  .DATA_WIDTH     (<%= width %>),
-  .REGISTER_INDEX (<%= register_index %>)
+  .DATA_WIDTH     (<%= width %>)
 ) u_register (
   .i_clk        (<%= register_block.clock %>),
   .i_rst_n      (<%= register_block.reset %>),

data/lib/rggen/systemverilog/rtl/register/type/external.rb

@@ -19,12 +19,11 @@ RgGen.define_list_item_feature(:register, :type, :external) do
     end
 
     def start_address
-      hex(register.offset_address, address_width)
+      hex(register.address_range.begin, address_width)
     end
 
     def end_address
-      address = register.offset_address + register.byte_size - 1
-      hex(address, address_width)
+      hex(register.address_range.last, address_width)
     end
   end
 end

data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb

@@ -7,7 +7,8 @@ rggen_apb_adapter #(
   .BASE_ADDRESS         (<%= base_address %>),
   .BYTE_SIZE            (<%= byte_size %>),
   .ERROR_STATUS         (<%= error_status %>),
-  .DEFAULT_READ_DATA    (<%= default_read_data %>)
+  .DEFAULT_READ_DATA    (<%= default_read_data %>),
+  .INSERT_SLICER        (<%= insert_slicer %>)
 ) u_adapter (
   .i_clk        (<%= clock %>),
   .i_rst_n      (<%= reset %>),

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb

@@ -9,6 +9,7 @@ rggen_axi4lite_adapter #(
   .BYTE_SIZE            (<%= byte_size %>),
   .ERROR_STATUS         (<%= error_status %>),
   .DEFAULT_READ_DATA    (<%= default_read_data %>),
+  .INSERT_SLICER        (<%= insert_slicer %>),
   .WRITE_FIRST          (<%= write_first %>)
 ) u_adapter (
   .i_clk        (<%= clock %>),

data/lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.erb

@@ -8,6 +8,7 @@ rggen_wishbone_adapter #(
   .BYTE_SIZE            (<%= byte_size %>),
   .ERROR_STATUS         (<%= error_status %>),
   .DEFAULT_READ_DATA    (<%= default_read_data %>),
+  .INSERT_SLICER        (<%= insert_slicer %>),
   .USE_STALL            (<%= use_stall %>)
 ) u_adapter (
   .i_clk        (<%= clock %>),

data/lib/rggen/systemverilog/rtl/register_block/protocol.rb

@@ -89,6 +89,9 @@ RgGen.define_list_feature(:register_block, :protocol) do
           name: 'DEFAULT_READ_DATA', data_type: :bit, width: bus_width,
           default: all_bits_0
         }
+        parameter :insert_slicer, {
+          name: 'INSERT_SLICER', data_type: :bit, width: 1, default: 0
+        }
       end
 
       private

data/lib/rggen/systemverilog/rtl/register_index.rb

@@ -102,7 +102,13 @@ module RgGen
             operands.reduce(:*)
           elsif operands.first == 1
             operands.last
-          elsif need_bracket
+          else
+            product_expression(operands, need_bracket)
+          end
+        end
+
+        def product_expression(operands, need_bracket)
+          if need_bracket && /[+\-*\/]/ =~ operands.last
             "#{operands.first}*(#{operands.last})"
           else
             operands.join('*')

data/lib/rggen/systemverilog/rtl/register_type.rb

@@ -32,15 +32,29 @@ module RgGen
         end
 
         def collect_offsets(component)
-          if component.register_file? && component.array?
+          if need_byte_offset?(component)
             [component.offset_address, byte_offset(component)]
           else
             component.offset_address
           end
         end
 
+        def need_byte_offset?(component)
+          if component.register_file?
+            component.array?
+          else
+            component.array? && !component.settings[:support_shared_address]
+          end
+        end
+
         def byte_offset(component)
-          "#{component.byte_size(false)}*(#{component.local_index})"
+          byte_size = component.entry_byte_size
+          local_index = component.local_index
+          if /[+\-*\/]/ =~ local_index
+            "#{byte_size}*(#{local_index})"
+          else
+            "#{byte_size}*#{local_index}"
+          end
         end
 
         def format_offsets(offsets)
@@ -59,10 +73,6 @@ module RgGen
           bits = register.bit_fields.map(&:bit_map).inject(:|)
           hex(bits, register.width)
         end
-
-        def register_index
-          register.local_index || 0
-        end
       end
     end
   end

data/lib/rggen/systemverilog/rtl.rb

@@ -7,6 +7,7 @@ require_relative 'rtl/register_index'
 require_relative 'rtl/register_type'
 require_relative 'rtl/indirect_index'
 require_relative 'rtl/bit_field_index'
+require_relative 'rtl_package/feature'
 
 RgGen.setup_plugin :'rggen-sv-rtl' do |plugin|
   plugin.version RgGen::SystemVerilog::VERSION
@@ -50,4 +51,17 @@ RgGen.setup_plugin :'rggen-sv-rtl' do |plugin|
     'rtl/bit_field/type/wo_wo1_wotrg',
     'rtl/bit_field/type/wrc_wrs'
   ]
+
+  plugin.register_component :sv_rtl_package do
+    component RgGen::SystemVerilog::Common::Component,
+              RgGen::SystemVerilog::Common::ComponentFactory
+    feature RgGen::SystemVerilog::RTLPackage::Feature,
+            RgGen::SystemVerilog::Common::FeatureFactory
+  end
+
+  plugin.files [
+    'rtl_package/bit_field/sv_rtl_package',
+    'rtl_package/register/sv_rtl_package',
+    'rtl_package/register_block/sv_rtl_package'
+  ]
 end

data/lib/rggen/systemverilog/rtl_package/bit_field/sv_rtl_package.rb

@@ -0,0 +1,65 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:bit_field, :sv_rtl_package) do
+  sv_rtl_package do
+    build do
+      localparam :__width, {
+        name: "#{full_name}_bit_width",
+        data_type: :int, default: bit_field.width
+      }
+      localparam :__mask, {
+        name: "#{full_name}_bit_mask",
+        data_type: :bit, width: bit_field.width, default: mask_value
+      }
+      define_offset_localparam
+      define_label_localparams
+    end
+
+    private
+
+    def mask_value
+      hex((1 << bit_field.width) - 1, bit_field.width)
+    end
+
+    def define_offset_localparam
+      if bit_field.sequential?
+        define_sequential_offset_localparam
+      else
+        define_single_offset_localparam
+      end
+    end
+
+    def define_sequential_offset_localparam
+      size = bit_field.sequence_size
+      localparam :__offset, {
+        name: "#{full_name}_bit_offset",
+        data_type: :int, array_size: [size], default: offset_value(size)
+      }
+    end
+
+    def offset_value(size)
+      array(Array.new(size, &bit_field.method(:lsb)))
+    end
+
+    def define_single_offset_localparam
+      localparam :__offset, {
+        name: "#{full_name}_bit_offset",
+        data_type: :int, default: bit_field.lsb
+      }
+    end
+
+    def define_label_localparams
+      bit_field.labels
+        .each { |label| define_label_localparam(label) }
+    end
+
+    def define_label_localparam(label)
+      identifier = "label_#{label.name}".downcase.to_sym
+      value = hex(label.value, bit_field.width)
+      localparam identifier, {
+        name: "#{full_name}_#{label.name}",
+        data_type: :bit, width: bit_field.width, default: value
+      }
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl_package/feature.rb

@@ -0,0 +1,28 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RTLPackage
+      class Feature < Common::Feature
+        private
+
+        def full_name(separator = '_')
+          component.full_name(separator)
+        end
+
+        def create_parameter(parameter_type, attributes, &block)
+          attributes =
+            attributes.merge(
+              parameter_type: parameter_type, array_format: :unpacked,
+              name: attributes[:name].upcase
+            )
+          DataObject.new(
+            :parameter, attributes, &block
+          )
+        end
+
+        define_entity :localparam, :create_parameter, :parameter, -> { register_block }
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl_package/register/sv_rtl_package.rb

@@ -0,0 +1,83 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register, :sv_rtl_package) do
+  sv_rtl_package do
+    build do
+      localparam :__byte_width, {
+        name: "#{full_name}_byte_width",
+        data_type: :int, default: register.byte_width
+      }
+      localparam :__byte_size, {
+        name: "#{full_name}_byte_size",
+        data_type: :int, default: register.total_byte_size(hierarchical: true)
+      }
+      define_array_size_localparam
+      define_offset_localparams
+    end
+
+    private
+
+    def define_array_size_localparam
+      return unless array?
+
+      list = array_size_list
+      localparam :__array_size, {
+        name: "#{full_name}_array_size",
+        data_type: :int, array_size: [list.size], default: array(list)
+      }
+    end
+
+    def define_offset_localparams
+      if array?
+        define_array_offset_localparams
+      else
+        define_single_offset_localparam
+      end
+    end
+
+    def define_array_offset_localparams
+      width = register_block.local_address_width
+      size_list = array_size_list
+      value_list = group_address_list(address_list, size_list).first
+      localparam :__offset, {
+        name: "#{full_name}_byte_offset",
+        data_type: :bit, width: width, array_size: size_list, default: value_list
+      }
+    end
+
+    def address_list
+      register
+        .expanded_offset_addresses
+        .map { |address| hex(address, register_block.local_address_width) }
+    end
+
+    def group_address_list(address_list, size_list)
+      list =
+        if size_list.size > 1
+          group_address_list(address_list, size_list[1..])
+        else
+          address_list
+        end
+      list
+        .each_slice(size_list.first)
+        .map(&method(:array))
+    end
+
+    def define_single_offset_localparam
+      width = register_block.local_address_width
+      value = address_list.first
+      localparam :__offset, {
+        name: "#{full_name}_byte_offset",
+        data_type: :bit, width: width, default: value
+      }
+    end
+
+    def array?
+      register.array?(hierarchical: true)
+    end
+
+    def array_size_list
+      register.array_size(hierarchical: true)
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl_package/register_block/sv_rtl_package.rb

@@ -0,0 +1,25 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_block, :sv_rtl_package) do
+  sv_rtl_package do
+    write_file '<%= package_name %>.sv' do |file|
+      file.body { sv_rtl_package_definition }
+    end
+
+    private
+
+    def sv_rtl_package_definition
+      package_definition(package_name) do |package|
+        package.parameters parameters
+      end
+    end
+
+    def package_name
+      "#{register_block.name}_rtl_pkg"
+    end
+
+    def parameters
+      register_block.declarations[:parameter]
+    end
+  end
+end

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.28.0'
+    VERSION = '0.30.0'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.28.0
+  version: 0.30.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2022-10-10 00:00:00.000000000 Z
+date: 2023-04-28 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -135,6 +135,10 @@ files:
 - lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/register_index.rb
 - lib/rggen/systemverilog/rtl/register_type.rb
+- lib/rggen/systemverilog/rtl_package/bit_field/sv_rtl_package.rb
+- lib/rggen/systemverilog/rtl_package/feature.rb
+- lib/rggen/systemverilog/rtl_package/register/sv_rtl_package.rb
+- lib/rggen/systemverilog/rtl_package/register_block/sv_rtl_package.rb
 - lib/rggen/systemverilog/version.rb
 homepage: https://github.com/rggen/rggen-systemverilog
 licenses:
@@ -153,15 +157,15 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: '2.6'
+      version: '2.7'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.3.7
+rubygems_version: 3.4.10
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.28.0
+summary: rggen-systemverilog-0.30.0
 test_files: []