rggen-systemverilog 0.25.1 → 0.26.0
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- checksums.yaml +4 -4
- data/LICENSE +1 -1
- data/README.md +1 -1
- data/lib/rggen/systemverilog/common/utility/identifier.rb +1 -1
- data/lib/rggen/systemverilog/ral/bit_field/type/rotrg_rwtrg_wotrg.rb +9 -0
- data/lib/rggen/systemverilog/ral/bit_field/type/rowo_rowotrg.rb +8 -0
- data/lib/rggen/systemverilog/ral/bit_field/type.rb +19 -6
- data/lib/rggen/systemverilog/ral/register_common.rb +1 -1
- data/lib/rggen/systemverilog/ral.rb +2 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb +2 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/{ro.erb → ro_rotrg.erb} +8 -4
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb +40 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rof.erb +5 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.erb +21 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.rb +52 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb +2 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/{rw_w1_wo_wo1.erb → rw_rwtrg_w1.erb} +4 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_rwtrg_w1.rb +46 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb +2 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.erb +2 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb +2 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb +2 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb +2 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.erb +22 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.rb +38 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb +2 -0
- data/lib/rggen/systemverilog/rtl/register/type/external.rb +5 -54
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb +3 -60
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +4 -118
- data/lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.erb +17 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.rb +26 -0
- data/lib/rggen/systemverilog/rtl/setup.rb +2 -4
- data/lib/rggen/systemverilog/rtl.rb +5 -3
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +18 -10
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb +0 -22
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb +0 -24
- data/lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb +0 -28
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA256:
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-
metadata.gz:
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-
data.tar.gz:
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+
metadata.gz: 6093eea4b475c6dddb948d2b0bb5053705cc64f38a5603c925d0ab04029e0978
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+
data.tar.gz: e2c07ce7eb68f15c9e4d2dbd0f83d7a74dbcb92ba292ba1fae8830c4ca147cb0
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SHA512:
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metadata.gz:
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data.tar.gz:
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+
metadata.gz: 2d460b5eecdc50fbae20514b7f814fd98774b6dcb05ab72df2936301a9218870609eb1236b13f9a305d1882f001360eb84537b083c5323d2fde475fe170ffaed
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data.tar.gz: 4ea6fb47189ec224f30701198d9a51de4ab68cbc2a601b048ad23b1edcda1308214218fd456550c2e8d085c3575ab2aeec7e58c43d6337dba81111c0e8f0b07f
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data/LICENSE
CHANGED
@@ -1,6 +1,6 @@
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1
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The MIT License (MIT)
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2
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-
Copyright (c) 2019-
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+
Copyright (c) 2019-2022 Taichi Ishitani
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5
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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data/README.md
CHANGED
@@ -34,7 +34,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
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## Copyright & License
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-
Copyright © 2019-
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+
Copyright © 2019-2022 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
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## Code of Conduct
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40
40
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@@ -4,11 +4,20 @@ RgGen.define_list_feature(:bit_field, :type) do
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4
4
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sv_ral do
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5
5
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base_feature do
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6
6
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define_helpers do
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-
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7
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+
def access(access_type = nil, &block)
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attribute_accessor('@access', access_type, &block)
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+
end
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10
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def model_name(name = nil, &block)
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10
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-
@model_name
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-
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+
attribute_accessor('@model_name', name, &block)
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+
end
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private
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def attribute_accessor(variable_name, value, &block)
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(new_value = value || block) &&
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instance_variable_set(variable_name, new_value)
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+
instance_variable_get(variable_name)
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12
21
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end
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end
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@@ -24,12 +33,11 @@ RgGen.define_list_feature(:bit_field, :type) do
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33
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end
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34
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26
35
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def access
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-
(
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+
eval_attribute(:access, bit_field.type).to_s.upcase
|
28
37
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end
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38
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30
39
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def model_name
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31
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-
|
32
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-
name.is_a?(Proc) && instance_eval(&name) || name || 'rggen_ral_field'
|
40
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+
eval_attribute(:model_name, 'rggen_ral_field')
|
33
41
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end
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def constructors
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@@ -73,6 +81,11 @@ RgGen.define_list_feature(:bit_field, :type) do
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73
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''
|
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82
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end
|
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83
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end
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+
|
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+
def eval_attribute(attribute, default_value)
|
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+
value = helper.__send__(attribute)
|
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value.is_a?(Proc) && instance_eval(&value) || value || default_value
|
88
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+
end
|
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89
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end
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90
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91
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default_feature do
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@@ -20,6 +20,8 @@ module RgGen
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20
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plugin.files [
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'ral/bit_field/type',
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22
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'ral/bit_field/type/rof',
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+
'ral/bit_field/type/rotrg_rwtrg_wotrg',
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'ral/bit_field/type/rowo_rowotrg',
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25
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'ral/bit_field/type/rwc_rws',
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26
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'ral/bit_field/type/rwe_rwl',
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'ral/bit_field/type/w0trg_w1trg',
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@@ -1,10 +1,14 @@
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1
1
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rggen_bit_field #(
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2
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-
.WIDTH
|
3
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-
.STORAGE
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2
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+
.WIDTH (<%= width %>),
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3
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+
.STORAGE (0),
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4
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+
.EXTERNAL_READ_DATA (1),
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+
.TRIGGER (<%= trigger %>)
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6
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) u_bit_field (
|
5
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-
.i_clk (
|
6
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-
.i_rst_n (
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+
.i_clk (<%= clock %>),
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8
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+
.i_rst_n (<%= reset %>),
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7
9
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.bit_field_if (<%= bit_field_if %>),
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10
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+
.o_write_trigger (),
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11
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+
.o_read_trigger (<%= read_trigger_signal %>),
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8
12
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.i_sw_write_enable ('0),
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9
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.i_hw_write_enable ('0),
|
10
14
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.i_hw_write_data ('0),
|
@@ -0,0 +1,40 @@
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1
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# frozen_string_literal: true
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|
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RgGen.define_list_item_feature(:bit_field, :type, [:ro, :rotrg]) do
|
4
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sv_rtl do
|
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build do
|
6
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unless bit_field.reference?
|
7
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input :value_in, {
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8
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name: "i_#{full_name}", width: width,
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array_size: array_size, array_format: array_port_format
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}
|
11
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end
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if rotrg?
|
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output :read_trigger, {
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name: "o_#{full_name}_read_trigger", width: 1,
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array_size: array_size, array_format: array_port_format
|
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}
|
17
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end
|
18
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end
|
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+
|
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main_code :bit_field, from_template: true
|
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|
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private
|
23
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+
|
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def rotrg?
|
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bit_field.type == :rotrg
|
26
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end
|
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+
|
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def trigger
|
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rotrg? && 1 || 0
|
30
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end
|
31
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+
|
32
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+
def read_trigger_signal
|
33
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+
rotrg? && read_trigger[loop_variables] || nil
|
34
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+
end
|
35
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+
|
36
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+
def reference_or_value_in
|
37
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+
reference_bit_field || value_in[loop_variables]
|
38
|
+
end
|
39
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+
end
|
40
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+
end
|
@@ -1,10 +1,13 @@
|
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1
1
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rggen_bit_field #(
|
2
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-
.WIDTH
|
3
|
-
.STORAGE
|
2
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+
.WIDTH (<%= width %>),
|
3
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+
.STORAGE (0),
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4
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+
.EXTERNAL_READ_DATA (1)
|
4
5
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) u_bit_field (
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5
6
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.i_clk ('0),
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6
7
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.i_rst_n ('0),
|
7
8
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.bit_field_if (<%= bit_field_if %>),
|
9
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+
.o_write_trigger (),
|
10
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+
.o_read_trigger (),
|
8
11
|
.i_sw_write_enable ('0),
|
9
12
|
.i_hw_write_enable ('0),
|
10
13
|
.i_hw_write_data ('0),
|
@@ -0,0 +1,21 @@
|
|
1
|
+
rggen_bit_field #(
|
2
|
+
.WIDTH (<%= width %>),
|
3
|
+
.INITIAL_VALUE (<%= initial_value %>),
|
4
|
+
.EXTERNAL_READ_DATA (1),
|
5
|
+
.TRIGGER (<%= trigger %>)
|
6
|
+
) u_bit_field (
|
7
|
+
.i_clk (<%= clock %>),
|
8
|
+
.i_rst_n (<%= reset %>),
|
9
|
+
.bit_field_if (<%= bit_field_if %>),
|
10
|
+
.o_write_trigger (<%= write_trigger_signal %>),
|
11
|
+
.o_read_trigger (<%= read_trigger_signal %>),
|
12
|
+
.i_sw_write_enable ('1),
|
13
|
+
.i_hw_write_enable ('0),
|
14
|
+
.i_hw_write_data ('0),
|
15
|
+
.i_hw_set ('0),
|
16
|
+
.i_hw_clear ('0),
|
17
|
+
.i_value (<%= reference_or_value_in %>),
|
18
|
+
.i_mask ('1),
|
19
|
+
.o_value (<%= value_out[loop_variables] %>),
|
20
|
+
.o_value_unmasked ()
|
21
|
+
);
|
@@ -0,0 +1,52 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
RgGen.define_list_item_feature(:bit_field, :type, [:rowo, :rowotrg]) do
|
4
|
+
sv_rtl do
|
5
|
+
build do
|
6
|
+
output :value_out, {
|
7
|
+
name: "o_#{full_name}", width: width,
|
8
|
+
array_size: array_size, array_format: array_port_format
|
9
|
+
}
|
10
|
+
unless bit_field.reference?
|
11
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+
input :value_in, {
|
12
|
+
name: "i_#{full_name}", width: width,
|
13
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+
array_size: array_size, array_format: array_port_format
|
14
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+
}
|
15
|
+
end
|
16
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+
if rowotrg?
|
17
|
+
output :write_trigger, {
|
18
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+
name: "o_#{full_name}_write_trigger", width: 1,
|
19
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+
array_size: array_size, array_format: array_port_format
|
20
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+
}
|
21
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+
output :read_trigger, {
|
22
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+
name: "o_#{full_name}_read_trigger", width: 1,
|
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+
array_size: array_size, array_format: array_port_format
|
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}
|
25
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+
end
|
26
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+
end
|
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+
|
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main_code :bit_field, from_template: true
|
29
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+
|
30
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+
private
|
31
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+
|
32
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+
def rowotrg?
|
33
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+
bit_field.type == :rowotrg
|
34
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+
end
|
35
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+
|
36
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+
def trigger
|
37
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+
rowotrg? && 1 || 0
|
38
|
+
end
|
39
|
+
|
40
|
+
def write_trigger_signal
|
41
|
+
rowotrg? && write_trigger[loop_variables] || nil
|
42
|
+
end
|
43
|
+
|
44
|
+
def read_trigger_signal
|
45
|
+
rowotrg? && read_trigger[loop_variables] || nil
|
46
|
+
end
|
47
|
+
|
48
|
+
def reference_or_value_in
|
49
|
+
reference_bit_field || value_in[loop_variables]
|
50
|
+
end
|
51
|
+
end
|
52
|
+
end
|
@@ -1,12 +1,14 @@
|
|
1
1
|
rggen_bit_field #(
|
2
2
|
.WIDTH (<%= width %>),
|
3
3
|
.INITIAL_VALUE (<%= initial_value %>),
|
4
|
-
.
|
5
|
-
.
|
4
|
+
.SW_WRITE_ONCE (<%= write_once %>),
|
5
|
+
.TRIGGER (<%= trigger %>)
|
6
6
|
) u_bit_field (
|
7
7
|
.i_clk (<%= clock %>),
|
8
8
|
.i_rst_n (<%= reset %>),
|
9
9
|
.bit_field_if (<%= bit_field_if %>),
|
10
|
+
.o_write_trigger (<%= write_trigger_signal %>),
|
11
|
+
.o_read_trigger (<%= read_trigger_signal %>),
|
10
12
|
.i_sw_write_enable ('1),
|
11
13
|
.i_hw_write_enable ('0),
|
12
14
|
.i_hw_write_data ('0),
|
@@ -0,0 +1,46 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
RgGen.define_list_item_feature(:bit_field, :type, [:rw, :rwtrg, :w1]) do
|
4
|
+
sv_rtl do
|
5
|
+
build do
|
6
|
+
output :value_out, {
|
7
|
+
name: "o_#{full_name}", width: width,
|
8
|
+
array_size: array_size, array_format: array_port_format
|
9
|
+
}
|
10
|
+
if rwtrg?
|
11
|
+
output :write_trigger, {
|
12
|
+
name: "o_#{full_name}_write_trigger", width: 1,
|
13
|
+
array_size: array_size, array_format: array_port_format
|
14
|
+
}
|
15
|
+
output :read_trigger, {
|
16
|
+
name: "o_#{full_name}_read_trigger", width: 1,
|
17
|
+
array_size: array_size, array_format: array_port_format
|
18
|
+
}
|
19
|
+
end
|
20
|
+
end
|
21
|
+
|
22
|
+
main_code :bit_field, from_template: true
|
23
|
+
|
24
|
+
private
|
25
|
+
|
26
|
+
def rwtrg?
|
27
|
+
bit_field.type == :rwtrg
|
28
|
+
end
|
29
|
+
|
30
|
+
def trigger
|
31
|
+
rwtrg? && 1 || 0
|
32
|
+
end
|
33
|
+
|
34
|
+
def write_trigger_signal
|
35
|
+
rwtrg? && write_trigger[loop_variables] || nil
|
36
|
+
end
|
37
|
+
|
38
|
+
def read_trigger_signal
|
39
|
+
rwtrg? && read_trigger[loop_variables] || nil
|
40
|
+
end
|
41
|
+
|
42
|
+
def write_once
|
43
|
+
bit_field.type == :w1 && 1 || 0
|
44
|
+
end
|
45
|
+
end
|
46
|
+
end
|
@@ -5,6 +5,8 @@ rggen_bit_field #(
|
|
5
5
|
.i_clk (<%= clock %>),
|
6
6
|
.i_rst_n (<%= reset %>),
|
7
7
|
.bit_field_if (<%= bit_field_if %>),
|
8
|
+
.o_write_trigger (),
|
9
|
+
.o_read_trigger (),
|
8
10
|
.i_sw_write_enable ('1),
|
9
11
|
.i_hw_write_enable (<%= set_signal %>),
|
10
12
|
.i_hw_write_data (<%= value_in[loop_variables] %>),
|
@@ -0,0 +1,22 @@
|
|
1
|
+
rggen_bit_field #(
|
2
|
+
.WIDTH (<%= width %>),
|
3
|
+
.INITIAL_VALUE (<%= initial_value %>),
|
4
|
+
.SW_READ_ACTION (RGGEN_READ_NONE),
|
5
|
+
.SW_WRITE_ONCE (<%= write_once %>),
|
6
|
+
.TRIGGER (<%= trigger %>)
|
7
|
+
) u_bit_field (
|
8
|
+
.i_clk (<%= clock %>),
|
9
|
+
.i_rst_n (<%= reset %>),
|
10
|
+
.bit_field_if (<%= bit_field_if %>),
|
11
|
+
.o_write_trigger (<%= write_trigger_signal %>),
|
12
|
+
.o_read_trigger (),
|
13
|
+
.i_sw_write_enable ('1),
|
14
|
+
.i_hw_write_enable ('0),
|
15
|
+
.i_hw_write_data ('0),
|
16
|
+
.i_hw_set ('0),
|
17
|
+
.i_hw_clear ('0),
|
18
|
+
.i_value ('0),
|
19
|
+
.i_mask ('1),
|
20
|
+
.o_value (<%= value_out[loop_variables] %>),
|
21
|
+
.o_value_unmasked ()
|
22
|
+
);
|
@@ -0,0 +1,38 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
RgGen.define_list_item_feature(:bit_field, :type, [:wo, :wo1, :wotrg]) do
|
4
|
+
sv_rtl do
|
5
|
+
build do
|
6
|
+
output :value_out, {
|
7
|
+
name: "o_#{full_name}", width: width,
|
8
|
+
array_size: array_size, array_format: array_port_format
|
9
|
+
}
|
10
|
+
if wotrg?
|
11
|
+
output :write_trigger, {
|
12
|
+
name: "o_#{full_name}_write_trigger", width: 1,
|
13
|
+
array_size: array_size, array_format: array_port_format
|
14
|
+
}
|
15
|
+
end
|
16
|
+
end
|
17
|
+
|
18
|
+
main_code :bit_field, from_template: true
|
19
|
+
|
20
|
+
private
|
21
|
+
|
22
|
+
def wotrg?
|
23
|
+
bit_field.type == :wotrg
|
24
|
+
end
|
25
|
+
|
26
|
+
def trigger
|
27
|
+
wotrg? && 1 || 0
|
28
|
+
end
|
29
|
+
|
30
|
+
def write_trigger_signal
|
31
|
+
wotrg? && write_trigger[loop_variables] || nil
|
32
|
+
end
|
33
|
+
|
34
|
+
def write_once
|
35
|
+
bit_field.type == :wo1 && 1 || 0
|
36
|
+
end
|
37
|
+
end
|
38
|
+
end
|
@@ -3,63 +3,14 @@
|
|
3
3
|
RgGen.define_list_item_feature(:register, :type, :external) do
|
4
4
|
sv_rtl do
|
5
5
|
build do
|
6
|
-
|
7
|
-
|
8
|
-
|
9
|
-
|
10
|
-
|
11
|
-
}
|
12
|
-
else
|
13
|
-
output :valid, {
|
14
|
-
name: "o_#{register.name}_valid", width: 1
|
15
|
-
}
|
16
|
-
output :access, {
|
17
|
-
name: "o_#{register.name}_access", width: '$bits(rggen_access)'
|
18
|
-
}
|
19
|
-
output :address, {
|
20
|
-
name: "o_#{register.name}_address", width: address_width
|
21
|
-
}
|
22
|
-
output :write_data, {
|
23
|
-
name: "o_#{register.name}_data", width: bus_width
|
24
|
-
}
|
25
|
-
output :strobe, {
|
26
|
-
name: "o_#{register.name}_strobe", width: byte_width
|
27
|
-
}
|
28
|
-
input :ready, {
|
29
|
-
name: "i_#{register.name}_ready", width: 1
|
30
|
-
}
|
31
|
-
input :status, {
|
32
|
-
name: "i_#{register.name}_status", width: 2
|
33
|
-
}
|
34
|
-
input :read_data, {
|
35
|
-
name: "i_#{register.name}_data", width: bus_width
|
36
|
-
}
|
37
|
-
interface :bus_if, {
|
38
|
-
name: 'bus_if', interface_type: 'rggen_bus_if',
|
39
|
-
parameter_values: [address_width, bus_width],
|
40
|
-
variables: [
|
41
|
-
'valid', 'access', 'address', 'write_data', 'strobe',
|
42
|
-
'ready', 'status', 'read_data'
|
43
|
-
]
|
44
|
-
}
|
45
|
-
end
|
6
|
+
interface_port :bus_if, {
|
7
|
+
name: "#{register.name}_bus_if",
|
8
|
+
interface_type: 'rggen_bus_if',
|
9
|
+
modport: 'master'
|
10
|
+
}
|
46
11
|
end
|
47
12
|
|
48
13
|
main_code :register, from_template: true
|
49
|
-
main_code :register do |code|
|
50
|
-
unless configuration.fold_sv_interface_port?
|
51
|
-
[
|
52
|
-
[valid, bus_if.valid],
|
53
|
-
[access, bus_if.access],
|
54
|
-
[address, bus_if.address],
|
55
|
-
[write_data, bus_if.write_data],
|
56
|
-
[strobe, bus_if.strobe],
|
57
|
-
[bus_if.ready, ready],
|
58
|
-
[bus_if.status, "rggen_status'(#{status})"],
|
59
|
-
[bus_if.read_data, read_data]
|
60
|
-
].map { |lhs, rhs| code << assign(lhs, rhs) << nl }
|
61
|
-
end
|
62
|
-
end
|
63
14
|
|
64
15
|
private
|
65
16
|
|
@@ -21,68 +21,11 @@ RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
|
|
21
21
|
|
22
22
|
sv_rtl do
|
23
23
|
build do
|
24
|
-
|
25
|
-
|
26
|
-
|
27
|
-
}
|
28
|
-
else
|
29
|
-
input :psel, {
|
30
|
-
name: 'i_psel', width: 1
|
31
|
-
}
|
32
|
-
input :penable, {
|
33
|
-
name: 'i_penable', width: 1
|
34
|
-
}
|
35
|
-
input :paddr, {
|
36
|
-
name: 'i_paddr', width: address_width
|
37
|
-
}
|
38
|
-
input :pprot, {
|
39
|
-
name: 'i_pprot', width: 3
|
40
|
-
}
|
41
|
-
input :pwrite, {
|
42
|
-
name: 'i_pwrite', width: 1
|
43
|
-
}
|
44
|
-
input :pstrb, {
|
45
|
-
name: 'i_pstrb', width: byte_width
|
46
|
-
}
|
47
|
-
input :pwdata, {
|
48
|
-
name: 'i_pwdata', width: bus_width
|
49
|
-
}
|
50
|
-
output :pready, {
|
51
|
-
name: 'o_pready', width: 1
|
52
|
-
}
|
53
|
-
output :prdata, {
|
54
|
-
name: 'o_prdata', width: bus_width
|
55
|
-
}
|
56
|
-
output :pslverr, {
|
57
|
-
name: 'o_pslverr', width: 1
|
58
|
-
}
|
59
|
-
interface :apb_if, {
|
60
|
-
name: 'apb_if', interface_type: 'rggen_apb_if',
|
61
|
-
parameter_values: [address_width, bus_width],
|
62
|
-
variables: [
|
63
|
-
'psel', 'penable', 'paddr', 'pprot', 'pwrite', 'pstrb', 'pwdata',
|
64
|
-
'pready', 'prdata', 'pslverr'
|
65
|
-
]
|
66
|
-
}
|
67
|
-
end
|
24
|
+
interface_port :apb_if, {
|
25
|
+
name: 'apb_if', interface_type: 'rggen_apb_if', modport: 'slave'
|
26
|
+
}
|
68
27
|
end
|
69
28
|
|
70
29
|
main_code :register_block, from_template: true
|
71
|
-
main_code :register_block do |code|
|
72
|
-
unless configuration.fold_sv_interface_port?
|
73
|
-
[
|
74
|
-
[apb_if.psel, psel],
|
75
|
-
[apb_if.penable, penable],
|
76
|
-
[apb_if.paddr, paddr],
|
77
|
-
[apb_if.pprot, pprot],
|
78
|
-
[apb_if.pwrite, pwrite],
|
79
|
-
[apb_if.pstrb, pstrb],
|
80
|
-
[apb_if.pwdata, pwdata],
|
81
|
-
[pready, apb_if.pready],
|
82
|
-
[prdata, apb_if.prdata],
|
83
|
-
[pslverr, apb_if.pslverr]
|
84
|
-
].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
|
85
|
-
end
|
86
|
-
end
|
87
30
|
end
|
88
31
|
end
|
@@ -19,132 +19,18 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
|
|
19
19
|
parameter :write_first, {
|
20
20
|
name: 'WRITE_FIRST', data_type: :bit, default: 1
|
21
21
|
}
|
22
|
-
|
23
|
-
|
24
|
-
|
25
|
-
|
26
|
-
}
|
27
|
-
else
|
28
|
-
input :awvalid, {
|
29
|
-
name: 'i_awvalid', width: 1
|
30
|
-
}
|
31
|
-
output :awready, {
|
32
|
-
name: 'o_awready', width: 1
|
33
|
-
}
|
34
|
-
input :awid, {
|
35
|
-
name: 'i_awid', width: id_port_width
|
36
|
-
}
|
37
|
-
input :awaddr, {
|
38
|
-
name: 'i_awaddr', width: address_width
|
39
|
-
}
|
40
|
-
input :awprot, {
|
41
|
-
name: 'i_awprot', width: 3
|
42
|
-
}
|
43
|
-
input :wvalid, {
|
44
|
-
name: 'i_wvalid', width: 1
|
45
|
-
}
|
46
|
-
output :wready, {
|
47
|
-
name: 'o_wready', width: 1
|
48
|
-
}
|
49
|
-
input :wdata, {
|
50
|
-
name: 'i_wdata', width: bus_width
|
51
|
-
}
|
52
|
-
input :wstrb, {
|
53
|
-
name: 'i_wstrb', width: byte_width
|
54
|
-
}
|
55
|
-
output :bvalid, {
|
56
|
-
name: 'o_bvalid', width: 1
|
57
|
-
}
|
58
|
-
output :bid, {
|
59
|
-
name: 'o_bid', width: id_port_width
|
60
|
-
}
|
61
|
-
input :bready, {
|
62
|
-
name: 'i_bready', width: 1
|
63
|
-
}
|
64
|
-
output :bresp, {
|
65
|
-
name: 'o_bresp', width: 2
|
66
|
-
}
|
67
|
-
input :arvalid, {
|
68
|
-
name: 'i_arvalid', width: 1
|
69
|
-
}
|
70
|
-
output :arready, {
|
71
|
-
name: 'o_arready', width: 1
|
72
|
-
}
|
73
|
-
input :arid, {
|
74
|
-
name: 'i_arid', width: id_port_width
|
75
|
-
}
|
76
|
-
input :araddr, {
|
77
|
-
name: 'i_araddr', width: address_width
|
78
|
-
}
|
79
|
-
input :arprot, {
|
80
|
-
name: 'i_arprot', width: 3
|
81
|
-
}
|
82
|
-
output :rvalid, {
|
83
|
-
name: 'o_rvalid', width: 1
|
84
|
-
}
|
85
|
-
input :rready, {
|
86
|
-
name: 'i_rready', width: 1
|
87
|
-
}
|
88
|
-
output :rid, {
|
89
|
-
name: 'o_rid', width: id_port_width
|
90
|
-
}
|
91
|
-
output :rdata, {
|
92
|
-
name: 'o_rdata', width: bus_width
|
93
|
-
}
|
94
|
-
output :rresp, {
|
95
|
-
name: 'o_rresp', width: 2
|
96
|
-
}
|
97
|
-
interface :axi4lite_if, {
|
98
|
-
name: 'axi4lite_if', interface_type: 'rggen_axi4lite_if',
|
99
|
-
parameter_values: [id_width, address_width, bus_width],
|
100
|
-
variables: [
|
101
|
-
'awvalid', 'awready', 'awid', 'awaddr', 'awprot',
|
102
|
-
'wvalid', 'wready', 'wdata', 'wstrb',
|
103
|
-
'bvalid', 'bready', 'bid', 'bresp',
|
104
|
-
'arvalid', 'arready', 'arid', 'araddr', 'arprot',
|
105
|
-
'rvalid', 'rready', 'rid', 'rdata', 'rresp'
|
106
|
-
]
|
107
|
-
}
|
108
|
-
end
|
22
|
+
interface_port :axi4lite_if, {
|
23
|
+
name: 'axi4lite_if',
|
24
|
+
interface_type: 'rggen_axi4lite_if', modport: 'slave'
|
25
|
+
}
|
109
26
|
end
|
110
27
|
|
111
28
|
main_code :register_block, from_template: true
|
112
|
-
main_code :register_block do |code|
|
113
|
-
configuration.fold_sv_interface_port? || assign_axi4lite_signals(code)
|
114
|
-
end
|
115
29
|
|
116
30
|
private
|
117
31
|
|
118
32
|
def id_port_width
|
119
33
|
"((#{id_width}>0)?#{id_width}:1)"
|
120
34
|
end
|
121
|
-
|
122
|
-
def assign_axi4lite_signals(code)
|
123
|
-
[
|
124
|
-
[axi4lite_if.awvalid, awvalid],
|
125
|
-
[awready, axi4lite_if.awready],
|
126
|
-
[axi4lite_if.awid, awid],
|
127
|
-
[axi4lite_if.awaddr, awaddr],
|
128
|
-
[axi4lite_if.awprot, awprot],
|
129
|
-
[axi4lite_if.wvalid, wvalid],
|
130
|
-
[wready, axi4lite_if.wready],
|
131
|
-
[axi4lite_if.wdata, wdata],
|
132
|
-
[axi4lite_if.wstrb, wstrb],
|
133
|
-
[bvalid, axi4lite_if.bvalid],
|
134
|
-
[axi4lite_if.bready, bready],
|
135
|
-
[bid, axi4lite_if.bid],
|
136
|
-
[bresp, axi4lite_if.bresp],
|
137
|
-
[axi4lite_if.arvalid, arvalid],
|
138
|
-
[arready, axi4lite_if.arready],
|
139
|
-
[axi4lite_if.arid, arid],
|
140
|
-
[axi4lite_if.araddr, araddr],
|
141
|
-
[axi4lite_if.arprot, arprot],
|
142
|
-
[rvalid, axi4lite_if.rvalid],
|
143
|
-
[axi4lite_if.rready, rready],
|
144
|
-
[rid, axi4lite_if.rid],
|
145
|
-
[rdata, axi4lite_if.rdata],
|
146
|
-
[rresp, axi4lite_if.rresp]
|
147
|
-
].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
|
148
|
-
end
|
149
35
|
end
|
150
36
|
end
|
@@ -0,0 +1,17 @@
|
|
1
|
+
rggen_wishbone_adapter #(
|
2
|
+
.ADDRESS_WIDTH (<%= address_width %>),
|
3
|
+
.LOCAL_ADDRESS_WIDTH (<%= local_address_width %>),
|
4
|
+
.BUS_WIDTH (<%= bus_width %>),
|
5
|
+
.REGISTERS (<%= total_registers %>),
|
6
|
+
.PRE_DECODE (<%= pre_decode %>),
|
7
|
+
.BASE_ADDRESS (<%= base_address %>),
|
8
|
+
.BYTE_SIZE (<%= byte_size %>),
|
9
|
+
.ERROR_STATUS (<%= error_status %>),
|
10
|
+
.DEFAULT_READ_DATA (<%= default_read_data %>),
|
11
|
+
.USE_STALL (<%= use_stall %>)
|
12
|
+
) u_adapter (
|
13
|
+
.i_clk (<%= clock %>),
|
14
|
+
.i_rst_n (<%= reset %>),
|
15
|
+
.wishbone_if (<%= wishbone_if %>),
|
16
|
+
.register_if (<%= register_if %>)
|
17
|
+
);
|
@@ -0,0 +1,26 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
RgGen.define_list_item_feature(:register_block, :protocol, :wishbone) do
|
4
|
+
configuration do
|
5
|
+
verify(:component) do
|
6
|
+
error_condition { configuration.bus_width > 64 }
|
7
|
+
message do
|
8
|
+
'bus width over 64 bit is not supported: ' \
|
9
|
+
"#{configuration.bus_width}"
|
10
|
+
end
|
11
|
+
end
|
12
|
+
end
|
13
|
+
|
14
|
+
sv_rtl do
|
15
|
+
build do
|
16
|
+
parameter :use_stall, {
|
17
|
+
name: 'USE_STALL', data_type: :bit, default: 1
|
18
|
+
}
|
19
|
+
interface_port :wishbone_if, {
|
20
|
+
name: 'wishbone_if', interface_type: 'rggen_wishbone_if', modport: 'slave'
|
21
|
+
}
|
22
|
+
end
|
23
|
+
|
24
|
+
main_code :register_block, from_template: true
|
25
|
+
end
|
26
|
+
end
|
@@ -3,11 +3,9 @@
|
|
3
3
|
require 'rggen/systemverilog/rtl'
|
4
4
|
|
5
5
|
RgGen.register_plugin RgGen::SystemVerilog::RTL do |builder|
|
6
|
-
builder.enable :global, [
|
7
|
-
:array_port_format, :fold_sv_interface_port
|
8
|
-
]
|
6
|
+
builder.enable :global, [:array_port_format]
|
9
7
|
builder.enable :register_block, [:sv_rtl_top, :protocol]
|
10
|
-
builder.enable :register_block, :protocol, [:apb, :axi4lite]
|
8
|
+
builder.enable :register_block, :protocol, [:apb, :axi4lite, :wishbone]
|
11
9
|
builder.enable :register_file, [:sv_rtl_top]
|
12
10
|
builder.enable :register, [:sv_rtl_top]
|
13
11
|
builder.enable :bit_field, [:sv_rtl_top]
|
@@ -25,19 +25,20 @@ module RgGen
|
|
25
25
|
'rtl/bit_field/sv_rtl_top',
|
26
26
|
'rtl/bit_field/type',
|
27
27
|
'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
|
28
|
-
'rtl/bit_field/type/
|
28
|
+
'rtl/bit_field/type/ro_rotrg',
|
29
29
|
'rtl/bit_field/type/rof',
|
30
|
+
'rtl/bit_field/type/rowo_rowotrg',
|
30
31
|
'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
|
31
|
-
'rtl/bit_field/type/
|
32
|
+
'rtl/bit_field/type/rw_rwtrg_w1',
|
32
33
|
'rtl/bit_field/type/rwc',
|
33
34
|
'rtl/bit_field/type/rwe_rwl',
|
34
35
|
'rtl/bit_field/type/rws',
|
35
36
|
'rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
|
36
37
|
'rtl/bit_field/type/w0t_w1t',
|
37
38
|
'rtl/bit_field/type/w0trg_w1trg',
|
39
|
+
'rtl/bit_field/type/wo_wo1_wotrg',
|
38
40
|
'rtl/bit_field/type/wrc_wrs',
|
39
41
|
'rtl/global/array_port_format',
|
40
|
-
'rtl/global/fold_sv_interface_port',
|
41
42
|
'rtl/register/sv_rtl_top',
|
42
43
|
'rtl/register/type',
|
43
44
|
'rtl/register/type/external',
|
@@ -45,6 +46,7 @@ module RgGen
|
|
45
46
|
'rtl/register_block/protocol',
|
46
47
|
'rtl/register_block/protocol/apb',
|
47
48
|
'rtl/register_block/protocol/axi4lite',
|
49
|
+
'rtl/register_block/protocol/wishbone',
|
48
50
|
'rtl/register_block/sv_rtl_top',
|
49
51
|
'rtl/register_file/sv_rtl_top'
|
50
52
|
]
|
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: rggen-systemverilog
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 0.
|
4
|
+
version: 0.26.0
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Taichi Ishitani
|
8
8
|
autorequire:
|
9
9
|
bindir: bin
|
10
10
|
cert_chain: []
|
11
|
-
date:
|
11
|
+
date: 2022-03-25 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: bundler
|
@@ -56,6 +56,8 @@ files:
|
|
56
56
|
- lib/rggen/systemverilog/ral.rb
|
57
57
|
- lib/rggen/systemverilog/ral/bit_field/type.rb
|
58
58
|
- lib/rggen/systemverilog/ral/bit_field/type/rof.rb
|
59
|
+
- lib/rggen/systemverilog/ral/bit_field/type/rotrg_rwtrg_wotrg.rb
|
60
|
+
- lib/rggen/systemverilog/ral/bit_field/type/rowo_rowotrg.rb
|
59
61
|
- lib/rggen/systemverilog/ral/bit_field/type/rwc_rws.rb
|
60
62
|
- lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb
|
61
63
|
- lib/rggen/systemverilog/ral/bit_field/type/w0trg_w1trg.rb
|
@@ -77,14 +79,16 @@ files:
|
|
77
79
|
- lib/rggen/systemverilog/rtl/bit_field/type.rb
|
78
80
|
- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb
|
79
81
|
- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb
|
80
|
-
- lib/rggen/systemverilog/rtl/bit_field/type/
|
81
|
-
- lib/rggen/systemverilog/rtl/bit_field/type/
|
82
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.erb
|
83
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb
|
82
84
|
- lib/rggen/systemverilog/rtl/bit_field/type/rof.erb
|
83
85
|
- lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
|
86
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.erb
|
87
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.rb
|
84
88
|
- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb
|
85
89
|
- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb
|
86
|
-
- lib/rggen/systemverilog/rtl/bit_field/type/
|
87
|
-
- lib/rggen/systemverilog/rtl/bit_field/type/
|
90
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/rw_rwtrg_w1.erb
|
91
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/rw_rwtrg_w1.rb
|
88
92
|
- lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb
|
89
93
|
- lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb
|
90
94
|
- lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.erb
|
@@ -97,12 +101,13 @@ files:
|
|
97
101
|
- lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb
|
98
102
|
- lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb
|
99
103
|
- lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb
|
104
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.erb
|
105
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.rb
|
100
106
|
- lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb
|
101
107
|
- lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb
|
102
108
|
- lib/rggen/systemverilog/rtl/bit_field_index.rb
|
103
109
|
- lib/rggen/systemverilog/rtl/feature.rb
|
104
110
|
- lib/rggen/systemverilog/rtl/global/array_port_format.rb
|
105
|
-
- lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb
|
106
111
|
- lib/rggen/systemverilog/rtl/indirect_index.rb
|
107
112
|
- lib/rggen/systemverilog/rtl/partial_sum.rb
|
108
113
|
- lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb
|
@@ -117,6 +122,8 @@ files:
|
|
117
122
|
- lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb
|
118
123
|
- lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb
|
119
124
|
- lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb
|
125
|
+
- lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.erb
|
126
|
+
- lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.rb
|
120
127
|
- lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb
|
121
128
|
- lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb
|
122
129
|
- lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb
|
@@ -130,6 +137,7 @@ licenses:
|
|
130
137
|
metadata:
|
131
138
|
bug_tracker_uri: https://github.com/rggen/rggen-systemverilog/issues
|
132
139
|
mailing_list_uri: https://groups.google.com/d/forum/rggen
|
140
|
+
rubygems_mfa_required: 'true'
|
133
141
|
source_code_uri: https://github.com/rggen/rggen-systemverilog
|
134
142
|
wiki_uri: https://github.com/rggen/rggen/wiki
|
135
143
|
post_install_message:
|
@@ -140,15 +148,15 @@ required_ruby_version: !ruby/object:Gem::Requirement
|
|
140
148
|
requirements:
|
141
149
|
- - ">="
|
142
150
|
- !ruby/object:Gem::Version
|
143
|
-
version: '2.
|
151
|
+
version: '2.6'
|
144
152
|
required_rubygems_version: !ruby/object:Gem::Requirement
|
145
153
|
requirements:
|
146
154
|
- - ">="
|
147
155
|
- !ruby/object:Gem::Version
|
148
156
|
version: '0'
|
149
157
|
requirements: []
|
150
|
-
rubygems_version: 3.
|
158
|
+
rubygems_version: 3.3.3
|
151
159
|
signing_key:
|
152
160
|
specification_version: 4
|
153
|
-
summary: rggen-systemverilog-0.
|
161
|
+
summary: rggen-systemverilog-0.26.0
|
154
162
|
test_files: []
|
@@ -1,22 +0,0 @@
|
|
1
|
-
# frozen_string_literal: true
|
2
|
-
|
3
|
-
RgGen.define_list_item_feature(:bit_field, :type, :ro) do
|
4
|
-
sv_rtl do
|
5
|
-
build do
|
6
|
-
unless bit_field.reference?
|
7
|
-
input :value_in, {
|
8
|
-
name: "i_#{full_name}", width: width,
|
9
|
-
array_size: array_size, array_format: array_port_format
|
10
|
-
}
|
11
|
-
end
|
12
|
-
end
|
13
|
-
|
14
|
-
main_code :bit_field, from_template: true
|
15
|
-
|
16
|
-
private
|
17
|
-
|
18
|
-
def reference_or_value_in
|
19
|
-
bit_field.reference? && reference_bit_field || value_in[loop_variables]
|
20
|
-
end
|
21
|
-
end
|
22
|
-
end
|
@@ -1,24 +0,0 @@
|
|
1
|
-
# frozen_string_literal: true
|
2
|
-
|
3
|
-
RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wo, :wo1]) do
|
4
|
-
sv_rtl do
|
5
|
-
build do
|
6
|
-
output :value_out, {
|
7
|
-
name: "o_#{full_name}", width: width,
|
8
|
-
array_size: array_size, array_format: array_port_format
|
9
|
-
}
|
10
|
-
end
|
11
|
-
|
12
|
-
main_code :bit_field, from_template: true
|
13
|
-
|
14
|
-
private
|
15
|
-
|
16
|
-
def read_action
|
17
|
-
bit_field.readable? && 'RGGEN_READ_DEFAULT' || 'RGGEN_READ_NONE'
|
18
|
-
end
|
19
|
-
|
20
|
-
def write_once
|
21
|
-
[:w1, :wo1].include?(bit_field.type) && 1 || 0
|
22
|
-
end
|
23
|
-
end
|
24
|
-
end
|
@@ -1,28 +0,0 @@
|
|
1
|
-
# frozen_string_literal: true
|
2
|
-
|
3
|
-
RgGen.define_simple_feature(:global, :fold_sv_interface_port) do
|
4
|
-
configuration do
|
5
|
-
property :fold_sv_interface_port?, default: true
|
6
|
-
|
7
|
-
input_pattern [
|
8
|
-
/true|on|yes/i, /false|off|no/i
|
9
|
-
], match_automatically: false
|
10
|
-
|
11
|
-
ignore_empty_value false
|
12
|
-
|
13
|
-
build do |value|
|
14
|
-
@fold_sv_interface_port =
|
15
|
-
if [true, false].include?(value)
|
16
|
-
value
|
17
|
-
elsif match_pattern(value)
|
18
|
-
[true, false][match_index]
|
19
|
-
else
|
20
|
-
error "cannot convert #{value.inspect} into boolean"
|
21
|
-
end
|
22
|
-
end
|
23
|
-
|
24
|
-
printable :fold_sv_interface_port do
|
25
|
-
fold_sv_interface_port?
|
26
|
-
end
|
27
|
-
end
|
28
|
-
end
|