rggen-systemverilog 0.25.1 → 0.26.0

checksums.yaml

@@ -1,7 +1,7 @@
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-  data.tar.gz: b8af85fb8a83278de85ab9b6bdbe927f5c2e6d62143f7ef7b31088e03d52dccf
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+  data.tar.gz: e2c07ce7eb68f15c9e4d2dbd0f83d7a74dbcb92ba292ba1fae8830c4ca147cb0
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data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2019-2021 Taichi Ishitani
+Copyright (c) 2019-2022 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -34,7 +34,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
 
 ## Copyright & License
 
-Copyright © 2019-2021 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2019-2022 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/systemverilog/common/utility/identifier.rb

@@ -96,7 +96,7 @@ module RgGen
 
           def __index_factors__
             Array.new(@array_size.size) do |i|
-              i.zero? ? nil : __reduce_array__(@array_size[-i..-1], :*, 1)
+              i.zero? ? nil : __reduce_array__(@array_size[-i..], :*, 1)
             end
           end
 

data/lib/rggen/systemverilog/ral/bit_field/type/rotrg_rwtrg_wotrg.rb

@@ -0,0 +1,9 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rotrg, :rwtrg, :wotrg]) do
+  sv_ral do
+    access do
+      { rotrg: :ro, rwtrg: :rw, wotrg: :wo }[bit_field.type]
+    end
+  end
+end

data/lib/rggen/systemverilog/ral/bit_field/type/rowo_rowotrg.rb

@@ -0,0 +1,8 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rowo, :rowotrg]) do
+  sv_ral do
+    access 'rowo'
+    model_name { 'rggen_ral_rowo_field' }
+  end
+end

data/lib/rggen/systemverilog/ral/bit_field/type.rb

@@ -4,11 +4,20 @@ RgGen.define_list_feature(:bit_field, :type) do
   sv_ral do
     base_feature do
       define_helpers do
-        attr_setter :access
+        def access(access_type = nil, &block)
+          attribute_accessor('@access', access_type, &block)
+        end
 
         def model_name(name = nil, &block)
-          @model_name = name || block || @model_name
-          @model_name
+          attribute_accessor('@model_name', name, &block)
+        end
+
+        private
+
+        def attribute_accessor(variable_name, value, &block)
+          (new_value = value || block) &&
+            instance_variable_set(variable_name, new_value)
+          instance_variable_get(variable_name)
         end
       end
 
@@ -24,12 +33,11 @@ RgGen.define_list_feature(:bit_field, :type) do
       end
 
       def access
-        (helper.access || bit_field.type).to_s.upcase
+        eval_attribute(:access, bit_field.type).to_s.upcase
       end
 
       def model_name
-        name = helper.model_name
-        name.is_a?(Proc) && instance_eval(&name) || name || 'rggen_ral_field'
+        eval_attribute(:model_name, 'rggen_ral_field')
       end
 
       def constructors
@@ -73,6 +81,11 @@ RgGen.define_list_feature(:bit_field, :type) do
           ''
         end
       end
+
+      def eval_attribute(attribute, default_value)
+        value = helper.__send__(attribute)
+        value.is_a?(Proc) && instance_eval(&value) || value || default_value
+      end
     end
 
     default_feature do

data/lib/rggen/systemverilog/ral/register_common.rb

@@ -9,7 +9,7 @@ module RgGen
         def array_indices
           if component.array?
             index_table = component.array_size.map { |size| (0...size).to_a }
-            index_table[0].product(*index_table[1..-1])
+            index_table[0].product(*index_table[1..])
           else
             [nil]
           end

data/lib/rggen/systemverilog/ral.rb

@@ -20,6 +20,8 @@ module RgGen
         plugin.files [
           'ral/bit_field/type',
           'ral/bit_field/type/rof',
+          'ral/bit_field/type/rotrg_rwtrg_wotrg',
+          'ral/bit_field/type/rowo_rowotrg',
           'ral/bit_field/type/rwc_rws',
           'ral/bit_field/type/rwe_rwl',
           'ral/bit_field/type/w0trg_w1trg',

data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb

@@ -7,6 +7,8 @@ rggen_bit_field #(
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  (<%= write_enable %>),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/{ro.erb → ro_rotrg.erb}

@@ -1,10 +1,14 @@
 rggen_bit_field #(
-  .WIDTH    (<%= width %>),
-  .STORAGE  (0)
+  .WIDTH              (<%= width %>),
+  .STORAGE            (0),
+  .EXTERNAL_READ_DATA (1),
+  .TRIGGER            (<%= trigger %>)
 ) u_bit_field (
-  .i_clk              ('0),
-  .i_rst_n            ('0),
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (<%= read_trigger_signal %>),
   .i_sw_write_enable  ('0),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb

@@ -0,0 +1,40 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:ro, :rotrg]) do
+  sv_rtl do
+    build do
+      unless bit_field.reference?
+        input :value_in, {
+          name: "i_#{full_name}", width: width,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      if rotrg?
+        output :read_trigger, {
+          name: "o_#{full_name}_read_trigger", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def rotrg?
+      bit_field.type == :rotrg
+    end
+
+    def trigger
+      rotrg? && 1 || 0
+    end
+
+    def read_trigger_signal
+      rotrg? && read_trigger[loop_variables] || nil
+    end
+
+    def reference_or_value_in
+      reference_bit_field || value_in[loop_variables]
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/rof.erb

@@ -1,10 +1,13 @@
 rggen_bit_field #(
-  .WIDTH    (<%= width %>),
-  .STORAGE  (0)
+  .WIDTH              (<%= width %>),
+  .STORAGE            (0),
+  .EXTERNAL_READ_DATA (1)
 ) u_bit_field (
   .i_clk              ('0),
   .i_rst_n            ('0),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  ('0),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.erb

@@ -0,0 +1,21 @@
+rggen_bit_field #(
+  .WIDTH              (<%= width %>),
+  .INITIAL_VALUE      (<%= initial_value %>),
+  .EXTERNAL_READ_DATA (1),
+  .TRIGGER            (<%= trigger %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (<%= write_trigger_signal %>),
+  .o_read_trigger     (<%= read_trigger_signal %>),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            (<%= reference_or_value_in %>),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.rb

@@ -0,0 +1,52 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rowo, :rowotrg]) do
+  sv_rtl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+      unless bit_field.reference?
+        input :value_in, {
+          name: "i_#{full_name}", width: width,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      if rowotrg?
+        output :write_trigger, {
+          name: "o_#{full_name}_write_trigger", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+        output :read_trigger, {
+          name: "o_#{full_name}_read_trigger", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def rowotrg?
+      bit_field.type == :rowotrg
+    end
+
+    def trigger
+      rowotrg? && 1 || 0
+    end
+
+    def write_trigger_signal
+      rowotrg? && write_trigger[loop_variables] || nil
+    end
+
+    def read_trigger_signal
+      rowotrg? && read_trigger[loop_variables] || nil
+    end
+
+    def reference_or_value_in
+      reference_bit_field || value_in[loop_variables]
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb

@@ -7,6 +7,8 @@ rggen_bit_field #(
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  (<%= write_enable %>),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/{rw_w1_wo_wo1.erb → rw_rwtrg_w1.erb}

@@ -1,12 +1,14 @@
 rggen_bit_field #(
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>),
-  .SW_READ_ACTION (<%= read_action %>),
-  .SW_WRITE_ONCE  (<%= write_once %>)
+  .SW_WRITE_ONCE  (<%= write_once %>),
+  .TRIGGER        (<%= trigger %>)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (<%= write_trigger_signal %>),
+  .o_read_trigger     (<%= read_trigger_signal %>),
   .i_sw_write_enable  ('1),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/rw_rwtrg_w1.rb

@@ -0,0 +1,46 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rw, :rwtrg, :w1]) do
+  sv_rtl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+      if rwtrg?
+        output :write_trigger, {
+          name: "o_#{full_name}_write_trigger", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+        output :read_trigger, {
+          name: "o_#{full_name}_read_trigger", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def rwtrg?
+      bit_field.type == :rwtrg
+    end
+
+    def trigger
+      rwtrg? && 1 || 0
+    end
+
+    def write_trigger_signal
+      rwtrg? && write_trigger[loop_variables] || nil
+    end
+
+    def read_trigger_signal
+      rwtrg? && read_trigger[loop_variables] || nil
+    end
+
+    def write_once
+      bit_field.type == :w1 && 1 || 0
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb

@@ -6,6 +6,8 @@ rggen_bit_field #(
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  ('1),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.erb

@@ -6,6 +6,8 @@ rggen_bit_field #(
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  (<%= control_signal %>),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb

@@ -5,6 +5,8 @@ rggen_bit_field #(
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  ('1),
   .i_hw_write_enable  (<%= set_signal %>),
   .i_hw_write_data    (<%= value_in[loop_variables] %>),

data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb

@@ -7,6 +7,8 @@ rggen_bit_field #(
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  ('1),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb

@@ -6,6 +6,8 @@ rggen_bit_field #(
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  ('1),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.erb

@@ -0,0 +1,22 @@
+rggen_bit_field #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>),
+  .SW_READ_ACTION (RGGEN_READ_NONE),
+  .SW_WRITE_ONCE  (<%= write_once %>),
+  .TRIGGER        (<%= trigger %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (<%= write_trigger_signal %>),
+  .o_read_trigger     (),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.rb

@@ -0,0 +1,38 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:wo, :wo1, :wotrg]) do
+  sv_rtl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+      if wotrg?
+        output :write_trigger, {
+          name: "o_#{full_name}_write_trigger", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def wotrg?
+      bit_field.type == :wotrg
+    end
+
+    def trigger
+      wotrg? && 1 || 0
+    end
+
+    def write_trigger_signal
+      wotrg? && write_trigger[loop_variables] || nil
+    end
+
+    def write_once
+      bit_field.type == :wo1 && 1 || 0
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb

@@ -6,6 +6,8 @@ rggen_bit_field #(
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  ('1),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/register/type/external.rb

@@ -3,63 +3,14 @@
 RgGen.define_list_item_feature(:register, :type, :external) do
   sv_rtl do
     build do
-      if configuration.fold_sv_interface_port?
-        interface_port :bus_if, {
-          name: "#{register.name}_bus_if",
-          interface_type: 'rggen_bus_if',
-          modport: 'master'
-        }
-      else
-        output :valid, {
-          name: "o_#{register.name}_valid", width: 1
-        }
-        output :access, {
-          name: "o_#{register.name}_access", width: '$bits(rggen_access)'
-        }
-        output :address, {
-          name: "o_#{register.name}_address", width: address_width
-        }
-        output :write_data, {
-          name: "o_#{register.name}_data", width: bus_width
-        }
-        output :strobe, {
-          name: "o_#{register.name}_strobe", width: byte_width
-        }
-        input :ready, {
-          name: "i_#{register.name}_ready", width: 1
-        }
-        input :status, {
-          name: "i_#{register.name}_status", width: 2
-        }
-        input :read_data, {
-          name: "i_#{register.name}_data", width: bus_width
-        }
-        interface :bus_if, {
-          name: 'bus_if', interface_type: 'rggen_bus_if',
-          parameter_values: [address_width, bus_width],
-          variables: [
-            'valid', 'access', 'address', 'write_data', 'strobe',
-            'ready', 'status', 'read_data'
-          ]
-        }
-      end
+      interface_port :bus_if, {
+        name: "#{register.name}_bus_if",
+        interface_type: 'rggen_bus_if',
+        modport: 'master'
+      }
     end
 
     main_code :register, from_template: true
-    main_code :register do |code|
-      unless configuration.fold_sv_interface_port?
-        [
-          [valid, bus_if.valid],
-          [access, bus_if.access],
-          [address, bus_if.address],
-          [write_data, bus_if.write_data],
-          [strobe, bus_if.strobe],
-          [bus_if.ready, ready],
-          [bus_if.status, "rggen_status'(#{status})"],
-          [bus_if.read_data, read_data]
-        ].map { |lhs, rhs| code << assign(lhs, rhs) << nl }
-      end
-    end
 
     private
 

data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb

@@ -21,68 +21,11 @@ RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
 
   sv_rtl do
     build do
-      if configuration.fold_sv_interface_port?
-        interface_port :apb_if, {
-          name: 'apb_if', interface_type: 'rggen_apb_if', modport: 'slave'
-        }
-      else
-        input :psel, {
-          name: 'i_psel', width: 1
-        }
-        input :penable, {
-          name: 'i_penable', width: 1
-        }
-        input :paddr, {
-          name: 'i_paddr', width: address_width
-        }
-        input :pprot, {
-          name: 'i_pprot', width: 3
-        }
-        input :pwrite, {
-          name: 'i_pwrite', width: 1
-        }
-        input :pstrb, {
-          name: 'i_pstrb', width: byte_width
-        }
-        input :pwdata, {
-          name: 'i_pwdata', width: bus_width
-        }
-        output :pready, {
-          name: 'o_pready', width: 1
-        }
-        output :prdata, {
-          name: 'o_prdata', width: bus_width
-        }
-        output :pslverr, {
-          name: 'o_pslverr', width: 1
-        }
-        interface :apb_if, {
-          name: 'apb_if', interface_type: 'rggen_apb_if',
-          parameter_values: [address_width, bus_width],
-          variables: [
-            'psel', 'penable', 'paddr', 'pprot', 'pwrite', 'pstrb', 'pwdata',
-            'pready', 'prdata', 'pslverr'
-          ]
-        }
-      end
+      interface_port :apb_if, {
+        name: 'apb_if', interface_type: 'rggen_apb_if', modport: 'slave'
+      }
     end
 
     main_code :register_block, from_template: true
-    main_code :register_block do |code|
-      unless configuration.fold_sv_interface_port?
-        [
-          [apb_if.psel, psel],
-          [apb_if.penable, penable],
-          [apb_if.paddr, paddr],
-          [apb_if.pprot, pprot],
-          [apb_if.pwrite, pwrite],
-          [apb_if.pstrb, pstrb],
-          [apb_if.pwdata, pwdata],
-          [pready, apb_if.pready],
-          [prdata, apb_if.prdata],
-          [pslverr, apb_if.pslverr]
-        ].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
-      end
-    end
   end
 end

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb

@@ -19,132 +19,18 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
       parameter :write_first, {
         name: 'WRITE_FIRST', data_type: :bit, default: 1
       }
-      if configuration.fold_sv_interface_port?
-        interface_port :axi4lite_if, {
-          name: 'axi4lite_if',
-          interface_type: 'rggen_axi4lite_if', modport: 'slave'
-        }
-      else
-        input :awvalid, {
-          name: 'i_awvalid', width: 1
-        }
-        output :awready, {
-          name: 'o_awready', width: 1
-        }
-        input :awid, {
-          name: 'i_awid', width: id_port_width
-        }
-        input :awaddr, {
-          name: 'i_awaddr', width: address_width
-        }
-        input :awprot, {
-          name: 'i_awprot', width: 3
-        }
-        input :wvalid, {
-          name: 'i_wvalid', width: 1
-        }
-        output :wready, {
-          name: 'o_wready', width: 1
-        }
-        input :wdata, {
-          name: 'i_wdata', width: bus_width
-        }
-        input :wstrb, {
-          name: 'i_wstrb', width: byte_width
-        }
-        output :bvalid, {
-          name: 'o_bvalid', width: 1
-        }
-        output :bid, {
-          name: 'o_bid', width: id_port_width
-        }
-        input :bready, {
-          name: 'i_bready', width: 1
-        }
-        output :bresp, {
-          name: 'o_bresp', width: 2
-        }
-        input :arvalid, {
-          name: 'i_arvalid', width: 1
-        }
-        output :arready, {
-          name: 'o_arready', width: 1
-        }
-        input :arid, {
-          name: 'i_arid', width: id_port_width
-        }
-        input :araddr, {
-          name: 'i_araddr', width: address_width
-        }
-        input :arprot, {
-          name: 'i_arprot', width: 3
-        }
-        output :rvalid, {
-          name: 'o_rvalid', width: 1
-        }
-        input :rready, {
-          name: 'i_rready', width: 1
-        }
-        output :rid, {
-          name: 'o_rid', width: id_port_width
-        }
-        output :rdata, {
-          name: 'o_rdata', width: bus_width
-        }
-        output :rresp, {
-          name: 'o_rresp', width: 2
-        }
-        interface :axi4lite_if, {
-          name: 'axi4lite_if', interface_type: 'rggen_axi4lite_if',
-          parameter_values: [id_width, address_width, bus_width],
-          variables: [
-            'awvalid', 'awready', 'awid', 'awaddr', 'awprot',
-            'wvalid', 'wready', 'wdata', 'wstrb',
-            'bvalid', 'bready', 'bid', 'bresp',
-            'arvalid', 'arready', 'arid', 'araddr', 'arprot',
-            'rvalid', 'rready', 'rid', 'rdata', 'rresp'
-          ]
-        }
-      end
+      interface_port :axi4lite_if, {
+        name: 'axi4lite_if',
+        interface_type: 'rggen_axi4lite_if', modport: 'slave'
+      }
     end
 
     main_code :register_block, from_template: true
-    main_code :register_block do |code|
-      configuration.fold_sv_interface_port? || assign_axi4lite_signals(code)
-    end
 
     private
 
     def id_port_width
       "((#{id_width}>0)?#{id_width}:1)"
     end
-
-    def assign_axi4lite_signals(code)
-      [
-        [axi4lite_if.awvalid, awvalid],
-        [awready, axi4lite_if.awready],
-        [axi4lite_if.awid, awid],
-        [axi4lite_if.awaddr, awaddr],
-        [axi4lite_if.awprot, awprot],
-        [axi4lite_if.wvalid, wvalid],
-        [wready, axi4lite_if.wready],
-        [axi4lite_if.wdata, wdata],
-        [axi4lite_if.wstrb, wstrb],
-        [bvalid, axi4lite_if.bvalid],
-        [axi4lite_if.bready, bready],
-        [bid, axi4lite_if.bid],
-        [bresp, axi4lite_if.bresp],
-        [axi4lite_if.arvalid, arvalid],
-        [arready, axi4lite_if.arready],
-        [axi4lite_if.arid, arid],
-        [axi4lite_if.araddr, araddr],
-        [axi4lite_if.arprot, arprot],
-        [rvalid, axi4lite_if.rvalid],
-        [axi4lite_if.rready, rready],
-        [rid, axi4lite_if.rid],
-        [rdata, axi4lite_if.rdata],
-        [rresp, axi4lite_if.rresp]
-      ].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
-    end
   end
 end

data/lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.erb

@@ -0,0 +1,17 @@
+rggen_wishbone_adapter #(
+  .ADDRESS_WIDTH        (<%= address_width %>),
+  .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
+  .BUS_WIDTH            (<%= bus_width %>),
+  .REGISTERS            (<%= total_registers %>),
+  .PRE_DECODE           (<%= pre_decode %>),
+  .BASE_ADDRESS         (<%= base_address %>),
+  .BYTE_SIZE            (<%= byte_size %>),
+  .ERROR_STATUS         (<%= error_status %>),
+  .DEFAULT_READ_DATA    (<%= default_read_data %>),
+  .USE_STALL            (<%= use_stall %>)
+) u_adapter (
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
+  .wishbone_if  (<%= wishbone_if %>),
+  .register_if  (<%= register_if %>)
+);

data/lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.rb

@@ -0,0 +1,26 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :wishbone) do
+  configuration do
+    verify(:component) do
+      error_condition { configuration.bus_width > 64 }
+      message do
+        'bus width over 64 bit is not supported: ' \
+        "#{configuration.bus_width}"
+      end
+    end
+  end
+
+  sv_rtl do
+    build do
+      parameter :use_stall, {
+        name: 'USE_STALL', data_type: :bit, default: 1
+      }
+      interface_port :wishbone_if, {
+        name: 'wishbone_if', interface_type: 'rggen_wishbone_if', modport: 'slave'
+      }
+    end
+
+    main_code :register_block, from_template: true
+  end
+end

data/lib/rggen/systemverilog/rtl/setup.rb

@@ -3,11 +3,9 @@
 require 'rggen/systemverilog/rtl'
 
 RgGen.register_plugin RgGen::SystemVerilog::RTL do |builder|
-  builder.enable :global, [
-    :array_port_format, :fold_sv_interface_port
-  ]
+  builder.enable :global, [:array_port_format]
   builder.enable :register_block, [:sv_rtl_top, :protocol]
-  builder.enable :register_block, :protocol, [:apb, :axi4lite]
+  builder.enable :register_block, :protocol, [:apb, :axi4lite, :wishbone]
   builder.enable :register_file, [:sv_rtl_top]
   builder.enable :register, [:sv_rtl_top]
   builder.enable :bit_field, [:sv_rtl_top]

data/lib/rggen/systemverilog/rtl.rb

@@ -25,19 +25,20 @@ module RgGen
           'rtl/bit_field/sv_rtl_top',
           'rtl/bit_field/type',
           'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
-          'rtl/bit_field/type/ro',
+          'rtl/bit_field/type/ro_rotrg',
           'rtl/bit_field/type/rof',
+          'rtl/bit_field/type/rowo_rowotrg',
           'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
-          'rtl/bit_field/type/rw_w1_wo_wo1',
+          'rtl/bit_field/type/rw_rwtrg_w1',
           'rtl/bit_field/type/rwc',
           'rtl/bit_field/type/rwe_rwl',
           'rtl/bit_field/type/rws',
           'rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
           'rtl/bit_field/type/w0t_w1t',
           'rtl/bit_field/type/w0trg_w1trg',
+          'rtl/bit_field/type/wo_wo1_wotrg',
           'rtl/bit_field/type/wrc_wrs',
           'rtl/global/array_port_format',
-          'rtl/global/fold_sv_interface_port',
           'rtl/register/sv_rtl_top',
           'rtl/register/type',
           'rtl/register/type/external',
@@ -45,6 +46,7 @@ module RgGen
           'rtl/register_block/protocol',
           'rtl/register_block/protocol/apb',
           'rtl/register_block/protocol/axi4lite',
+          'rtl/register_block/protocol/wishbone',
           'rtl/register_block/sv_rtl_top',
           'rtl/register_file/sv_rtl_top'
         ]

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.25.1'
+    VERSION = '0.26.0'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.25.1
+  version: 0.26.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2021-05-16 00:00:00.000000000 Z
+date: 2022-03-25 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -56,6 +56,8 @@ files:
 - lib/rggen/systemverilog/ral.rb
 - lib/rggen/systemverilog/ral/bit_field/type.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rof.rb
+- lib/rggen/systemverilog/ral/bit_field/type/rotrg_rwtrg_wotrg.rb
+- lib/rggen/systemverilog/ral/bit_field/type/rowo_rowotrg.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rwc_rws.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb
 - lib/rggen/systemverilog/ral/bit_field/type/w0trg_w1trg.rb
@@ -77,14 +79,16 @@ files:
 - lib/rggen/systemverilog/rtl/bit_field/type.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/ro.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/ro.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rw_rwtrg_w1.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rw_rwtrg_w1.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.erb
@@ -97,12 +101,13 @@ files:
 - lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb
 - lib/rggen/systemverilog/rtl/bit_field_index.rb
 - lib/rggen/systemverilog/rtl/feature.rb
 - lib/rggen/systemverilog/rtl/global/array_port_format.rb
-- lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb
 - lib/rggen/systemverilog/rtl/indirect_index.rb
 - lib/rggen/systemverilog/rtl/partial_sum.rb
 - lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb
@@ -117,6 +122,8 @@ files:
 - lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb
 - lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb
 - lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb
+- lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.erb
+- lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.rb
 - lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb
 - lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb
@@ -130,6 +137,7 @@ licenses:
 metadata:
   bug_tracker_uri: https://github.com/rggen/rggen-systemverilog/issues
   mailing_list_uri: https://groups.google.com/d/forum/rggen
+  rubygems_mfa_required: 'true'
   source_code_uri: https://github.com/rggen/rggen-systemverilog
   wiki_uri: https://github.com/rggen/rggen/wiki
 post_install_message: 
@@ -140,15 +148,15 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: '2.5'
+      version: '2.6'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.2.3
+rubygems_version: 3.3.3
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.25.1
+summary: rggen-systemverilog-0.26.0
 test_files: []

data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb

@@ -1,22 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, :ro) do
-  sv_rtl do
-    build do
-      unless bit_field.reference?
-        input :value_in, {
-          name: "i_#{full_name}", width: width,
-          array_size: array_size, array_format: array_port_format
-        }
-      end
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def reference_or_value_in
-      bit_field.reference? && reference_bit_field || value_in[loop_variables]
-    end
-  end
-end

data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb

@@ -1,24 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wo, :wo1]) do
-  sv_rtl do
-    build do
-      output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
-      }
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def read_action
-      bit_field.readable? && 'RGGEN_READ_DEFAULT' || 'RGGEN_READ_NONE'
-    end
-
-    def write_once
-      [:w1, :wo1].include?(bit_field.type) && 1 || 0
-    end
-  end
-end

data/lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb

@@ -1,28 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_simple_feature(:global, :fold_sv_interface_port) do
-  configuration do
-    property :fold_sv_interface_port?, default: true
-
-    input_pattern [
-      /true|on|yes/i, /false|off|no/i
-    ], match_automatically: false
-
-    ignore_empty_value false
-
-    build do |value|
-      @fold_sv_interface_port =
-        if [true, false].include?(value)
-          value
-        elsif match_pattern(value)
-          [true, false][match_index]
-        else
-          error "cannot convert #{value.inspect} into boolean"
-        end
-    end
-
-    printable :fold_sv_interface_port do
-      fold_sv_interface_port?
-    end
-  end
-end