rggen-systemverilog 0.19.0 → 0.23.0

data/lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb

@@ -0,0 +1,30 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_file, :sv_rtl_top) do
+  sv_rtl do
+    include RgGen::SystemVerilog::RTL::RegisterIndex
+
+    main_code :register_file do
+      local_scope("g_#{register_file.name}") do |scope|
+        scope.top_scope top_scope?
+        scope.loop_size loop_size
+        scope.body(&method(:body_code))
+      end
+    end
+
+    private
+
+    def top_scope?
+      register_file(:upper).nil?
+    end
+
+    def loop_size
+      (register_file.array? || nil) &&
+        local_loop_variables.zip(register_file.array_size).to_h
+    end
+
+    def body_code(code)
+      register_file.generate_code(code, :register_file, :top_down, 1)
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/register_index.rb

@@ -0,0 +1,112 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RTL
+      module RegisterIndex
+        include PartialSum
+
+        EXPORTED_METHODS = [
+          :loop_variables, :local_loop_variables,
+          :local_index, :local_indices,
+          :index, :inside_roop?
+        ].freeze
+
+        def self.included(feature)
+          feature.module_eval do
+            EXPORTED_METHODS.each { |m| export m }
+
+            pre_build do
+              @base_index = files_and_registers.sum(&:count)
+            end
+          end
+        end
+
+        def loop_variables
+          (inside_roop? || nil) &&
+            [*upper_register_file&.loop_variables, *local_loop_variables]
+        end
+
+        def local_loop_variables
+          (component.array? || nil) &&
+            begin
+              start_depth = (upper_register_file&.loop_variables&.size || 0) + 1
+              Array.new(component.array_size.size) do |i|
+                create_identifier(loop_index(i + start_depth))
+              end
+            end
+        end
+
+        def local_index
+          (component.array? || nil) &&
+            local_index_coefficients
+              .zip(local_loop_variables)
+              .map { |operands| product(operands, false) }
+              .join('+')
+        end
+
+        def local_indices
+          [*upper_register_file&.local_indices, local_index]
+        end
+
+        def index(offset_or_offsets = nil)
+          operands = index_operands(offset_or_offsets)
+          partial_indices = partial_sums(operands)
+          if partial_indices.empty? || partial_indices.all?(&method(:integer?))
+            partial_indices.sum
+          else
+            partial_indices.join('+')
+          end
+        end
+
+        def inside_roop?
+          component.array? || upper_register_file&.inside_roop? || false
+        end
+
+        private
+
+        def upper_register_file
+          component.register_file
+        end
+
+        def local_index_coefficients
+          coefficients = []
+          component.array_size.reverse.inject(1) do |total, size|
+            coefficients.unshift(total)
+            total * size
+          end
+          coefficients
+        end
+
+        def index_operands(offset_or_offsets)
+          offsets = offset_or_offsets && Array(offset_or_offsets)
+          [
+            *upper_register_file&.index(offsets&.slice(0..-2)),
+            @base_index,
+            *local_register_index(offsets&.slice(-1))
+          ]
+        end
+
+        def local_register_index(offset)
+          (component.array? || nil) &&
+            begin
+              operands = [component.count(false), offset || local_index]
+              product(operands, true)
+            end
+        end
+
+        def product(operands, need_bracket)
+          if operands.all?(&method(:integer?))
+            operands.reduce(:*)
+          elsif operands.first == 1
+            operands.last
+          elsif need_bracket
+            "#{operands.first}*(#{operands.last})"
+          else
+            operands.join('*')
+          end
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/setup.rb

@@ -2,12 +2,13 @@
 
 require 'rggen/systemverilog/rtl'
 
-RgGen.setup :'rggen-sv-rtl', RgGen::SystemVerilog::RTL do |builder|
+RgGen.setup RgGen::SystemVerilog::RTL do |builder|
   builder.enable :global, [
     :array_port_format, :fold_sv_interface_port
   ]
   builder.enable :register_block, [:sv_rtl_top, :protocol]
   builder.enable :register_block, :protocol, [:apb, :axi4lite]
+  builder.enable :register_file, [:sv_rtl_top]
   builder.enable :register, [:sv_rtl_top]
   builder.enable :bit_field, [:sv_rtl_top]
 end

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.19.0'
+    VERSION = '0.23.0'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.19.0
+  version: 0.23.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2020-02-17 00:00:00.000000000 Z
+date: 2020-08-25 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: docile
@@ -93,22 +93,26 @@ files:
 - lib/rggen/systemverilog/ral/register/type/external.rb
 - lib/rggen/systemverilog/ral/register/type/indirect.erb
 - lib/rggen/systemverilog/ral/register/type/indirect.rb
-- lib/rggen/systemverilog/ral/register_block/sv_ral_block_model.erb
+- lib/rggen/systemverilog/ral/register_block/sv_ral_model.erb
+- lib/rggen/systemverilog/ral/register_block/sv_ral_model.rb
 - lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb
+- lib/rggen/systemverilog/ral/register_common.rb
+- lib/rggen/systemverilog/ral/register_file/sv_ral_model.erb
+- lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb
 - lib/rggen/systemverilog/ral/setup.rb
 - lib/rggen/systemverilog/rtl.rb
 - lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/bit_field/type.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/ro.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/ro.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb
@@ -119,15 +123,20 @@ files:
 - lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rws.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rws.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs_wcrs.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs_wcrs.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src_wsrc.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src_wsrc.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb
 - lib/rggen/systemverilog/rtl/feature.rb
 - lib/rggen/systemverilog/rtl/global/array_port_format.rb
 - lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb
+- lib/rggen/systemverilog/rtl/partial_sum.rb
 - lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/register/type.rb
 - lib/rggen/systemverilog/rtl/register/type/default.erb
@@ -142,6 +151,8 @@ files:
 - lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb
 - lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb
 - lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb
+- lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb
+- lib/rggen/systemverilog/rtl/register_index.rb
 - lib/rggen/systemverilog/rtl/setup.rb
 - lib/rggen/systemverilog/version.rb
 homepage: https://github.com/rggen/rggen-systemverilog
@@ -170,5 +181,5 @@ requirements: []
 rubygems_version: 3.1.2
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.19.0
+summary: rggen-systemverilog-0.23.0
 test_files: []

data/lib/rggen/systemverilog/ral/register_block/sv_ral_block_model.erb

@@ -1,11 +0,0 @@
-function new(string name);
-  super.new(name);
-endfunction
-function void build();
-<% reg_model_constructors.each do |constructor| %>
-  <%= constructor %>
-<% end %>
-endfunction
-function uvm_reg_map create_default_map();
-  return create_map("default_map", 0, <%= byte_width %>, UVM_LITTLE_ENDIAN, 1);
-endfunction