rggen-systemverilog 0.19.0 → 0.23.0

data/lib/rggen/systemverilog/rtl/bit_field/type/{rc_w0c_w1c.rb → rc_w0c_w1c_wc_woc.rb}

@@ -1,18 +1,18 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c]) do
+RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc]) do
   sv_rtl do
     build do
-      input :register_block, :set, {
+      input :set, {
         name: "i_#{full_name}_set", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }
       if bit_field.reference?
-        output :register_block, :value_unmasked, {
+        output :value_unmasked, {
           name: "o_#{full_name}_unmasked", data_type: :logic, width: width,
           array_size: array_size, array_format: array_port_format
         }
@@ -24,15 +24,16 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c]) do
     private
 
     def module_name
-      if bit_field.type == :rc
-        'rggen_bit_field_rc'
-      else
-        'rggen_bit_field_w01c'
-      end
+      bit_field.type == :rc && 'rggen_bit_field_rc' || 'rggen_bit_field_w01c_wc_woc'
     end
 
     def clear_value
-      bin({ w0c: 0, w1c: 1 }[bit_field.type], 1)
+      value = { w0c: 0b00, w1c: 0b01, wc: 0b10, woc: 0b10 }[bit_field.type]
+      bin(value, 2)
+    end
+
+    def write_only
+      bit_field.write_only? && 1 || 0
     end
 
     def value_out_unmasked

data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb

@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, :ro) do
   sv_rtl do
     build do
       unless bit_field.reference?
-        input :register_block, :value_in, {
+        input :value_in, {
           name: "i_#{full_name}", data_type: :logic, width: width,
           array_size: array_size, array_format: array_port_format
         }

data/lib/rggen/systemverilog/rtl/bit_field/type/{rs_w0s_w1s.erb → rs_w0s_w1s_ws_wos.erb}

@@ -1,6 +1,7 @@
 <%= module_name %> #(
-<% if [:w0s, :w1s].include?(bit_field.type) %>
+<% if bit_field.type != :rs %>
   .SET_VALUE      (<%= set_value %>),
+  .WRITE_ONLY     (<%= write_only %>),
 <% end %>
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>)

data/lib/rggen/systemverilog/rtl/bit_field/type/{rs_w0s_w1s.rb → rs_w0s_w1s_ws_wos.rb}

@@ -1,13 +1,13 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s]) do
+RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos]) do
   sv_rtl do
     build do
-      input :register_block, :clear, {
+      input :clear, {
         name: "i_#{full_name}_clear", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }
@@ -18,15 +18,16 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s]) do
     private
 
     def module_name
-      if bit_field.type == :rs
-        'rggen_bit_field_rs'
-      else
-        'rggen_bit_field_w01s'
-      end
+      bit_field.type == :rs && 'rggen_bit_field_rs' || 'rggen_bit_field_w01s_ws_wos'
     end
 
     def set_value
-      bin({ w0s: 0, w1s: 1 }[bit_field.type], 1)
+      value = { w0s: 0b00, w1s: 0b01, ws: 0b10, wos: 0b10 }[bit_field.type]
+      bin(value, 2)
+    end
+
+    def write_only
+      bit_field.write_only? && 1 || 0
     end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb

@@ -3,7 +3,7 @@
 RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wo, :wo1]) do
   sv_rtl do
     build do
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }

data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb

@@ -4,12 +4,12 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
   sv_rtl do
     build do
       unless bit_field.reference?
-        input :register_block, :clear, {
+        input :clear, {
           name: "i_#{full_name}_clear", data_type: :logic, width: 1,
           array_size: array_size, array_format: array_port_format
         }
       end
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }

data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb

@@ -4,12 +4,12 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwe) do
   sv_rtl do
     build do
       unless bit_field.reference?
-        input :register_block, :enable, {
+        input :enable, {
           name: "i_#{full_name}_enable", data_type: :logic, width: 1,
           array_size: array_size, array_format: array_port_format
         }
       end
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }

data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb

@@ -4,12 +4,12 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwl) do
   sv_rtl do
     build do
       unless bit_field.reference?
-        input :register_block, :lock, {
+        input :lock, {
           name: "i_#{full_name}_lock", data_type: :logic, width: 1,
           array_size: array_size, array_format: array_port_format
         }
       end
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }

data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb

@@ -4,16 +4,16 @@ RgGen.define_list_item_feature(:bit_field, :type, :rws) do
   sv_rtl do
     build do
       unless bit_field.reference?
-        input :register_block, :set, {
+        input :set, {
           name: "i_#{full_name}_set", data_type: :logic, width: 1,
           array_size: array_size, array_format: array_port_format
         }
       end
-      input :register_block, :value_in, {
+      input :value_in, {
         name: "i_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }

data/lib/rggen/systemverilog/rtl/bit_field/type/{w0crs_w1crs.erb → w0crs_w1crs_wcrs.erb}

@@ -1,4 +1,4 @@
-rggen_bit_field_w01crs #(
+rggen_bit_field_w01crs_wcrs #(
   .CLEAR_VALUE    (<%= clear_value %>),
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>)

data/lib/rggen/systemverilog/rtl/bit_field/type/{w0crs_w1crs.rb → w0crs_w1crs_wcrs.rb}

@@ -1,9 +1,9 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs]) do
+RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs, :wcrs]) do
   sv_rtl do
     build do
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }
@@ -14,8 +14,8 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs]) do
     private
 
     def clear_value
-      value = (bit_field.type == :w0crs && 0) || 1
-      bin(value, 1)
+      value = { w0crs: 0b00, w1crs: 0b01, wcrs: 0b10 }[bit_field.type]
+      bin(value, 2)
     end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/{w0src_w1src.erb → w0src_w1src_wsrc.erb}

@@ -1,4 +1,4 @@
-rggen_bit_field_w01src #(
+rggen_bit_field_w01src_wsrc #(
   .SET_VALUE      (<%= set_value %>),
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>)

data/lib/rggen/systemverilog/rtl/bit_field/type/{w0src_w1src.rb → w0src_w1src_wsrc.rb}

@@ -1,9 +1,9 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src]) do
+RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src, :wsrc]) do
   sv_rtl do
     build do
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }
@@ -14,8 +14,8 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src]) do
     private
 
     def set_value
-      value = (bit_field.type == :w0src && 0) || 1
-      bin(value, 1)
+      value = { w0src: 0b00, w1src: 0b01, wsrc: 0b10 }[bit_field.type]
+      bin(value, 2)
     end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb

@@ -0,0 +1,10 @@
+rggen_bit_field_w01t #(
+  .TOGGLE_VALUE   (<%= toggle_value %>),
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
+  .bit_field_if (<%= bit_field_if %>),
+  .o_value      (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb

@@ -0,0 +1,20 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:w0t, :w1t]) do
+  sv_rtl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def toggle_value
+      bin({ w0t: 0, w1t: 1 }[bit_field.type], 1)
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb

@@ -3,7 +3,7 @@
 RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
   sv_rtl do
     build do
-      output :register_block, :trigger, {
+      output :trigger, {
         name: "o_#{full_name}_trigger", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }

data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb

@@ -0,0 +1,9 @@
+rggen_bit_field_<%= bit_field.type %> #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
+  .bit_field_if (<%= bit_field_if %>),
+  .o_value      (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb

@@ -0,0 +1,14 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:wrc, :wrs]) do
+  sv_rtl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+  end
+end

data/lib/rggen/systemverilog/rtl/feature.rb

@@ -6,43 +6,39 @@ module RgGen
       class Feature < Common::Feature
         private
 
-        def create_variable(data_type, attributes = {}, &block)
+        def create_variable(data_type, attributes, &block)
           DataObject.new(
             :variable, attributes.merge(data_type: data_type), &block
           )
         end
 
-        def create_interface(_, attributes = {}, &block)
+        def create_if_instance(_, attributes, &block)
           InterfaceInstance.new(attributes, &block)
         end
 
-        def create_argument(direction, attributes = {}, &block)
+        def create_argument(direction, attributes, &block)
           DataObject.new(
             :argument, attributes.merge(direction: direction), &block
           )
         end
 
-        def create_interface_port(_, attributes = {}, &block)
+        def create_if_port(_, attributes, &block)
           InterfacePort.new(attributes, &block)
         end
 
-        def create_parameter(parameter_type, attributes = {}, &block)
+        def create_parameter(parameter_type, attributes, &block)
           DataObject.new(
             :parameter, attributes.merge(parameter_type: parameter_type), &block
           )
         end
 
-        [
-          [:logic, :create_variable, :variable],
-          [:interface, :create_interface, :variable],
-          [:input, :create_argument, :port],
-          [:output, :create_argument, :port],
-          [:interface_port, :create_interface_port, :port],
-          [:parameter, :create_parameter, :parameter],
-          [:localparam, :create_parameter, :parameter]
-        ].each do |entity, creation_method, declaration_type|
-          define_entity(entity, creation_method, declaration_type)
-        end
+        define_entity :logic, :create_variable, :variable, -> { component }
+        define_entity :interface, :create_if_instance, :variable, -> { component }
+        define_entity :input, :create_argument, :port, -> { register_block }
+        define_entity :output, :create_argument, :port, -> { register_block }
+        define_entity :interface_port, :create_if_port, :port, -> { register_block }
+        define_entity :parameter, :create_parameter, :parameter, -> { register_block }
+        define_entity :localparam, :create_parameter, :parameter, -> { component }
       end
     end
   end

data/lib/rggen/systemverilog/rtl/partial_sum.rb

@@ -0,0 +1,29 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RTL
+      module PartialSum
+        private
+
+        def partial_sums(operands)
+          sums =
+            operands
+              .chunk(&method(:integer?))
+              .flat_map(&method(:calc_partial_sum))
+              .reject { |value| integer?(value) && value.zero? }
+          sums.empty? && [0] || sums
+        end
+
+        def calc_partial_sum(kind_ans_values)
+          kind, values = kind_ans_values
+          kind && values.sum || values
+        end
+
+        def integer?(value)
+          value.is_a?(Integer)
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb

@@ -2,18 +2,11 @@
 
 RgGen.define_simple_feature(:register, :sv_rtl_top) do
   sv_rtl do
-    export :index
-    export :local_index
-    export :loop_variables
-
-    pre_build do
-      @base_index =
-        register_block.registers.map(&:count).sum
-    end
+    include RgGen::SystemVerilog::RTL::RegisterIndex
 
     build do
-      if register.bit_fields?
-        interface :register, :bit_field_if, {
+      unless register.bit_fields.empty?
+        interface :bit_field_if, {
           name: 'bit_field_if',
           interface_type: 'rggen_bit_field_if',
           parameter_values: [register.width]
@@ -21,62 +14,32 @@ RgGen.define_simple_feature(:register, :sv_rtl_top) do
       end
     end
 
-    main_code :register_block do
+    main_code :register_file do
       local_scope("g_#{register.name}") do |scope|
-        scope.top_scope
+        scope.top_scope top_scope?
         scope.loop_size loop_size
         scope.variables variables
         scope.body(&method(:body_code))
       end
     end
 
-    def index(offset = nil)
-      operands =
-        register.array? ? [@base_index, offset || local_index] : [@base_index]
-      if operands.all? { |operand| operand.is_a?(Integer) }
-        operands.sum
-      else
-        operands.join('+')
-      end
-    end
-
-    def local_index
-      (register.array? || nil) &&
-        loop_variables
-          .zip(local_index_coefficients)
-          .map { |v, c| [c, v].compact.join('*') }
-          .join('+')
-    end
-
-    def loop_variables
-      (register.array? || nil) &&
-        register.array_size.map.with_index(1) do |_size, i|
-          create_identifier(loop_index(i))
-        end
-    end
-
     private
 
-    def local_index_coefficients
-      coefficients = []
-      register.array_size.reverse.inject(1) do |total, size|
-        coefficients.unshift(coefficients.size.zero? ? nil : total)
-        total * size
-      end
-      coefficients
+    def top_scope?
+      register_file.nil?
     end
 
     def loop_size
       (register.array? || nil) &&
-        loop_variables.zip(register.array_size).to_h
+        local_loop_variables.zip(register.array_size).to_h
     end
 
     def variables
-      register.declarations(:register, :variable)
+      register.declarations[:variable]
     end
 
     def body_code(code)
-      register.generate_code(:register, :top_down, code)
+      register.generate_code(code, :register, :top_down)
     end
   end
 end