rggen-systemverilog 0.18.0 → 0.22.0
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- checksums.yaml +4 -4
- data/LICENSE +1 -1
- data/README.md +2 -2
- data/lib/rggen/systemverilog/common.rb +2 -2
- data/lib/rggen/systemverilog/common/component.rb +2 -6
- data/lib/rggen/systemverilog/common/feature.rb +39 -26
- data/lib/rggen/systemverilog/common/utility.rb +6 -2
- data/lib/rggen/systemverilog/common/utility/data_object.rb +2 -2
- data/lib/rggen/systemverilog/common/utility/interface_instance.rb +2 -2
- data/lib/rggen/systemverilog/common/utility/interface_port.rb +9 -5
- data/lib/rggen/systemverilog/common/utility/local_scope.rb +2 -2
- data/lib/rggen/systemverilog/common/utility/structure_definition.rb +3 -5
- data/lib/rggen/systemverilog/ral.rb +6 -1
- data/lib/rggen/systemverilog/ral/bit_field/type.rb +15 -10
- data/lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb +1 -11
- data/lib/rggen/systemverilog/ral/feature.rb +5 -7
- data/lib/rggen/systemverilog/ral/register/type.rb +10 -52
- data/lib/rggen/systemverilog/ral/register/type/default.erb +1 -1
- data/lib/rggen/systemverilog/ral/register/type/external.rb +6 -10
- data/lib/rggen/systemverilog/ral/register/type/indirect.erb +3 -3
- data/lib/rggen/systemverilog/ral/register/type/indirect.rb +5 -2
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.erb +8 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.rb +36 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb +1 -32
- data/lib/rggen/systemverilog/ral/register_common.rb +46 -0
- data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.erb +8 -0
- data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb +57 -0
- data/lib/rggen/systemverilog/ral/setup.rb +3 -2
- data/lib/rggen/systemverilog/rtl.rb +7 -1
- data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +34 -19
- data/lib/rggen/systemverilog/rtl/bit_field/type.rb +1 -5
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb +10 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb +20 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb +1 -1
- data/lib/rggen/systemverilog/rtl/feature.rb +12 -16
- data/lib/rggen/systemverilog/rtl/partial_sum.rb +29 -0
- data/lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb +10 -47
- data/lib/rggen/systemverilog/rtl/register/type.rb +25 -1
- data/lib/rggen/systemverilog/rtl/register/type/external.rb +15 -15
- data/lib/rggen/systemverilog/rtl/register/type/indirect.rb +3 -3
- data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +17 -7
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb +9 -5
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb +14 -15
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb +11 -6
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +53 -30
- data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +11 -13
- data/lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb +30 -0
- data/lib/rggen/systemverilog/rtl/register_index.rb +112 -0
- data/lib/rggen/systemverilog/rtl/setup.rb +2 -1
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +16 -7
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_block_model.erb +0 -11
@@ -2,12 +2,13 @@
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2
2
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3
3
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require 'rggen/systemverilog/rtl'
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4
4
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5
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-
RgGen.setup
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5
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+
RgGen.setup RgGen::SystemVerilog::RTL do |builder|
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6
6
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builder.enable :global, [
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7
7
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:array_port_format, :fold_sv_interface_port
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8
8
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]
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9
9
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builder.enable :register_block, [:sv_rtl_top, :protocol]
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10
10
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builder.enable :register_block, :protocol, [:apb, :axi4lite]
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11
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+
builder.enable :register_file, [:sv_rtl_top]
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11
12
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builder.enable :register, [:sv_rtl_top]
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12
13
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builder.enable :bit_field, [:sv_rtl_top]
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end
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metadata
CHANGED
@@ -1,14 +1,14 @@
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1
1
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--- !ruby/object:Gem::Specification
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name: rggen-systemverilog
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3
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version: !ruby/object:Gem::Version
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-
version: 0.
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4
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+
version: 0.22.0
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5
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platform: ruby
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6
6
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authors:
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7
7
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- Taichi Ishitani
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8
8
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autorequire:
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9
9
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bindir: bin
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10
10
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cert_chain: []
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11
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-
date:
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11
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+
date: 2020-08-17 00:00:00.000000000 Z
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12
12
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dependencies:
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13
13
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- !ruby/object:Gem::Dependency
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14
14
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name: docile
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@@ -54,7 +54,7 @@ dependencies:
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54
54
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version: '0'
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55
55
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description: 'SystemVerilog RTL and UVM RAL model generators for RgGen.
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56
56
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|
57
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-
'
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57
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+
'
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58
58
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email:
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59
59
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- rggen@googlegroups.com
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60
60
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executables: []
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@@ -93,8 +93,12 @@ files:
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93
93
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- lib/rggen/systemverilog/ral/register/type/external.rb
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94
94
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- lib/rggen/systemverilog/ral/register/type/indirect.erb
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95
95
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- lib/rggen/systemverilog/ral/register/type/indirect.rb
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96
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-
- lib/rggen/systemverilog/ral/register_block/
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96
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+
- lib/rggen/systemverilog/ral/register_block/sv_ral_model.erb
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97
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+
- lib/rggen/systemverilog/ral/register_block/sv_ral_model.rb
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97
98
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- lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb
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99
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+
- lib/rggen/systemverilog/ral/register_common.rb
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100
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+
- lib/rggen/systemverilog/ral/register_file/sv_ral_model.erb
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101
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+
- lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb
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98
102
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- lib/rggen/systemverilog/ral/setup.rb
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99
103
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- lib/rggen/systemverilog/rtl.rb
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100
104
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- lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb
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@@ -123,11 +127,14 @@ files:
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123
127
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- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb
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124
128
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- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.erb
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125
129
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- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb
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130
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+
- lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb
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131
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+
- lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb
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126
132
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- lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb
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127
133
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- lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb
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128
134
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- lib/rggen/systemverilog/rtl/feature.rb
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129
135
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- lib/rggen/systemverilog/rtl/global/array_port_format.rb
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130
136
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- lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb
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137
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+
- lib/rggen/systemverilog/rtl/partial_sum.rb
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131
138
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- lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb
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132
139
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- lib/rggen/systemverilog/rtl/register/type.rb
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133
140
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- lib/rggen/systemverilog/rtl/register/type/default.erb
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@@ -142,6 +149,8 @@ files:
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142
149
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- lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb
|
143
150
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- lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb
|
144
151
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- lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb
|
152
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+
- lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb
|
153
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+
- lib/rggen/systemverilog/rtl/register_index.rb
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145
154
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- lib/rggen/systemverilog/rtl/setup.rb
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146
155
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- lib/rggen/systemverilog/version.rb
|
147
156
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homepage: https://github.com/rggen/rggen-systemverilog
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@@ -160,15 +169,15 @@ required_ruby_version: !ruby/object:Gem::Requirement
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160
169
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requirements:
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161
170
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- - ">="
|
162
171
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- !ruby/object:Gem::Version
|
163
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-
version: '2.
|
172
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+
version: '2.4'
|
164
173
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required_rubygems_version: !ruby/object:Gem::Requirement
|
165
174
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requirements:
|
166
175
|
- - ">="
|
167
176
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- !ruby/object:Gem::Version
|
168
177
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version: '0'
|
169
178
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requirements: []
|
170
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-
rubygems_version: 3.
|
179
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+
rubygems_version: 3.1.2
|
171
180
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signing_key:
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172
181
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specification_version: 4
|
173
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-
summary: rggen-systemverilog-0.
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182
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+
summary: rggen-systemverilog-0.22.0
|
174
183
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test_files: []
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@@ -1,11 +0,0 @@
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1
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-
function new(string name);
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2
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super.new(name);
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3
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-
endfunction
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4
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-
function void build();
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5
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<% reg_model_constructors.each do |constructor| %>
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6
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-
<%= constructor %>
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7
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<% end %>
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-
endfunction
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9
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-
function uvm_reg_map create_default_map();
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10
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-
return create_map("default_map", 0, <%= byte_width %>, UVM_LITTLE_ENDIAN, 1);
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11
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-
endfunction
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