rggen-systemverilog 0.18.0 → 0.22.0
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- checksums.yaml +4 -4
- data/LICENSE +1 -1
- data/README.md +2 -2
- data/lib/rggen/systemverilog/common.rb +2 -2
- data/lib/rggen/systemverilog/common/component.rb +2 -6
- data/lib/rggen/systemverilog/common/feature.rb +39 -26
- data/lib/rggen/systemverilog/common/utility.rb +6 -2
- data/lib/rggen/systemverilog/common/utility/data_object.rb +2 -2
- data/lib/rggen/systemverilog/common/utility/interface_instance.rb +2 -2
- data/lib/rggen/systemverilog/common/utility/interface_port.rb +9 -5
- data/lib/rggen/systemverilog/common/utility/local_scope.rb +2 -2
- data/lib/rggen/systemverilog/common/utility/structure_definition.rb +3 -5
- data/lib/rggen/systemverilog/ral.rb +6 -1
- data/lib/rggen/systemverilog/ral/bit_field/type.rb +15 -10
- data/lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb +1 -11
- data/lib/rggen/systemverilog/ral/feature.rb +5 -7
- data/lib/rggen/systemverilog/ral/register/type.rb +10 -52
- data/lib/rggen/systemverilog/ral/register/type/default.erb +1 -1
- data/lib/rggen/systemverilog/ral/register/type/external.rb +6 -10
- data/lib/rggen/systemverilog/ral/register/type/indirect.erb +3 -3
- data/lib/rggen/systemverilog/ral/register/type/indirect.rb +5 -2
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.erb +8 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.rb +36 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb +1 -32
- data/lib/rggen/systemverilog/ral/register_common.rb +46 -0
- data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.erb +8 -0
- data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb +57 -0
- data/lib/rggen/systemverilog/ral/setup.rb +3 -2
- data/lib/rggen/systemverilog/rtl.rb +7 -1
- data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +34 -19
- data/lib/rggen/systemverilog/rtl/bit_field/type.rb +1 -5
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb +10 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb +20 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb +1 -1
- data/lib/rggen/systemverilog/rtl/feature.rb +12 -16
- data/lib/rggen/systemverilog/rtl/partial_sum.rb +29 -0
- data/lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb +10 -47
- data/lib/rggen/systemverilog/rtl/register/type.rb +25 -1
- data/lib/rggen/systemverilog/rtl/register/type/external.rb +15 -15
- data/lib/rggen/systemverilog/rtl/register/type/indirect.rb +3 -3
- data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +17 -7
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb +9 -5
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb +14 -15
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb +11 -6
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +53 -30
- data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +11 -13
- data/lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb +30 -0
- data/lib/rggen/systemverilog/rtl/register_index.rb +112 -0
- data/lib/rggen/systemverilog/rtl/setup.rb +2 -1
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +16 -7
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_block_model.erb +0 -11
@@ -3,7 +3,7 @@
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3
3
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RgGen.define_list_item_feature(:register, :type, :indirect) do
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4
4
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sv_rtl do
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5
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build do
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-
logic :
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+
logic :indirect_index, { width: index_width }
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7
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end
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8
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main_code :register do |code|
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@@ -19,11 +19,11 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
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end
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def index_width
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-
@index_width ||= index_fields.map(&:width).
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+
@index_width ||= index_fields.map(&:width).sum
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end
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def index_values
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-
loop_variables = register.
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+
loop_variables = register.local_loop_variables
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register.index_entries.zip(index_fields).map do |entry, field|
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if entry.array_index?
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loop_variables.shift[0, field.width]
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@@ -65,21 +65,27 @@ RgGen.define_list_feature(:register_block, :protocol) do
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base_feature do
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build do
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-
parameter :
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+
parameter :address_width, {
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name: 'ADDRESS_WIDTH', data_type: :int, default: local_address_width
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+
}
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parameter :pre_decode, {
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name: 'PRE_DECODE', data_type: :bit, width: 1, default: 0
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}
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parameter :base_address, {
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name: 'BASE_ADDRESS', data_type: :bit, width: address_width,
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default: all_bits_0
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}
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parameter :error_status, {
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name: 'ERROR_STATUS', data_type: :bit, width: 1, default: 0
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}
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-
parameter :
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+
parameter :default_read_data, {
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name: 'DEFAULT_READ_DATA', data_type: :bit, width: bus_width,
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-
default:
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+
default: all_bits_0
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}
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end
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private
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-
def address_width
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configuration.address_width
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-
end
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-
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def bus_width
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configuration.bus_width
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end
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@@ -96,6 +102,10 @@ RgGen.define_list_feature(:register_block, :protocol) do
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register_block.total_registers
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end
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+
def byte_size
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register_block.byte_size
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+
end
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+
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def clock
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register_block.clock
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end
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@@ -1,9 +1,13 @@
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rggen_apb_adapter #(
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-
.ADDRESS_WIDTH
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-
.
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-
.
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-
.
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-
.
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.ADDRESS_WIDTH (<%= address_width %>),
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.LOCAL_ADDRESS_WIDTH (<%= local_address_width %>),
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.BUS_WIDTH (<%= bus_width %>),
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.REGISTERS (<%= total_registers %>),
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.PRE_DECODE (<%= pre_decode %>),
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.BASE_ADDRESS (<%= base_address %>),
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+
.BYTE_SIZE (<%= byte_size %>),
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+
.ERROR_STATUS (<%= error_status %>),
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+
.DEFAULT_READ_DATA (<%= default_read_data %>)
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) u_adapter (
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.i_clk (<%= clock %>),
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.i_rst_n (<%= reset %>),
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@@ -22,42 +22,41 @@ RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
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sv_rtl do
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build do
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if configuration.fold_sv_interface_port?
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-
interface_port :
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+
interface_port :apb_if, {
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name: 'apb_if', interface_type: 'rggen_apb_if', modport: 'slave'
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}
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else
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-
input :
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+
input :psel, {
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name: 'i_psel', data_type: :logic, width: 1
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}
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-
input :
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+
input :penable, {
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name: 'i_penable', data_type: :logic, width: 1
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}
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-
input :
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+
input :paddr, {
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name: 'i_paddr', data_type: :logic, width: address_width
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}
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-
input :
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+
input :pprot, {
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name: 'i_pprot', data_type: :logic, width: 3
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}
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-
input :
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+
input :pwrite, {
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name: 'i_pwrite', data_type: :logic, width: 1
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}
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-
input :
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-
name: 'i_pstrb', data_type: :logic,
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-
width: byte_width
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+
input :pstrb, {
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+
name: 'i_pstrb', data_type: :logic, width: byte_width
|
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}
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-
input :
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47
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+
input :pwdata, {
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name: 'i_pwdata', data_type: :logic, width: bus_width
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}
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-
output :
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+
output :pready, {
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name: 'o_pready', data_type: :logic, width: 1
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53
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}
|
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-
output :
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53
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+
output :prdata, {
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55
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name: 'o_prdata', data_type: :logic, width: bus_width
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}
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-
output :
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+
output :pslverr, {
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name: 'o_pslverr', data_type: :logic, width: 1
|
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}
|
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-
interface :
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+
interface :apb_if, {
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name: 'apb_if', interface_type: 'rggen_apb_if',
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parameter_values: [address_width, bus_width],
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variables: [
|
@@ -82,7 +81,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
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[pready, apb_if.pready],
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[prdata, apb_if.prdata],
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[pslverr, apb_if.pslverr]
|
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-
].
|
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+
].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
|
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end
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end
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end
|
@@ -1,10 +1,15 @@
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1
1
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rggen_axi4lite_adapter #(
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-
.
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3
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-
.
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-
.
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5
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-
.
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-
.
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-
.
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2
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+
.ID_WIDTH (<%= id_width %>),
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3
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+
.ADDRESS_WIDTH (<%= address_width %>),
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4
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+
.LOCAL_ADDRESS_WIDTH (<%= local_address_width %>),
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5
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+
.BUS_WIDTH (<%= bus_width %>),
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6
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+
.REGISTERS (<%= total_registers %>),
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7
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+
.PRE_DECODE (<%= pre_decode %>),
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8
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+
.BASE_ADDRESS (<%= base_address %>),
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9
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+
.BYTE_SIZE (<%= byte_size %>),
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10
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+
.ERROR_STATUS (<%= error_status %>),
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11
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+
.DEFAULT_READ_DATA (<%= default_read_data %>),
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+
.WRITE_FIRST (<%= write_first %>)
|
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13
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) u_adapter (
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14
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.i_clk (<%= clock %>),
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15
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.i_rst_n (<%= reset %>),
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@@ -13,83 +13,96 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
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sv_rtl do
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build do
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-
parameter :
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-
name: '
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-
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-
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+
parameter :id_width, {
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name: 'ID_WIDTH', data_type: :int, default: 0
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}
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parameter :write_first, {
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name: 'WRITE_FIRST', data_type: :bit, default: 1
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}
|
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22
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if configuration.fold_sv_interface_port?
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-
interface_port :
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+
interface_port :axi4lite_if, {
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name: 'axi4lite_if',
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interface_type: 'rggen_axi4lite_if', modport: 'slave'
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}
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else
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-
input :
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+
input :awvalid, {
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name: 'i_awvalid', data_type: :logic, width: 1
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}
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-
output :
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output :awready, {
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name: 'o_awready', data_type: :logic, width: 1
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}
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-
input :
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input :awid, {
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name: 'i_awid', data_type: :logic, width: id_port_width
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}
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input :awaddr, {
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name: 'i_awaddr', data_type: :logic, width: address_width
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}
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input :
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+
input :awprot, {
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name: 'i_awprot', data_type: :logic, width: 3
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}
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-
input :
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input :wvalid, {
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name: 'i_wvalid', data_type: :logic, width: 1
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}
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output :
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output :wready, {
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name: 'o_wready', data_type: :logic, width: 1
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}
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input :
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+
input :wdata, {
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name: 'i_wdata', data_type: :logic, width: bus_width
|
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}
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input :
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input :wstrb, {
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name: 'i_wstrb', data_type: :logic, width: byte_width
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}
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output :
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output :bvalid, {
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name: 'o_bvalid', data_type: :logic, width: 1
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}
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-
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+
output :bid, {
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name: 'o_bid', data_type: :logic, width: id_port_width
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}
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input :bready, {
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name: 'i_bready', data_type: :logic, width: 1
|
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}
|
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-
output :
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+
output :bresp, {
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name: 'o_bresp', data_type: :logic, width: 2
|
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}
|
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-
input :
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+
input :arvalid, {
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name: 'i_arvalid', data_type: :logic, width: 1
|
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}
|
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-
output :
|
70
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+
output :arready, {
|
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name: 'o_arready', data_type: :logic, width: 1
|
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}
|
66
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-
input :
|
73
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+
input :arid, {
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+
name: 'i_arid', data_type: :logic, width: id_port_width
|
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+
}
|
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+
input :araddr, {
|
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name: 'i_araddr', data_type: :logic, width: address_width
|
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}
|
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-
input :
|
79
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+
input :arprot, {
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name: 'i_arprot', data_type: :logic, width: 3
|
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}
|
72
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-
output :
|
82
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+
output :rvalid, {
|
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name: 'o_rvalid', data_type: :logic, width: 1
|
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}
|
75
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input :
|
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+
input :rready, {
|
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name: 'i_rready', data_type: :logic, width: 1
|
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}
|
78
|
-
output :
|
88
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+
output :rid, {
|
89
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+
name: 'o_rid', data_type: :logic, width: id_port_width
|
90
|
+
}
|
91
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+
output :rdata, {
|
79
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|
name: 'o_rdata', data_type: :logic, width: bus_width
|
80
93
|
}
|
81
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-
output :
|
94
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+
output :rresp, {
|
82
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|
name: 'o_rresp', data_type: :logic, width: 2
|
83
96
|
}
|
84
|
-
interface :
|
97
|
+
interface :axi4lite_if, {
|
85
98
|
name: 'axi4lite_if', interface_type: 'rggen_axi4lite_if',
|
86
|
-
parameter_values: [address_width, bus_width],
|
99
|
+
parameter_values: [id_width, address_width, bus_width],
|
87
100
|
variables: [
|
88
|
-
'awvalid', 'awready', 'awaddr', 'awprot',
|
101
|
+
'awvalid', 'awready', 'awid', 'awaddr', 'awprot',
|
89
102
|
'wvalid', 'wready', 'wdata', 'wstrb',
|
90
|
-
'bvalid', 'bready', 'bresp',
|
91
|
-
'arvalid', 'arready', 'araddr', 'arprot',
|
92
|
-
'rvalid', 'rready', 'rdata', 'rresp'
|
103
|
+
'bvalid', 'bready', 'bid', 'bresp',
|
104
|
+
'arvalid', 'arready', 'arid', 'araddr', 'arprot',
|
105
|
+
'rvalid', 'rready', 'rid', 'rdata', 'rresp'
|
93
106
|
]
|
94
107
|
}
|
95
108
|
end
|
@@ -101,6 +114,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
|
|
101
114
|
[
|
102
115
|
[axi4lite_if.awvalid, awvalid],
|
103
116
|
[awready, axi4lite_if.awready],
|
117
|
+
[axi4lite_if.awid, awid],
|
104
118
|
[axi4lite_if.awaddr, awaddr],
|
105
119
|
[axi4lite_if.awprot, awprot],
|
106
120
|
[axi4lite_if.wvalid, wvalid],
|
@@ -109,17 +123,26 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
|
|
109
123
|
[axi4lite_if.wstrb, wstrb],
|
110
124
|
[bvalid, axi4lite_if.bvalid],
|
111
125
|
[axi4lite_if.bready, bready],
|
126
|
+
[bid, axi4lite_if.bid],
|
112
127
|
[bresp, axi4lite_if.bresp],
|
113
128
|
[axi4lite_if.arvalid, arvalid],
|
114
129
|
[arready, axi4lite_if.arready],
|
130
|
+
[axi4lite_if.arid, arid],
|
115
131
|
[axi4lite_if.araddr, araddr],
|
116
132
|
[axi4lite_if.arprot, arprot],
|
117
133
|
[rvalid, axi4lite_if.rvalid],
|
118
134
|
[axi4lite_if.rready, rready],
|
135
|
+
[rid, axi4lite_if.rid],
|
119
136
|
[rdata, axi4lite_if.rdata],
|
120
137
|
[rresp, axi4lite_if.rresp]
|
121
138
|
].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
|
122
139
|
end
|
123
140
|
end
|
141
|
+
|
142
|
+
private
|
143
|
+
|
144
|
+
def id_port_width
|
145
|
+
"((#{id_width}>0)?#{id_width}:1)"
|
146
|
+
end
|
124
147
|
end
|
125
148
|
end
|
@@ -5,17 +5,16 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
|
|
5
5
|
export :total_registers
|
6
6
|
|
7
7
|
build do
|
8
|
-
input :
|
8
|
+
input :clock, {
|
9
9
|
name: 'i_clk', data_type: :logic, width: 1
|
10
10
|
}
|
11
|
-
input :
|
11
|
+
input :reset, {
|
12
12
|
name: 'i_rst_n', data_type: :logic, width: 1
|
13
13
|
}
|
14
|
-
interface :
|
14
|
+
interface :register_if, {
|
15
15
|
name: 'register_if', interface_type: 'rggen_register_if',
|
16
16
|
parameter_values: [address_width, bus_width, value_width],
|
17
|
-
array_size: [total_registers],
|
18
|
-
variables: ['value']
|
17
|
+
array_size: [total_registers], variables: ['value']
|
19
18
|
}
|
20
19
|
end
|
21
20
|
|
@@ -24,10 +23,7 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
|
|
24
23
|
end
|
25
24
|
|
26
25
|
def total_registers
|
27
|
-
register_block
|
28
|
-
.registers
|
29
|
-
.map(&:count)
|
30
|
-
.inject(:+)
|
26
|
+
register_block.files_and_registers.map(&:count).sum
|
31
27
|
end
|
32
28
|
|
33
29
|
private
|
@@ -68,19 +64,21 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
|
|
68
64
|
end
|
69
65
|
|
70
66
|
def parameters
|
71
|
-
register_block.declarations
|
67
|
+
register_block.declarations[:parameter]
|
72
68
|
end
|
73
69
|
|
74
70
|
def ports
|
75
|
-
register_block.declarations
|
71
|
+
register_block.declarations[:port]
|
76
72
|
end
|
77
73
|
|
78
74
|
def variables
|
79
|
-
register_block.declarations
|
75
|
+
register_block.declarations[:variable]
|
80
76
|
end
|
81
77
|
|
82
78
|
def sv_module_body(code)
|
83
|
-
register_block
|
79
|
+
{ register_block: nil, register_file: 1 }.each do |kind, depth|
|
80
|
+
register_block.generate_code(code, kind, :top_down, depth)
|
81
|
+
end
|
84
82
|
end
|
85
83
|
end
|
86
84
|
end
|
@@ -0,0 +1,30 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
RgGen.define_simple_feature(:register_file, :sv_rtl_top) do
|
4
|
+
sv_rtl do
|
5
|
+
include RgGen::SystemVerilog::RTL::RegisterIndex
|
6
|
+
|
7
|
+
main_code :register_file do
|
8
|
+
local_scope("g_#{register_file.name}") do |scope|
|
9
|
+
scope.top_scope top_scope?
|
10
|
+
scope.loop_size loop_size
|
11
|
+
scope.body(&method(:body_code))
|
12
|
+
end
|
13
|
+
end
|
14
|
+
|
15
|
+
private
|
16
|
+
|
17
|
+
def top_scope?
|
18
|
+
register_file(:upper).nil?
|
19
|
+
end
|
20
|
+
|
21
|
+
def loop_size
|
22
|
+
(register_file.array? || nil) &&
|
23
|
+
local_loop_variables.zip(register_file.array_size).to_h
|
24
|
+
end
|
25
|
+
|
26
|
+
def body_code(code)
|
27
|
+
register_file.generate_code(code, :register_file, :top_down, 1)
|
28
|
+
end
|
29
|
+
end
|
30
|
+
end
|
@@ -0,0 +1,112 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
module RgGen
|
4
|
+
module SystemVerilog
|
5
|
+
module RTL
|
6
|
+
module RegisterIndex
|
7
|
+
include PartialSum
|
8
|
+
|
9
|
+
EXPORTED_METHODS = [
|
10
|
+
:loop_variables, :local_loop_variables,
|
11
|
+
:local_index, :local_indices,
|
12
|
+
:index, :inside_roop?
|
13
|
+
].freeze
|
14
|
+
|
15
|
+
def self.included(feature)
|
16
|
+
feature.module_eval do
|
17
|
+
EXPORTED_METHODS.each { |m| export m }
|
18
|
+
|
19
|
+
pre_build do
|
20
|
+
@base_index = files_and_registers.sum(&:count)
|
21
|
+
end
|
22
|
+
end
|
23
|
+
end
|
24
|
+
|
25
|
+
def loop_variables
|
26
|
+
(inside_roop? || nil) &&
|
27
|
+
[*upper_register_file&.loop_variables, *local_loop_variables]
|
28
|
+
end
|
29
|
+
|
30
|
+
def local_loop_variables
|
31
|
+
(component.array? || nil) &&
|
32
|
+
begin
|
33
|
+
start_depth = (upper_register_file&.loop_variables&.size || 0) + 1
|
34
|
+
Array.new(component.array_size.size) do |i|
|
35
|
+
create_identifier(loop_index(i + start_depth))
|
36
|
+
end
|
37
|
+
end
|
38
|
+
end
|
39
|
+
|
40
|
+
def local_index
|
41
|
+
(component.array? || nil) &&
|
42
|
+
local_index_coefficients
|
43
|
+
.zip(local_loop_variables)
|
44
|
+
.map { |operands| product(operands, false) }
|
45
|
+
.join('+')
|
46
|
+
end
|
47
|
+
|
48
|
+
def local_indices
|
49
|
+
[*upper_register_file&.local_indices, local_index]
|
50
|
+
end
|
51
|
+
|
52
|
+
def index(offset_or_offsets = nil)
|
53
|
+
operands = index_operands(offset_or_offsets)
|
54
|
+
partial_indices = partial_sums(operands)
|
55
|
+
if partial_indices.empty? || partial_indices.all?(&method(:integer?))
|
56
|
+
partial_indices.sum
|
57
|
+
else
|
58
|
+
partial_indices.join('+')
|
59
|
+
end
|
60
|
+
end
|
61
|
+
|
62
|
+
def inside_roop?
|
63
|
+
component.array? || upper_register_file&.inside_roop? || false
|
64
|
+
end
|
65
|
+
|
66
|
+
private
|
67
|
+
|
68
|
+
def upper_register_file
|
69
|
+
component.register_file
|
70
|
+
end
|
71
|
+
|
72
|
+
def local_index_coefficients
|
73
|
+
coefficients = []
|
74
|
+
component.array_size.reverse.inject(1) do |total, size|
|
75
|
+
coefficients.unshift(total)
|
76
|
+
total * size
|
77
|
+
end
|
78
|
+
coefficients
|
79
|
+
end
|
80
|
+
|
81
|
+
def index_operands(offset_or_offsets)
|
82
|
+
offsets = offset_or_offsets && Array(offset_or_offsets)
|
83
|
+
[
|
84
|
+
*upper_register_file&.index(offsets&.slice(0..-2)),
|
85
|
+
@base_index,
|
86
|
+
*local_register_index(offsets&.slice(-1))
|
87
|
+
]
|
88
|
+
end
|
89
|
+
|
90
|
+
def local_register_index(offset)
|
91
|
+
(component.array? || nil) &&
|
92
|
+
begin
|
93
|
+
operands = [component.count(false), offset || local_index]
|
94
|
+
product(operands, true)
|
95
|
+
end
|
96
|
+
end
|
97
|
+
|
98
|
+
def product(operands, need_bracket)
|
99
|
+
if operands.all?(&method(:integer?))
|
100
|
+
operands.reduce(:*)
|
101
|
+
elsif operands.first == 1
|
102
|
+
operands.last
|
103
|
+
elsif need_bracket
|
104
|
+
"#{operands.first}*(#{operands.last})"
|
105
|
+
else
|
106
|
+
operands.join('*')
|
107
|
+
end
|
108
|
+
end
|
109
|
+
end
|
110
|
+
end
|
111
|
+
end
|
112
|
+
end
|