rggen-systemverilog 0.18.0 → 0.19.0

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
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data/LICENSE CHANGED
@@ -1,6 +1,6 @@
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  The MIT License (MIT)
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- Copyright (c) 2019 Taichi Ishitani
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+ Copyright (c) 2019-2020 Taichi Ishitani
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  Permission is hereby granted, free of charge, to any person obtaining a copy
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  of this software and associated documentation files (the "Software"), to deal
data/README.md CHANGED
@@ -1,5 +1,5 @@
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  [![Gem Version](https://badge.fury.io/rb/rggen-systemverilog.svg)](https://badge.fury.io/rb/rggen-systemverilog)
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- [![Build Status](https://travis-ci.com/rggen/rggen-systemverilog.svg?branch=master)](https://travis-ci.com/rggen/rggen-systemverilog)
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+ [![CI](https://github.com/rggen/rggen-systemverilog/workflows/CI/badge.svg)](https://github.com/rggen/rggen-systemverilog/actions?query=workflow%3ACI)
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  [![Maintainability](https://api.codeclimate.com/v1/badges/88086c5be538a1564a35/maintainability)](https://codeclimate.com/github/rggen/rggen-systemverilog/maintainability)
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  [![codecov](https://codecov.io/gh/rggen/rggen-systemverilog/branch/master/graph/badge.svg)](https://codecov.io/gh/rggen/rggen-systemverilog)
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  [![Quality Gate Status](https://sonarcloud.io/api/project_badges/measure?project=rggen_rggen-systemverilog&metric=alert_status)](https://sonarcloud.io/dashboard?id=rggen_rggen-systemverilog)
@@ -34,7 +34,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
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  ## Copyright & License
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- Copyright © 2019 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
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+ Copyright © 2019-2020 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
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  ## Code of Conduct
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@@ -16,9 +16,9 @@ module RgGen
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  def define_entity(entity_type, creation_method, declaration_type)
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  context =
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  EntityContext.new(entity_type, creation_method, declaration_type)
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- define_method(entity_type) do |domain, name, **attributes, &block|
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+ define_method(entity_type) do |domain, name, attributes = {}, &block|
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  entity =
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- create_entity(context, { name: name }.merge(attributes), block)
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+ create_entity(context, { name: name }.merge(attributes), &block)
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  add_entity(entity, context, domain, name)
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  end
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  end
@@ -42,10 +42,10 @@ module RgGen
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  @package_imports = Hash.new { |h, k| h[k] = [] }
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  end
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- def create_entity(context, attributes, block)
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+ def create_entity(context, attributes, &block)
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  creation_method = context.creation_method
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  entity_type = context.entity_type
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- __send__(creation_method, entity_type, attributes, block)
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+ __send__(creation_method, entity_type, attributes, &block)
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  end
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  def add_entity(entity, context, domain, name)
@@ -79,7 +79,7 @@ module RgGen
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  [width, bit_length].max
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  end
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- def argument(name, **attribute)
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+ def argument(name, attribute = {})
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  DataObject.new(:argument, attribute.merge(name: name)).declaration
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  end
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@@ -90,7 +90,7 @@ module RgGen
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  module_definition: ModuleDefinition,
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  package_definition: PackageDefinition
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  }.each do |method_name, definition|
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- define_method(method_name) do |name, **attributes, &block|
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+ define_method(method_name) do |name, attributes = {}, &block|
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  definition.new(attributes.merge(name: name), &block).to_code
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  end
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  end
@@ -7,9 +7,9 @@ module RgGen
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  class DataObject
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  include Core::Utility::AttributeSetter
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- def initialize(object_type, **default_attributes)
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+ def initialize(object_type, default_attributes = {})
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  @object_type = object_type
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- apply_attributes(default_attributes)
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+ apply_attributes(**default_attributes)
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  block_given? && yield(self)
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  end
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@@ -7,8 +7,8 @@ module RgGen
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  class InterfaceInstance
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  include Core::Utility::AttributeSetter
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- def initialize(**default_attributes)
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- apply_attributes(default_attributes)
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+ def initialize(default_attributes = {})
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+ apply_attributes(**default_attributes)
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  block_given? && yield(self)
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  end
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@@ -7,8 +7,8 @@ module RgGen
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  class InterfacePort
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  include Core::Utility::AttributeSetter
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- def initialize(**default_attributes)
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- apply_attributes(default_attributes)
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+ def initialize(default_attributes = {})
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+ apply_attributes(**default_attributes)
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  block_given? && yield(self)
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  end
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@@ -9,8 +9,8 @@ module RgGen
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  include Core::Utility::AttributeSetter
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- def initialize(**default_attributes, &block)
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- apply_attributes(default_attributes)
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+ def initialize(default_attributes = {}, &block)
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+ apply_attributes(**default_attributes)
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  super(&block)
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  end
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@@ -6,16 +6,14 @@ module RgGen
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  class Feature < Common::Feature
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  private
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- def create_variable(_, attributes, block)
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+ def create_variable(_, attributes = {}, &block)
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  DataObject.new(
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  :variable, attributes.merge(array_format: :unpacked), &block
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  )
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  end
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- def create_parameter(_, attributes, block)
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- DataObject.new(
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- :parameter, attributes, &block
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- )
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+ def create_parameter(_, attributes = {}, &block)
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+ DataObject.new(:parameter, attributes, &block)
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  end
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  define_entity :variable, :create_variable, :variable
@@ -6,27 +6,27 @@ module RgGen
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  class Feature < Common::Feature
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  private
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- def create_variable(data_type, attributes, block)
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+ def create_variable(data_type, attributes = {}, &block)
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  DataObject.new(
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  :variable, attributes.merge(data_type: data_type), &block
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  )
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  end
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- def create_interface(_, attributes, block)
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+ def create_interface(_, attributes = {}, &block)
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  InterfaceInstance.new(attributes, &block)
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  end
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- def create_argument(direction, attributes, block)
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+ def create_argument(direction, attributes = {}, &block)
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  DataObject.new(
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  :argument, attributes.merge(direction: direction), &block
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  )
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  end
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- def create_interface_port(_, attributes, block)
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+ def create_interface_port(_, attributes = {}, &block)
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  InterfacePort.new(attributes, &block)
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  end
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- def create_parameter(parameter_type, attributes, block)
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+ def create_parameter(parameter_type, attributes = {}, &block)
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  DataObject.new(
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  :parameter, attributes.merge(parameter_type: parameter_type), &block
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  )
@@ -8,7 +8,7 @@ RgGen.define_simple_feature(:register, :sv_rtl_top) do
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  pre_build do
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  @base_index =
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- register_block.registers.map(&:count).inject(0, :+)
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+ register_block.registers.map(&:count).sum
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  end
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  build do
@@ -34,7 +34,7 @@ RgGen.define_simple_feature(:register, :sv_rtl_top) do
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  operands =
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  register.array? ? [@base_index, offset || local_index] : [@base_index]
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  if operands.all? { |operand| operand.is_a?(Integer) }
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- operands.inject(:+)
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+ operands.sum
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  else
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  operands.join('+')
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  end
@@ -14,14 +14,14 @@ RgGen.define_list_item_feature(:register, :type, :external) do
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  name: "o_#{register.name}_valid",
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  data_type: :logic, width: 1
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  }
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+ output :register_block, :access, {
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+ name: "o_#{register.name}_access",
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+ data_type: :logic, width: '$bits(rggen_access)'
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+ }
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  output :register_block, :address, {
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  name: "o_#{register.name}_address",
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  data_type: :logic, width: address_width
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  }
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- output :register_block, :write, {
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- name: "o_#{register.name}_write",
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- data_type: :logic, width: 1
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- }
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  output :register_block, :write_data, {
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  name: "o_#{register.name}_data",
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  data_type: :logic, width: bus_width
@@ -46,7 +46,7 @@ RgGen.define_list_item_feature(:register, :type, :external) do
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  name: 'bus_if', interface_type: 'rggen_bus_if',
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  parameter_values: [address_width, bus_width],
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  variables: [
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- 'valid', 'address', 'write', 'write_data', 'strobe',
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+ 'valid', 'access', 'address', 'write_data', 'strobe',
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  'ready', 'status', 'read_data'
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  ]
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  }
@@ -58,8 +58,8 @@ RgGen.define_list_item_feature(:register, :type, :external) do
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  unless configuration.fold_sv_interface_port?
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  [
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  [valid, bus_if.valid],
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+ [access, bus_if.access],
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  [address, bus_if.address],
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- [write, bus_if.write],
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  [write_data, bus_if.write_data],
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  [strobe, bus_if.strobe],
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  [bus_if.ready, ready],
@@ -19,7 +19,7 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
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  end
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  def index_width
22
- @index_width ||= index_fields.map(&:width).inject(:+)
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+ @index_width ||= index_fields.map(&:width).sum
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  end
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  def index_values
@@ -82,7 +82,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
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  [pready, apb_if.pready],
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  [prdata, apb_if.prdata],
84
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  [pslverr, apb_if.pslverr]
85
- ].map { |lhs, rhs| code << assign(lhs, rhs) << nl }
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+ ].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
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  end
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  end
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  end
@@ -24,10 +24,7 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
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24
  end
25
25
 
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  def total_registers
27
- register_block
28
- .registers
29
- .map(&:count)
30
- .inject(:+)
27
+ register_block.registers.map(&:count).sum
31
28
  end
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29
 
33
30
  private
@@ -2,6 +2,6 @@
2
2
 
3
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  module RgGen
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4
  module SystemVerilog
5
- VERSION = '0.18.0'
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+ VERSION = '0.19.0'
6
6
  end
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  end
metadata CHANGED
@@ -1,14 +1,14 @@
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  --- !ruby/object:Gem::Specification
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  name: rggen-systemverilog
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  version: !ruby/object:Gem::Version
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- version: 0.18.0
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+ version: 0.19.0
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  platform: ruby
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  authors:
7
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  - Taichi Ishitani
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  autorequire:
9
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  bindir: bin
10
10
  cert_chain: []
11
- date: 2019-11-19 00:00:00.000000000 Z
11
+ date: 2020-02-17 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: docile
@@ -54,7 +54,7 @@ dependencies:
54
54
  version: '0'
55
55
  description: 'SystemVerilog RTL and UVM RAL model generators for RgGen.
56
56
 
57
- '
57
+ '
58
58
  email:
59
59
  - rggen@googlegroups.com
60
60
  executables: []
@@ -160,15 +160,15 @@ required_ruby_version: !ruby/object:Gem::Requirement
160
160
  requirements:
161
161
  - - ">="
162
162
  - !ruby/object:Gem::Version
163
- version: '2.3'
163
+ version: '2.4'
164
164
  required_rubygems_version: !ruby/object:Gem::Requirement
165
165
  requirements:
166
166
  - - ">="
167
167
  - !ruby/object:Gem::Version
168
168
  version: '0'
169
169
  requirements: []
170
- rubygems_version: 3.0.3
170
+ rubygems_version: 3.1.2
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171
  signing_key:
172
172
  specification_version: 4
173
- summary: rggen-systemverilog-0.18.0
173
+ summary: rggen-systemverilog-0.19.0
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174
  test_files: []