rggen-systemverilog 0.18.0 → 0.19.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2019 Taichi Ishitani
+Copyright (c) 2019-2020 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -1,5 +1,5 @@
 [![Gem Version](https://badge.fury.io/rb/rggen-systemverilog.svg)](https://badge.fury.io/rb/rggen-systemverilog)
-[![Build Status](https://travis-ci.com/rggen/rggen-systemverilog.svg?branch=master)](https://travis-ci.com/rggen/rggen-systemverilog)
+[![CI](https://github.com/rggen/rggen-systemverilog/workflows/CI/badge.svg)](https://github.com/rggen/rggen-systemverilog/actions?query=workflow%3ACI)
 [![Maintainability](https://api.codeclimate.com/v1/badges/88086c5be538a1564a35/maintainability)](https://codeclimate.com/github/rggen/rggen-systemverilog/maintainability)
 [![codecov](https://codecov.io/gh/rggen/rggen-systemverilog/branch/master/graph/badge.svg)](https://codecov.io/gh/rggen/rggen-systemverilog)
 [![Quality Gate Status](https://sonarcloud.io/api/project_badges/measure?project=rggen_rggen-systemverilog&metric=alert_status)](https://sonarcloud.io/dashboard?id=rggen_rggen-systemverilog)
@@ -34,7 +34,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
 
 ## Copyright & License
 
-Copyright © 2019 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2019-2020 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/systemverilog/common/feature.rb

@@ -16,9 +16,9 @@ module RgGen
           def define_entity(entity_type, creation_method, declaration_type)
             context =
               EntityContext.new(entity_type, creation_method, declaration_type)
-            define_method(entity_type) do |domain, name, **attributes, &block|
+            define_method(entity_type) do |domain, name, attributes = {}, &block|
               entity =
-                create_entity(context, { name: name }.merge(attributes), block)
+                create_entity(context, { name: name }.merge(attributes), &block)
               add_entity(entity, context, domain, name)
             end
           end
@@ -42,10 +42,10 @@ module RgGen
           @package_imports = Hash.new { |h, k| h[k] = [] }
         end
 
-        def create_entity(context, attributes, block)
+        def create_entity(context, attributes, &block)
           creation_method = context.creation_method
           entity_type = context.entity_type
-          __send__(creation_method, entity_type, attributes, block)
+          __send__(creation_method, entity_type, attributes, &block)
         end
 
         def add_entity(entity, context, domain, name)

data/lib/rggen/systemverilog/common/utility.rb

@@ -79,7 +79,7 @@ module RgGen
           [width, bit_length].max
         end
 
-        def argument(name, **attribute)
+        def argument(name, attribute = {})
           DataObject.new(:argument, attribute.merge(name: name)).declaration
         end
 
@@ -90,7 +90,7 @@ module RgGen
           module_definition: ModuleDefinition,
           package_definition: PackageDefinition
         }.each do |method_name, definition|
-          define_method(method_name) do |name, **attributes, &block|
+          define_method(method_name) do |name, attributes = {}, &block|
             definition.new(attributes.merge(name: name), &block).to_code
           end
         end

data/lib/rggen/systemverilog/common/utility/data_object.rb

@@ -7,9 +7,9 @@ module RgGen
         class DataObject
           include Core::Utility::AttributeSetter
 
-          def initialize(object_type, **default_attributes)
+          def initialize(object_type, default_attributes = {})
             @object_type = object_type
-            apply_attributes(default_attributes)
+            apply_attributes(**default_attributes)
             block_given? && yield(self)
           end
 

data/lib/rggen/systemverilog/common/utility/interface_instance.rb

@@ -7,8 +7,8 @@ module RgGen
         class InterfaceInstance
           include Core::Utility::AttributeSetter
 
-          def initialize(**default_attributes)
-            apply_attributes(default_attributes)
+          def initialize(default_attributes = {})
+            apply_attributes(**default_attributes)
             block_given? && yield(self)
           end
 

data/lib/rggen/systemverilog/common/utility/interface_port.rb

@@ -7,8 +7,8 @@ module RgGen
         class InterfacePort
           include Core::Utility::AttributeSetter
 
-          def initialize(**default_attributes)
-            apply_attributes(default_attributes)
+          def initialize(default_attributes = {})
+            apply_attributes(**default_attributes)
             block_given? && yield(self)
           end
 

data/lib/rggen/systemverilog/common/utility/structure_definition.rb

@@ -9,8 +9,8 @@ module RgGen
 
           include Core::Utility::AttributeSetter
 
-          def initialize(**default_attributes, &block)
-            apply_attributes(default_attributes)
+          def initialize(default_attributes = {}, &block)
+            apply_attributes(**default_attributes)
             super(&block)
           end
 

data/lib/rggen/systemverilog/ral/feature.rb

@@ -6,16 +6,14 @@ module RgGen
       class Feature < Common::Feature
         private
 
-        def create_variable(_, attributes, block)
+        def create_variable(_, attributes = {}, &block)
           DataObject.new(
             :variable, attributes.merge(array_format: :unpacked), &block
           )
         end
 
-        def create_parameter(_, attributes, block)
-          DataObject.new(
-            :parameter, attributes, &block
-          )
+        def create_parameter(_, attributes = {}, &block)
+          DataObject.new(:parameter, attributes, &block)
         end
 
         define_entity :variable, :create_variable, :variable

data/lib/rggen/systemverilog/rtl/feature.rb

@@ -6,27 +6,27 @@ module RgGen
       class Feature < Common::Feature
         private
 
-        def create_variable(data_type, attributes, block)
+        def create_variable(data_type, attributes = {}, &block)
           DataObject.new(
             :variable, attributes.merge(data_type: data_type), &block
           )
         end
 
-        def create_interface(_, attributes, block)
+        def create_interface(_, attributes = {}, &block)
           InterfaceInstance.new(attributes, &block)
         end
 
-        def create_argument(direction, attributes, block)
+        def create_argument(direction, attributes = {}, &block)
           DataObject.new(
             :argument, attributes.merge(direction: direction), &block
           )
         end
 
-        def create_interface_port(_, attributes, block)
+        def create_interface_port(_, attributes = {}, &block)
           InterfacePort.new(attributes, &block)
         end
 
-        def create_parameter(parameter_type, attributes, block)
+        def create_parameter(parameter_type, attributes = {}, &block)
           DataObject.new(
             :parameter, attributes.merge(parameter_type: parameter_type), &block
           )

data/lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb

@@ -8,7 +8,7 @@ RgGen.define_simple_feature(:register, :sv_rtl_top) do
 
     pre_build do
       @base_index =
-        register_block.registers.map(&:count).inject(0, :+)
+        register_block.registers.map(&:count).sum
     end
 
     build do
@@ -34,7 +34,7 @@ RgGen.define_simple_feature(:register, :sv_rtl_top) do
       operands =
         register.array? ? [@base_index, offset || local_index] : [@base_index]
       if operands.all? { |operand| operand.is_a?(Integer) }
-        operands.inject(:+)
+        operands.sum
       else
         operands.join('+')
       end

data/lib/rggen/systemverilog/rtl/register/type/external.rb

@@ -14,14 +14,14 @@ RgGen.define_list_item_feature(:register, :type, :external) do
           name: "o_#{register.name}_valid",
           data_type: :logic, width: 1
         }
+        output :register_block, :access, {
+          name: "o_#{register.name}_access",
+          data_type: :logic, width: '$bits(rggen_access)'
+        }
         output :register_block, :address, {
           name: "o_#{register.name}_address",
           data_type: :logic, width: address_width
         }
-        output :register_block, :write, {
-          name: "o_#{register.name}_write",
-          data_type: :logic, width: 1
-        }
         output :register_block, :write_data, {
           name: "o_#{register.name}_data",
           data_type: :logic, width: bus_width
@@ -46,7 +46,7 @@ RgGen.define_list_item_feature(:register, :type, :external) do
           name: 'bus_if', interface_type: 'rggen_bus_if',
           parameter_values: [address_width, bus_width],
           variables: [
-            'valid', 'address', 'write', 'write_data', 'strobe',
+            'valid', 'access', 'address', 'write_data', 'strobe',
             'ready', 'status', 'read_data'
           ]
         }
@@ -58,8 +58,8 @@ RgGen.define_list_item_feature(:register, :type, :external) do
       unless configuration.fold_sv_interface_port?
         [
           [valid, bus_if.valid],
+          [access, bus_if.access],
           [address, bus_if.address],
-          [write, bus_if.write],
           [write_data, bus_if.write_data],
           [strobe, bus_if.strobe],
           [bus_if.ready, ready],

data/lib/rggen/systemverilog/rtl/register/type/indirect.rb

@@ -19,7 +19,7 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
     end
 
     def index_width
-      @index_width ||= index_fields.map(&:width).inject(:+)
+      @index_width ||= index_fields.map(&:width).sum
     end
 
     def index_values

data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb

@@ -82,7 +82,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
           [pready, apb_if.pready],
           [prdata, apb_if.prdata],
           [pslverr, apb_if.pslverr]
-        ].map { |lhs, rhs| code << assign(lhs, rhs) << nl }
+        ].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
       end
     end
   end

data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb

@@ -24,10 +24,7 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
     end
 
     def total_registers
-      register_block
-        .registers
-        .map(&:count)
-        .inject(:+)
+      register_block.registers.map(&:count).sum
     end
 
     private

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.18.0'
+    VERSION = '0.19.0'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.18.0
+  version: 0.19.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2019-11-19 00:00:00.000000000 Z
+date: 2020-02-17 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: docile
@@ -54,7 +54,7 @@ dependencies:
         version: '0'
 description: 'SystemVerilog RTL and UVM RAL model generators for RgGen.
 
-'
+  '
 email:
 - rggen@googlegroups.com
 executables: []
@@ -160,15 +160,15 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: '2.3'
+      version: '2.4'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.0.3
+rubygems_version: 3.1.2
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.18.0
+summary: rggen-systemverilog-0.19.0
 test_files: []