reggae_eda 0.0.6

data/lib/reggae/visitor.rb

@@ -0,0 +1,107 @@
+require_relative 'code'
+
+module Reggae
+
+  class Visitor
+
+    def initialize options={}
+      @indent=-2
+    end
+
+    def inc str=nil
+      say(str) if str
+      @indent+=2
+    end
+
+    def dec
+      @indent-=2
+    end
+
+    def say str
+      puts " "*@indent+str.to_s if @verbose
+    end
+
+    def visit mm
+      inc
+      mm.accept(self,nil)
+      dec
+    end
+
+    def visitMemoryMap mm,args=nil
+      inc "MemoryMap"
+      say mm.name
+      mm.parameters.accept(self,nil)
+      mm.zones.each{|zone| zone.accept(self,nil)}
+      dec
+    end
+
+    def visitParameters params,args=nil
+      inc "Parameters"
+      params.bus.accept(self,nil)
+      params.range.accept(self,nil)
+      dec
+    end
+
+    def visitBus bus,args=nil
+      inc "Bus"
+      say bus.frequency
+      say bus.address_size
+      say bus.data_size
+      dec
+    end
+
+    def visitRange range,args=nil
+      inc "Range"
+      say range.from
+      say range.to
+      dec
+    end
+
+    def visitZone zone,args=nil
+      inc "Zone"
+      say zone.name
+      zone.range.accept(self)
+      zone.registers.each{|reg| reg.accept(self)}
+      zone.subzones.each{|subzone| subzone.accept(self)}
+      dec
+    end
+
+    def visitSubzone zone,args=nil
+      inc "Subzone"
+      say zone.name
+      zone.range.accept(self)
+      zone.registers.each{|reg| reg.accept(self)}
+      dec
+    end
+
+    def visitRegister reg,args=nil
+      inc "Register"
+      say reg.name
+      say reg.address
+      say reg.init
+      reg.bits.each{|bit| bit.accept(self)}
+      reg.bitfields.each{|bitfield| bitfield.accept(self)}
+
+      dec
+    end
+
+    def visitBit bit,args=nil
+      inc "Bit"
+      say bit.position
+      say bit.name
+      say bit.purpose
+      say bit.toggle
+      dec
+    end
+
+    def visitBitfield bitfield,args=nil
+      inc "Bitfield"
+      say bitfield.position
+      say bitfield.name
+      say bitfield.purpose
+      say bitfield.toggle
+      dec
+    end
+
+  end
+end

data/tests/regmap.sexp

@@ -0,0 +1,139 @@
+(memory_map soc
+
+  (parameters
+      (bus
+        (frequency 100)
+        (address_size 8)
+        (data_size 32)
+      )
+
+      (range 0x0 0x7)
+  )
+
+  (zone ram_instr
+    (range 0x0 0x3)
+
+    (register address
+      (address 0x0)
+      (init 0x0)
+      (bitfield 9..0
+        (name value)
+      )
+    )
+
+    (register datain
+      (address 0x1)
+      (init 0x0)
+    )
+
+    (register dataout
+      (address 0x2)
+      (init 0x0)
+      (sampling true)
+    )
+
+    (register control
+      (address 0x3)
+      (init 0x0)
+      (bit 0
+        (name en)
+        (toggle true)
+        (purpose "write to memory")
+      )
+      (bit 1
+        (name wr)
+        (purpose "write")
+        (toggle true)
+      )
+      (bit 2
+        (name reset)
+        (purpose "reset all bram memory")
+        (toggle true)
+      )
+      (bit 3
+        (name mode)
+        (purpose "mode 0 is access from UART")
+      )
+    )
+  )
+
+  (zone ram_data
+    (range 0x4 0x7)
+
+    (register address
+      (address 0x4)
+      (init 0x0)
+      (bitfield 9..0
+        (name value)
+      )
+    )
+
+    (register datain
+      (address 0x5)
+      (init 0x0)
+    )
+
+    (register dataout
+      (address 0x6)
+      (init 0x0)
+      (sampling true)
+    )
+
+    (register control
+      (address 0x7)
+      (init 0x0)
+      (bit 0
+        (name en)
+        (toggle true)
+        (purpose "write to memory")
+      )
+      (bit 1
+        (name wr)
+        (purpose "write")
+        (toggle true)
+      )
+      (bit 2
+        (name reset)
+        (purpose "reset all bram memory")
+        (toggle true)
+      )
+      (bit 3
+        (name mode)
+        (purpose "mode 0 is access from UART")
+      )
+    )
+  )
+
+  (zone processor
+    (range 0x8 0xc)
+
+    (register boot_address
+      (address 0x8)
+      (init 0x0)
+      (bitfield 9..0
+        (name value)
+      )
+    )
+
+    (register control
+      (address 0x9)
+      (init 0x0)
+      (bit 0
+        (name init)
+        (purpose "set the boot_address")
+      )
+      (bit 1
+        (name go)
+        (purpose "run the processor")
+      )
+    )
+
+    (register status
+      (address 0xa)
+      (init 0x0)
+      (bit 0
+        (name stopped)
+      )
+    )
+  )
+)

metadata

@@ -0,0 +1,64 @@
+--- !ruby/object:Gem::Specification
+name: reggae_eda
+version: !ruby/object:Gem::Version
+  version: 0.0.6
+platform: ruby
+authors:
+- Jean-Christophe Le Lann
+autorequire: 
+bindir: bin
+cert_chain: []
+date: 2020-05-28 00:00:00.000000000 Z
+dependencies: []
+description: Generates a bus-based VHDL IP from a register-map specification. An UART-bus
+  master can be added if needed.
+email: jean-christophe.le_lann@ensta-bretagne.fr
+executables:
+- reggae
+extensions: []
+extra_rdoc_files: []
+files:
+- assets/Nexys4DDR_Master.xdc
+- assets/fifo.vhd
+- assets/flag_buf.vhd
+- assets/mod_m_counter.vhd
+- assets/slow_ticker.vhd
+- assets/uart.vhd
+- assets/uart_bus_master.vhd
+- assets/uart_rx.vhd
+- assets/uart_tx.vhd
+- bin/reggae
+- lib/reggae.rb
+- lib/reggae/ast.rb
+- lib/reggae/code.rb
+- lib/reggae/compiler.rb
+- lib/reggae/parser.rb
+- lib/reggae/pretty_printer.rb
+- lib/reggae/version.rb
+- lib/reggae/vhdl_generator.rb
+- lib/reggae/visitor.rb
+- tests/regmap.sexp
+homepage: http://www.ensta-bretagne.fr/lelann/reggae
+licenses:
+- MIT
+metadata: {}
+post_install_message: 
+rdoc_options: []
+require_paths:
+- lib
+required_ruby_version: !ruby/object:Gem::Requirement
+  requirements:
+  - - ">="
+    - !ruby/object:Gem::Version
+      version: '0'
+required_rubygems_version: !ruby/object:Gem::Requirement
+  requirements:
+  - - ">="
+    - !ruby/object:Gem::Version
+      version: '0'
+requirements: []
+rubygems_version: 3.0.6
+signing_key: 
+specification_version: 4
+summary: Register-map generator for VHDL
+test_files: []