reggae_eda 0.0.6
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +7 -0
- data/assets/Nexys4DDR_Master.xdc +255 -0
- data/assets/fifo.vhd +109 -0
- data/assets/flag_buf.vhd +45 -0
- data/assets/mod_m_counter.vhd +36 -0
- data/assets/slow_ticker.vhd +49 -0
- data/assets/uart.vhd +69 -0
- data/assets/uart_bus_master.vhd +256 -0
- data/assets/uart_rx.vhd +90 -0
- data/assets/uart_tx.vhd +102 -0
- data/bin/reggae +6 -0
- data/lib/reggae.rb +3 -0
- data/lib/reggae/ast.rb +72 -0
- data/lib/reggae/code.rb +55 -0
- data/lib/reggae/compiler.rb +110 -0
- data/lib/reggae/parser.rb +281 -0
- data/lib/reggae/pretty_printer.rb +107 -0
- data/lib/reggae/version.rb +3 -0
- data/lib/reggae/vhdl_generator.rb +973 -0
- data/lib/reggae/visitor.rb +107 -0
- data/tests/regmap.sexp +139 -0
- metadata +64 -0
@@ -0,0 +1,107 @@
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require_relative 'code'
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module Reggae
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class Visitor
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def initialize options={}
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@indent=-2
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end
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def inc str=nil
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say(str) if str
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@indent+=2
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end
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def dec
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@indent-=2
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end
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def say str
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puts " "*@indent+str.to_s if @verbose
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end
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def visit mm
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inc
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mm.accept(self,nil)
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dec
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end
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def visitMemoryMap mm,args=nil
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inc "MemoryMap"
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say mm.name
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mm.parameters.accept(self,nil)
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mm.zones.each{|zone| zone.accept(self,nil)}
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dec
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end
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def visitParameters params,args=nil
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inc "Parameters"
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params.bus.accept(self,nil)
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params.range.accept(self,nil)
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dec
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end
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def visitBus bus,args=nil
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inc "Bus"
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say bus.frequency
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say bus.address_size
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say bus.data_size
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dec
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end
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def visitRange range,args=nil
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inc "Range"
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say range.from
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say range.to
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dec
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end
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def visitZone zone,args=nil
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inc "Zone"
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say zone.name
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zone.range.accept(self)
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zone.registers.each{|reg| reg.accept(self)}
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zone.subzones.each{|subzone| subzone.accept(self)}
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dec
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end
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def visitSubzone zone,args=nil
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inc "Subzone"
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say zone.name
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zone.range.accept(self)
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zone.registers.each{|reg| reg.accept(self)}
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dec
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end
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def visitRegister reg,args=nil
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inc "Register"
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say reg.name
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say reg.address
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say reg.init
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reg.bits.each{|bit| bit.accept(self)}
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reg.bitfields.each{|bitfield| bitfield.accept(self)}
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dec
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end
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def visitBit bit,args=nil
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inc "Bit"
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say bit.position
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say bit.name
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say bit.purpose
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say bit.toggle
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dec
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end
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def visitBitfield bitfield,args=nil
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inc "Bitfield"
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say bitfield.position
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say bitfield.name
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say bitfield.purpose
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say bitfield.toggle
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dec
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end
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end
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end
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data/tests/regmap.sexp
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(memory_map soc
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(parameters
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(bus
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(frequency 100)
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(address_size 8)
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(data_size 32)
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)
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(range 0x0 0x7)
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)
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(zone ram_instr
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(range 0x0 0x3)
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(register address
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(address 0x0)
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(init 0x0)
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(bitfield 9..0
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(name value)
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)
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)
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(register datain
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(address 0x1)
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(init 0x0)
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)
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(register dataout
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(address 0x2)
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(init 0x0)
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(sampling true)
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)
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(register control
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(address 0x3)
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(init 0x0)
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(bit 0
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(name en)
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(toggle true)
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(purpose "write to memory")
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)
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(bit 1
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(name wr)
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(purpose "write")
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(toggle true)
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)
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(bit 2
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(name reset)
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(purpose "reset all bram memory")
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(toggle true)
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)
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(bit 3
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(name mode)
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(purpose "mode 0 is access from UART")
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)
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)
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)
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(zone ram_data
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(range 0x4 0x7)
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(register address
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(address 0x4)
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(init 0x0)
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(bitfield 9..0
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(name value)
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)
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)
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(register datain
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(address 0x5)
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(init 0x0)
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)
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(register dataout
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(address 0x6)
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(init 0x0)
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(sampling true)
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)
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(register control
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(address 0x7)
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(init 0x0)
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(bit 0
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(name en)
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(toggle true)
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(purpose "write to memory")
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)
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(bit 1
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(name wr)
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(purpose "write")
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(toggle true)
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)
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(bit 2
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(name reset)
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(purpose "reset all bram memory")
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(toggle true)
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)
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(bit 3
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(name mode)
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(purpose "mode 0 is access from UART")
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)
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)
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)
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(zone processor
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(range 0x8 0xc)
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(register boot_address
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(address 0x8)
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(init 0x0)
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(bitfield 9..0
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(name value)
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)
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)
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(register control
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(address 0x9)
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(init 0x0)
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(bit 0
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(name init)
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(purpose "set the boot_address")
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)
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(bit 1
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(name go)
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(purpose "run the processor")
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)
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)
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(register status
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(address 0xa)
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(init 0x0)
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(bit 0
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(name stopped)
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)
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)
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)
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)
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metadata
ADDED
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--- !ruby/object:Gem::Specification
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name: reggae_eda
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version: !ruby/object:Gem::Version
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version: 0.0.6
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platform: ruby
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authors:
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- Jean-Christophe Le Lann
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autorequire:
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bindir: bin
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cert_chain: []
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date: 2020-05-28 00:00:00.000000000 Z
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dependencies: []
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description: Generates a bus-based VHDL IP from a register-map specification. An UART-bus
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master can be added if needed.
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email: jean-christophe.le_lann@ensta-bretagne.fr
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executables:
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- reggae
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extensions: []
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extra_rdoc_files: []
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files:
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- assets/Nexys4DDR_Master.xdc
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- assets/fifo.vhd
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- assets/flag_buf.vhd
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- assets/mod_m_counter.vhd
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- assets/slow_ticker.vhd
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- assets/uart.vhd
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- assets/uart_bus_master.vhd
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- assets/uart_rx.vhd
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- assets/uart_tx.vhd
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- bin/reggae
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- lib/reggae.rb
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- lib/reggae/ast.rb
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- lib/reggae/code.rb
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- lib/reggae/compiler.rb
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- lib/reggae/parser.rb
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- lib/reggae/pretty_printer.rb
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- lib/reggae/version.rb
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- lib/reggae/vhdl_generator.rb
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- lib/reggae/visitor.rb
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- tests/regmap.sexp
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homepage: http://www.ensta-bretagne.fr/lelann/reggae
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licenses:
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- MIT
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metadata: {}
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post_install_message:
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rdoc_options: []
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require_paths:
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- lib
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required_ruby_version: !ruby/object:Gem::Requirement
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requirements:
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- - ">="
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- !ruby/object:Gem::Version
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version: '0'
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required_rubygems_version: !ruby/object:Gem::Requirement
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requirements:
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- - ">="
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- !ruby/object:Gem::Version
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version: '0'
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requirements: []
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rubygems_version: 3.0.6
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signing_key:
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specification_version: 4
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summary: Register-map generator for VHDL
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test_files: []
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