reggae_eda 0.0.6

data/assets/slow_ticker.vhd

@@ -0,0 +1,49 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity slow_ticker is
+  generic(N : natural := 27);
+  port(
+    reset_n   : in  std_logic;
+    fast_clk  : in  std_logic;
+    slow_clk  : out std_logic; --50% high/low
+    slow_tick : out std_logic  --single pulse on positive edge
+    );
+end entity;
+
+architecture rtl of slow_ticker is
+  signal counter : unsigned(N-1 downto 0);
+  signal slow_clk_r,slow_clk_c : std_logic;
+begin
+
+  counting : process(reset_n,fast_clk)
+  begin
+    if reset_n = '0' then
+      counter <= to_unsigned(0, N);
+      slow_clk_r <= '0';
+    elsif rising_edge(fast_clk) then
+      counter <= counter + 1;
+      slow_clk_r <= slow_clk_c;
+    end if;
+  end process;
+ 
+  slow_clk_c <= counter(N-1);
+  slow_clk <= slow_clk_r;
+  
+  tick : process(reset_n,fast_clk)
+  begin
+    if reset_n = '0' then
+      slow_tick <= '0';
+    elsif rising_edge(fast_clk) then
+      if slow_clk_r='0' then
+        slow_tick <= slow_clk_c xor slow_clk_r;
+      else
+        slow_tick <= '0';
+      end if;
+    end if;
+  end process;
+
+end rtl;
+
+

data/assets/uart.vhd

@@ -0,0 +1,69 @@
+-- Listing 7.4
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+entity uart is
+  generic(
+    -- Default setting:
+    -- 19,200 baud, 8 data bis, 1 stop its, 2^2 FIFO
+    DBIT     : integer := 8;            -- # data bits
+    SB_TICK  : integer := 16;           -- # ticks for stop bits, 16/24/32
+    --   for 1/1.5/2 stop bits
+    DVSR     : integer := 163;          -- baud rate divisor
+    -- DVSR = 50M/(16*baud rate)
+    DVSR_BIT : integer := 8;            -- # bits of DVSR
+    FIFO_W   : integer := 2             -- # addr bits of FIFO
+   -- # words in FIFO=2^FIFO_W
+    );
+  port(
+    clk, reset_n        : in  std_logic;
+    rd_uart, wr_uart  : in  std_logic;
+    rx                : in  std_logic;
+    w_data            : in  std_logic_vector(7 downto 0);
+    tx_full, rx_empty : out std_logic;
+    r_data            : out std_logic_vector(7 downto 0);
+    tx                : out std_logic
+    );
+end uart;
+
+architecture str_arch of uart is
+  signal tick                        : std_logic;
+  signal rx_done_tick                : std_logic;
+  signal tx_fifo_out                 : std_logic_vector(7 downto 0);
+  signal rx_data_out                 : std_logic_vector(7 downto 0);
+  signal tx_empty, tx_fifo_not_empty : std_logic;
+  signal tx_done_tick                : std_logic;
+begin
+
+  baud_gen_unit : entity work.mod_m_counter(arch)
+    generic map(M => DVSR, N => DVSR_BIT)
+    port map(clk => clk, reset_n => reset_n,
+             q   =>open, max_tick => tick);
+
+  uart_rx_unit : entity work.uart_rx(arch)
+    generic map(DBIT => DBIT, SB_TICK => SB_TICK)
+    port map(clk    => clk, reset_n => reset_n, rx => rx,
+             s_tick => tick, rx_done_tick => rx_done_tick,
+             dout   => rx_data_out);
+
+  fifo_rx_unit : entity work.fifo(arch)
+    generic map(B => DBIT, W => FIFO_W)
+    port map(clk   => clk, reset_n => reset_n, rd => rd_uart,
+             wr    => rx_done_tick, w_data => rx_data_out,
+             empty => rx_empty, full => open, r_data => r_data);
+
+  fifo_tx_unit : entity work.fifo(arch)
+    generic map(B => DBIT, W => FIFO_W)
+    port map(clk  => clk, reset_n => reset_n, rd => tx_done_tick,
+             wr   => wr_uart, w_data => w_data, empty => tx_empty,
+             full => tx_full, r_data => tx_fifo_out);
+
+  uart_tx_unit : entity work.uart_tx(arch)
+    generic map(DBIT => DBIT, SB_TICK => SB_TICK)
+    port map(clk          => clk, reset_n => reset_n,
+             tx_start     => tx_fifo_not_empty,
+             s_tick       => tick, din => tx_fifo_out,
+             tx_done_tick => tx_done_tick, tx => tx);
+
+  tx_fifo_not_empty <= not tx_empty;
+end str_arch;

data/assets/uart_bus_master.vhd

@@ -0,0 +1,256 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity uart_bus_master is
+  generic(
+    ADDR_WIDTH : natural :=8;
+    DATA_WIDTH : natural :=32
+    );
+  port(
+    reset_n : in  std_logic;
+    clk     : in  std_logic;
+    -- UART side
+    rx      : in  std_logic;
+    tx      : out std_logic;
+    -- Bus side
+    ce      : out std_logic;
+    we      : out std_logic;
+    address : out unsigned(7 downto 0);
+    datain  : out std_logic_vector(DATA_WIDTH-1 downto 0);
+    dataout : in  std_logic_vector(DATA_WIDTH-1 downto 0);
+    debug   : out std_logic_vector(15 downto 0)
+    );
+end entity;
+
+architecture rtl of uart_bus_master is
+  --
+   constant NB_BYTES_PER_ADDR : natural := ADDR_WIDTH/8;
+   subtype byte_a_type is natural range 0 to NB_BYTES_PER_ADDR;
+   signal byte_a,byte_a_c : byte_a_type;
+
+   constant NB_BYTES_PER_DATA : natural := DATA_WIDTH/8;
+   subtype byte_d_type is natural range 0 to NB_BYTES_PER_DATA;
+   signal byte_d,byte_d_c : byte_d_type;
+  --
+  signal rd_uart, wr_uart, wr_uart_c : std_logic;
+  signal w_data, w_data_c            : std_logic_vector(7 downto 0);
+  signal tx_full, rx_empty           : std_logic;
+  signal r_data                      : std_logic_vector(7 downto 0);
+  --
+  signal data_from_pc_r              : std_logic_vector(7 downto 0);
+  signal data_from_pc_valid_r        : std_logic;
+  --
+  type state_type is (
+    IDLE, WRITING_RCV_ADDR, WRITING_RCV_DATA, WRITING_APPLY_PULSE,
+    READING_RCV_ADDR, READING_APPLY_PULSE_WS, READING_APPLY_PULSE);
+  signal state, state_c           : state_type;
+  --
+  signal sreset                   : std_logic;
+  signal ce_r,ce_c                 : std_logic;
+  signal we_r,we_c                 : std_logic;
+  signal addr_r,addr_c             : std_logic_vector(7 downto 0);
+  signal datain_r,data_c           : std_logic_vector(DATA_WIDTH-1 downto 0);
+  -- debug
+  signal slow_clk, slow_tick      : std_logic;
+  signal done_read, done_read_c   : std_logic;
+  signal done_write, done_write_c : std_logic;
+  signal debug_idle : std_logic;
+begin
+
+  uart_1 : entity work.uart
+    generic map (
+      DBIT     => 8,
+      SB_TICK  => 16,
+      DVSR     => 325,
+      DVSR_BIT => 9,
+      FIFO_W   => 3)
+    port map (
+      clk      => clk,
+      reset_n  => reset_n,
+      rd_uart  => rd_uart,
+      wr_uart  => wr_uart,
+      rx       => rx,
+      w_data   => w_data,
+      tx_full  => tx_full,
+      rx_empty => rx_empty,
+      r_data   => r_data,
+      tx       => tx);
+
+  -- pump the internal UART FIFO *systematically* (when something is written in it)
+  -- no accumulation in the FIFO
+  rd_uart <= not(rx_empty);
+
+  sampling_data_p : process(reset_n, clk)
+  begin
+    if reset_n = '0' then
+      data_from_pc_r       <= (others => '0');
+      data_from_pc_valid_r <= '0';
+    elsif rising_edge(clk) then
+      data_from_pc_valid_r <= '0';
+      if rd_uart = '1' then
+        data_from_pc_r <= r_data;
+        data_from_pc_valid_r <= '1';
+      end if;
+    end if;
+  end process;
+
+  debug_idle <= '1' when state=IDLE else '0';
+  debug <= "00000000" & data_from_pc_r(7 downto 0);
+  --================= BUS bridge =================
+  -- protocol using 8 bits UART :
+  -- for write :
+  -- byte 0 : 00010001=0x11
+  -- byte 1 : address
+  -- byte 2 : data
+  -- for read :
+  -- byte 0 : 00010000=0x10
+  -- byte 1 : address
+  -- =============================================
+  tick : process(reset_n, clk)
+  begin
+    if reset_n = '0' then
+      state      <= IDLE;
+      ce_r       <= '0';
+      we_r       <= '0';
+      addr_r     <= (others => '0');
+      datain_r   <= (others => '0');
+      wr_uart    <= '0';
+      w_data     <= (others => '0');
+      done_read  <= '0';
+      done_write <= '0';
+      byte_a     <= NB_BYTES_PER_ADDR-1;
+      byte_d     <= NB_BYTES_PER_DATA-1;
+    elsif rising_edge(clk) then
+      state      <= state_c;
+      ce_r       <= ce_c;
+      we_r       <= we_c;
+      addr_r     <= addr_c;
+      datain_r   <= data_c;
+      wr_uart    <= wr_uart_c;
+      w_data     <= w_data_c;
+      done_read  <= done_read_c;
+      done_write <= done_write_c;
+      byte_a    <= byte_a_c;
+      byte_d    <= byte_d_c;
+    end if;
+  end process;
+
+  ce <= ce_r;
+  we <= we_r;
+  address <= unsigned(addr_r);
+  datain  <= datain_r;
+
+  comb : process(addr_r, data_from_pc_r, data_from_pc_valid_r, datain_r,
+                 dataout, state, w_data, done_read, done_write,
+                 byte_a,byte_d)
+    variable state_v      : state_type;
+    variable ce_v         : std_logic;
+    variable we_v         : std_logic;
+    variable addr_v       : std_logic_vector(7 downto 0);
+    variable data_v       : std_logic_vector(DATA_WIDTH-1 downto 0);
+    variable wr_uart_v    : std_logic;
+    variable w_data_v     : std_logic_vector(7 downto 0);
+    --debug
+    variable done_read_v  : std_logic;
+    variable done_write_v : std_logic;
+    variable byte_a_v : byte_a_type;
+    variable byte_d_v : byte_d_type;
+  begin
+    state_v      := state;
+    --
+    ce_v         := '0';
+    we_v         := '0';
+    addr_v       := addr_r;
+    data_v       := datain_r;
+    --
+    wr_uart_v    := '0';
+    w_data_v     := w_data;
+    done_read_v  := done_read;
+    done_write_v := done_write;
+    byte_a_v     := byte_a;
+    byte_d_v     := byte_d;
+
+    case state_v is
+
+      when IDLE =>
+        if data_from_pc_valid_r = '1' then
+          if data_from_pc_r = x"11" then
+            state_v := WRITING_RCV_ADDR;
+          elsif data_from_pc_r = x"10" then
+            state_v := READING_RCV_ADDR;
+          end if;
+        end if;
+
+      when WRITING_RCV_ADDR =>
+        if data_from_pc_valid_r = '1' then
+          addr_v((byte_a_v+1)*8-1 downto byte_a_v*8) := data_from_pc_r;--WHEN addr is 8 bits
+          if byte_a_v/=0 then
+            byte_a_v:=byte_a_v-1;
+          else
+            byte_a_v:=NB_BYTES_PER_ADDR-1;
+            state_v := WRITING_RCV_DATA;
+          end if;
+        end if;
+
+      when WRITING_RCV_DATA =>
+        if data_from_pc_valid_r = '1' then
+          data_v((byte_d_v+1)*8-1 downto byte_d_v*8) := data_from_pc_r;
+          if byte_d_v /=0 then
+            byte_d_v := byte_d_v-1;
+          else
+            ce_v    := '1';
+            we_v    := '1';
+            byte_d_v   := NB_BYTES_PER_DATA-1;
+            state_v     := IDLE;
+            done_read_v := '1';
+          end if;
+        end if;
+
+      when READING_RCV_ADDR =>
+        if data_from_pc_valid_r = '1' then
+          addr_v((byte_a_v+1)*8-1 downto byte_a_v*8) := data_from_pc_r;--WHEN addr is 8 bits
+          if byte_a_v/=0 then
+            byte_a_v:=byte_a_v-1;
+          else
+            ce_v    := '1';
+            we_v    := '0';
+            byte_a_v:=NB_BYTES_PER_ADDR-1;
+            state_v := READING_APPLY_PULSE_WS;
+          end if;
+        end if;
+
+      when READING_APPLY_PULSE_WS =>
+        state_v := READING_APPLY_PULSE;
+
+      when READING_APPLY_PULSE =>
+        wr_uart_v   := '1';
+        w_data_v    := dataout((byte_d_v+1)*8-1 downto (byte_d_v*8));
+        if byte_d_v /=0 then
+          byte_d_v := byte_d_v-1;
+        else
+          byte_d_v   := NB_BYTES_PER_DATA-1;
+          state_v     := IDLE;
+          done_read_v := '1';
+        end if;
+      when others =>
+        null;
+    end case;
+
+    state_c     <= state_v;
+    --
+    ce_c        <= ce_v;
+    we_c        <= we_v;
+    addr_c      <= addr_v;
+    data_c      <= data_v;
+    --
+    wr_uart_c   <= wr_uart_v;
+    w_data_c    <= w_data_v;
+    done_read_c <= done_read_v;
+    done_read_c <= done_write_v;
+    byte_a_c   <= byte_a_v;
+    byte_d_c   <= byte_d_v;
+
+  end process;
+
+end rtl;

data/assets/uart_rx.vhd

@@ -0,0 +1,90 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+entity uart_rx is
+  generic(
+    DBIT    : integer := 8;             -- # data bits
+    SB_TICK : integer := 16             -- # ticks for stop bits
+    );
+  port(
+    clk, reset_n   : in  std_logic;
+    rx           : in  std_logic;
+    s_tick       : in  std_logic;
+    rx_done_tick : out std_logic;
+    dout         : out std_logic_vector(7 downto 0)
+    );
+end uart_rx;
+
+architecture arch of uart_rx is
+  type state_type is (idle, start, data, stop);
+  signal state_reg, state_next : state_type;
+  signal s_reg, s_next         : unsigned(3 downto 0);
+  signal n_reg, n_next         : unsigned(2 downto 0);
+  signal b_reg, b_next         : std_logic_vector(7 downto 0);
+begin
+  -- FSMD state & data registers
+  process(clk, reset_n)
+  begin
+    if reset_n = '0' then
+      state_reg <= idle;
+      s_reg     <= (others => '0');
+      n_reg     <= (others => '0');
+      b_reg     <= (others => '0');
+    elsif (clk'event and clk = '1') then
+      state_reg <= state_next;
+      s_reg     <= s_next;
+      n_reg     <= n_next;
+      b_reg     <= b_next;
+    end if;
+  end process;
+  -- next-state logic & data path functional units/routing
+  process(state_reg, s_reg, n_reg, b_reg, s_tick, rx)
+  begin
+    state_next   <= state_reg;
+    s_next       <= s_reg;
+    n_next       <= n_reg;
+    b_next       <= b_reg;
+    rx_done_tick <= '0';
+    case state_reg is
+      when idle =>
+        if rx = '0' then
+          state_next <= start;
+          s_next     <= (others => '0');
+        end if;
+      when start =>
+        if (s_tick = '1') then
+          if s_reg = 7 then
+            state_next <= data;
+            s_next     <= (others => '0');
+            n_next     <= (others => '0');
+          else
+            s_next <= s_reg + 1;
+          end if;
+        end if;
+      when data =>
+        if (s_tick = '1') then
+          if s_reg = 15 then
+            s_next <= (others => '0');
+            b_next <= rx & b_reg(7 downto 1);
+            if n_reg = (DBIT-1) then
+              state_next <= stop;
+            else
+              n_next <= n_reg + 1;
+            end if;
+          else
+            s_next <= s_reg + 1;
+          end if;
+        end if;
+      when stop =>
+        if (s_tick = '1') then
+          if s_reg = (SB_TICK-1) then
+            state_next   <= idle;
+            rx_done_tick <= '1';
+          else
+            s_next <= s_reg + 1;
+          end if;
+        end if;
+    end case;
+  end process;
+  dout <= b_reg;
+end arch;