pq_crypto 0.6.4 → 0.6.6

data/ext/pqcrypto/vendor/mldsa-native/mldsa/src/native/x86_64/src/mldsa_polyz_unpack_19_avx2_asm.S

@@ -0,0 +1,355 @@
+/*
+ * Copyright (c) The mldsa-native project authors
+ * SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
+ */
+
+/* References
+ * ==========
+ *
+ * - [REF_AVX2]
+ *   CRYSTALS-Dilithium optimized AVX2 implementation
+ *   Bai, Ducas, Kiltz, Lepoint, Lyubashevsky, Schwabe, Seiler, Stehlé
+ *   https://github.com/pq-crystals/dilithium/tree/master/avx2
+ */
+
+/*
+ * This file is derived from the public domain
+ * AVX2 Dilithium implementation @[REF_AVX2].
+ */
+
+
+/*yaml
+  Name: polyz_unpack_19_avx2_asm
+  Description: x86_64 AVX2 unpacking of 19-bit packed coefficients.
+    Unpack polynomial z with 20-bit packed coefficients (GAMMA1 = 2^19),
+    mapping packed [0, 2^20-1] to signed [-(2^19-1), 2^19] via GAMMA1 - x.
+  Signature: void mld_polyz_unpack_19_avx2_asm(int32_t *r, const uint8_t *a)
+  ABI:
+    Architecture: x86_64
+    CallingConvention: SysV
+    Features: [AVX2]
+    rdi:
+      type: buffer
+      size_bytes: 1024
+      permissions: write-only
+      c_parameter: int32_t *r
+      description: Output polynomial (256 x int32_t)
+    rsi:
+      type: buffer
+      size_bytes: 640
+      permissions: read-only
+      c_parameter: const uint8_t *a
+      description: Packed input bytes
+*/
+
+#include "../../../common.h"
+
+#if defined(MLD_ARITH_BACKEND_X86_64_DEFAULT) &&   \
+    (!defined(MLD_CONFIG_NO_SIGN_API) ||           \
+     !defined(MLD_CONFIG_NO_VERIFY_API)) &&        \
+    !defined(MLD_CONFIG_MULTILEVEL_NO_SHARED) &&   \
+    (defined(MLD_CONFIG_MULTILEVEL_WITH_SHARED) || \
+     (MLD_CONFIG_PARAMETER_SET == 65 || MLD_CONFIG_PARAMETER_SET == 87))
+
+
+/*
+ * WARNING: This file is auto-derived from the mldsa-native source file
+ *   dev/x86_64/src/mldsa_polyz_unpack_19_avx2_asm.S using scripts/simpasm. Do not modify it directly.
+ */
+
+.text
+.balign 4
+.global MLD_ASM_NAMESPACE(polyz_unpack_19_avx2_asm)
+MLD_ASM_FN_SYMBOL(polyz_unpack_19_avx2_asm)
+
+        .cfi_startproc
+        movabsq $-0xfbfcfd00fdff00, %rax # imm = 0xFF040302FF020100
+        vmovq %rax, %xmm1
+        movabsq $-0xf6f7f800f8f9fb, %rax # imm = 0xFF090807FF070605
+        vpinsrq $0x1, %rax, %xmm1, %xmm1
+        movabsq $-0xe5e6e700e7e8ea, %rax # imm = 0xFF1A1918FF181716
+        vmovq %rax, %xmm5
+        movabsq $-0xe0e1e200e2e3e5, %rax # imm = 0xFF1F1E1DFF1D1C1B
+        vpinsrq $0x1, %rax, %xmm5, %xmm5
+        vinserti128 $0x1, %xmm5, %ymm1, %ymm1
+        movabsq $0x400000000, %rax      # imm = 0x400000000
+        vmovq %rax, %xmm2
+        movabsq $0x400000000, %rax      # imm = 0x400000000
+        vpinsrq $0x1, %rax, %xmm2, %xmm2
+        vinserti128 $0x1, %xmm2, %ymm2, %ymm2
+        movl $0xfffff, %eax          # imm = 0xFFFFF
+        vmovd %eax, %xmm3
+        vpbroadcastd %xmm3, %ymm3
+        movl $0x80000, %eax          # imm = 0x80000
+        vmovd %eax, %xmm4
+        vpbroadcastd %xmm4, %ymm4
+        vmovdqu (%rsi), %xmm0
+        vmovdqu 0x4(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, (%rdi)
+        vmovdqu 0x14(%rsi), %xmm0
+        vmovdqu 0x18(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x20(%rdi)
+        vmovdqu 0x28(%rsi), %xmm0
+        vmovdqu 0x2c(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x40(%rdi)
+        vmovdqu 0x3c(%rsi), %xmm0
+        vmovdqu 0x40(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x60(%rdi)
+        vmovdqu 0x50(%rsi), %xmm0
+        vmovdqu 0x54(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x80(%rdi)
+        vmovdqu 0x64(%rsi), %xmm0
+        vmovdqu 0x68(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0xa0(%rdi)
+        vmovdqu 0x78(%rsi), %xmm0
+        vmovdqu 0x7c(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0xc0(%rdi)
+        vmovdqu 0x8c(%rsi), %xmm0
+        vmovdqu 0x90(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0xe0(%rdi)
+        vmovdqu 0xa0(%rsi), %xmm0
+        vmovdqu 0xa4(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x100(%rdi)
+        vmovdqu 0xb4(%rsi), %xmm0
+        vmovdqu 0xb8(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x120(%rdi)
+        vmovdqu 0xc8(%rsi), %xmm0
+        vmovdqu 0xcc(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x140(%rdi)
+        vmovdqu 0xdc(%rsi), %xmm0
+        vmovdqu 0xe0(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x160(%rdi)
+        vmovdqu 0xf0(%rsi), %xmm0
+        vmovdqu 0xf4(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x180(%rdi)
+        vmovdqu 0x104(%rsi), %xmm0
+        vmovdqu 0x108(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x1a0(%rdi)
+        vmovdqu 0x118(%rsi), %xmm0
+        vmovdqu 0x11c(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x1c0(%rdi)
+        vmovdqu 0x12c(%rsi), %xmm0
+        vmovdqu 0x130(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x1e0(%rdi)
+        vmovdqu 0x140(%rsi), %xmm0
+        vmovdqu 0x144(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x200(%rdi)
+        vmovdqu 0x154(%rsi), %xmm0
+        vmovdqu 0x158(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x220(%rdi)
+        vmovdqu 0x168(%rsi), %xmm0
+        vmovdqu 0x16c(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x240(%rdi)
+        vmovdqu 0x17c(%rsi), %xmm0
+        vmovdqu 0x180(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x260(%rdi)
+        vmovdqu 0x190(%rsi), %xmm0
+        vmovdqu 0x194(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x280(%rdi)
+        vmovdqu 0x1a4(%rsi), %xmm0
+        vmovdqu 0x1a8(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x2a0(%rdi)
+        vmovdqu 0x1b8(%rsi), %xmm0
+        vmovdqu 0x1bc(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x2c0(%rdi)
+        vmovdqu 0x1cc(%rsi), %xmm0
+        vmovdqu 0x1d0(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x2e0(%rdi)
+        vmovdqu 0x1e0(%rsi), %xmm0
+        vmovdqu 0x1e4(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x300(%rdi)
+        vmovdqu 0x1f4(%rsi), %xmm0
+        vmovdqu 0x1f8(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x320(%rdi)
+        vmovdqu 0x208(%rsi), %xmm0
+        vmovdqu 0x20c(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x340(%rdi)
+        vmovdqu 0x21c(%rsi), %xmm0
+        vmovdqu 0x220(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x360(%rdi)
+        vmovdqu 0x230(%rsi), %xmm0
+        vmovdqu 0x234(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x380(%rdi)
+        vmovdqu 0x244(%rsi), %xmm0
+        vmovdqu 0x248(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x3a0(%rdi)
+        vmovdqu 0x258(%rsi), %xmm0
+        vmovdqu 0x25c(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x3c0(%rdi)
+        vmovdqu 0x26c(%rsi), %xmm0
+        vmovdqu 0x270(%rsi), %xmm5
+        vinserti128 $0x1, %xmm5, %ymm0, %ymm0
+        vpshufb %ymm1, %ymm0, %ymm0
+        vpsrlvd %ymm2, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubd %ymm0, %ymm4, %ymm0
+        vmovdqa %ymm0, 0x3e0(%rdi)
+        retq
+        .cfi_endproc
+
+MLD_ASM_FN_SIZE(polyz_unpack_19_avx2_asm)
+
+
+#endif /* MLD_ARITH_BACKEND_X86_64_DEFAULT && (!MLD_CONFIG_NO_SIGN_API || \
+          !MLD_CONFIG_NO_VERIFY_API) && !MLD_CONFIG_MULTILEVEL_NO_SHARED && \
+          (MLD_CONFIG_MULTILEVEL_WITH_SHARED || MLD_CONFIG_PARAMETER_SET == 65 \
+          || MLD_CONFIG_PARAMETER_SET == 87) */
+
+#if defined(__ELF__)
+.section .note.GNU-stack,"",%progbits
+#endif

data/ext/pqcrypto/vendor/mldsa-native/mldsa/src/native/x86_64/src/mldsa_rej_uniform_avx2_asm.S

@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) The mldsa-native project authors
+ * SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
+ */
+
+/* References
+ * ==========
+ *
+ * - [REF_AVX2]
+ *   CRYSTALS-Dilithium optimized AVX2 implementation
+ *   Bai, Ducas, Kiltz, Lepoint, Lyubashevsky, Schwabe, Seiler, Stehlé
+ *   https://github.com/pq-crystals/dilithium/tree/master/avx2
+ */
+
+/*
+ * This file is derived from the public domain
+ * AVX2 Dilithium implementation @[REF_AVX2].
+ */
+
+/*yaml
+  Name: rej_uniform_avx2_asm
+  Description: x86_64 AVX2 rejection sampling of uniform coefficients mod q.
+    Extract 23-bit values from the input byte buffer and accept those that are
+    < MLDSA_Q, writing accepted coefficients to the output buffer. Returns the
+    number of valid coefficients written (at most 256).
+  Signature: unsigned mld_rej_uniform_avx2_asm(int32_t *r, const uint8_t buf[840], const uint8_t table[256][8])
+  ABI:
+    Architecture: x86_64
+    CallingConvention: SysV
+    Features: [AVX2]
+    rdi:
+      type: buffer
+      size_bytes: 1024
+      permissions: write-only
+      c_parameter: int32_t *r
+      description: Output buffer (256 x int32_t)
+    rsi:
+      type: buffer
+      size_bytes: 840
+      permissions: read-only
+      c_parameter: const uint8_t buf[840]
+      description: Input buffer (MLD_POLY_UNIFORM_NBLOCKS * SHAKE128_RATE = 5 * 168)
+    rdx:
+      type: buffer
+      size_bytes: 2048
+      permissions: read-only
+      c_parameter: const uint8_t table[256][8]
+      description: Lookup table (256 x 8 x uint8_t)
+*/
+
+#include "../../../common.h"
+#if defined(MLD_ARITH_BACKEND_X86_64_DEFAULT) && \
+    !defined(MLD_CONFIG_MULTILEVEL_NO_SHARED)
+
+/*
+ * WARNING: This file is auto-derived from the mldsa-native source file
+ *   dev/x86_64/src/mldsa_rej_uniform_avx2_asm.S using scripts/simpasm. Do not modify it directly.
+ */
+
+.text
+.balign 4
+.global MLD_ASM_NAMESPACE(rej_uniform_avx2_asm)
+MLD_ASM_FN_SYMBOL(rej_uniform_avx2_asm)
+
+        .cfi_startproc
+        movabsq $-0xfafbfc00fdff00, %r10 # imm = 0xFF050403FF020100
+        vmovq %r10, %xmm0
+        movabsq $-0xf4f5f600f7f8fa, %r10 # imm = 0xFF0B0A09FF080706
+        vpinsrq $0x1, %r10, %xmm0, %xmm0
+        movabsq $-0xf6f7f800f9fafc, %r10 # imm = 0xFF090807FF060504
+        vmovq %r10, %xmm3
+        movabsq $-0xf0f1f200f3f4f6, %r10 # imm = 0xFF0F0E0DFF0C0B0A
+        vpinsrq $0x1, %r10, %xmm3, %xmm3
+        vinserti128 $0x1, %xmm3, %ymm0, %ymm0
+        movl $0x7fffff, %r8d         # imm = 0x7FFFFF
+        vmovd %r8d, %xmm1
+        vpbroadcastd %xmm1, %ymm1
+        movl $0x7fe001, %r8d         # imm = 0x7FE001
+        vmovd %r8d, %xmm2
+        vpbroadcastd %xmm2, %ymm2
+        xorl %eax, %eax
+        xorl %ecx, %ecx
+
+Lmld_rej_uniform_avx2_asm_loop:
+        cmpl $0xf8, %eax
+        ja Lmld_rej_uniform_avx2_asm_scalar
+        cmpl $0x328, %ecx            # imm = 0x328
+        ja Lmld_rej_uniform_avx2_asm_scalar
+        vmovdqu (%rsi,%rcx), %ymm3
+        addl $0x18, %ecx
+        vpermq $0x94, %ymm3, %ymm3     # ymm3 = ymm3[0,1,1,2]
+        vpshufb %ymm0, %ymm3, %ymm3
+        vpand %ymm1, %ymm3, %ymm3
+        vpsubd %ymm2, %ymm3, %ymm4
+        vmovmskps %ymm4, %r8d
+        popcntl %r8d, %r9d
+        vmovq (%rdx,%r8,8), %xmm4
+        vpmovzxbd %xmm4, %ymm4    # ymm4 = xmm4[0],zero,zero,zero,xmm4[1],zero,zero,zero,xmm4[2],zero,zero,zero,xmm4[3],zero,zero,zero,xmm4[4],zero,zero,zero,xmm4[5],zero,zero,zero,xmm4[6],zero,zero,zero,xmm4[7],zero,zero,zero
+        vpermd %ymm3, %ymm4, %ymm3
+        vmovdqu %ymm3, (%rdi,%rax,4)
+        addl %r9d, %eax
+        jmp Lmld_rej_uniform_avx2_asm_loop
+
+Lmld_rej_uniform_avx2_asm_scalar:
+        cmpl $0x100, %eax            # imm = 0x100
+        jae Lmld_rej_uniform_avx2_asm_done
+        cmpl $0x345, %ecx            # imm = 0x345
+        ja Lmld_rej_uniform_avx2_asm_done
+        movzwl (%rsi,%rcx), %r8d
+        movzbl 0x2(%rsi,%rcx), %r9d
+        shll $0x10, %r9d
+        orl %r9d, %r8d
+        andl $0x7fffff, %r8d         # imm = 0x7FFFFF
+        addl $0x3, %ecx
+        cmpl $0x7fe001, %r8d         # imm = 0x7FE001
+        jae Lmld_rej_uniform_avx2_asm_scalar
+        movl %r8d, (%rdi,%rax,4)
+        addl $0x1, %eax
+        jmp Lmld_rej_uniform_avx2_asm_scalar
+
+Lmld_rej_uniform_avx2_asm_done:
+        retq
+        .cfi_endproc
+
+MLD_ASM_FN_SIZE(rej_uniform_avx2_asm)
+
+#endif /* MLD_ARITH_BACKEND_X86_64_DEFAULT && !MLD_CONFIG_MULTILEVEL_NO_SHARED \
+        */
+
+#if defined(__ELF__)
+.section .note.GNU-stack,"",%progbits
+#endif

data/ext/pqcrypto/vendor/mldsa-native/mldsa/src/native/x86_64/src/mldsa_rej_uniform_eta2_avx2_asm.S

@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) The mldsa-native project authors
+ * SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
+ */
+
+/* References
+ * ==========
+ *
+ * - [REF_AVX2]
+ *   CRYSTALS-Dilithium optimized AVX2 implementation
+ *   Bai, Ducas, Kiltz, Lepoint, Lyubashevsky, Schwabe, Seiler, Stehlé
+ *   https://github.com/pq-crystals/dilithium/tree/master/avx2
+ */
+
+/*
+ * This file is derived from the public domain
+ * AVX2 Dilithium implementation @[REF_AVX2].
+ */
+
+/*yaml
+  Name: rej_uniform_eta2_avx2_asm
+  Description: x86_64 AVX2 rejection sampling of eta=2 secret coefficients.
+    Extracts 4-bit nibbles from the input byte buffer, accepts those < 15,
+    and maps an accepted nibble n to the coefficient 2 - (n mod 5) via a
+    centered modulo-5 reduction, producing values in [-2, 2].
+  Signature: unsigned mld_rej_uniform_eta2_avx2_asm(int32_t *r, const uint8_t *buf, const uint8_t table[256][8])
+  ABI:
+    Architecture: x86_64
+    CallingConvention: SysV
+    Features: [AVX2]
+    rdi:
+      type: buffer
+      size_bytes: 1024
+      permissions: write-only
+      c_parameter: int32_t *r
+      description: Output coefficient buffer (256 x int32_t)
+    rsi:
+      type: buffer
+      size_bytes: 136
+      permissions: read-only
+      c_parameter: const uint8_t *buf
+      description: Input byte buffer (MLD_AVX2_REJ_UNIFORM_ETA2_BUFLEN = 136)
+    rdx:
+      type: buffer
+      size_bytes: 2048
+      permissions: read-only
+      c_parameter: const uint8_t *table
+      description: Lookup table (256 x 8 uint8_t = mld_rej_uniform_table)
+*/
+
+#include "../../../common.h"
+#if defined(MLD_ARITH_BACKEND_X86_64_DEFAULT) && !defined(MLD_CONFIG_MULTILEVEL_NO_SHARED)
+
+/*
+ * WARNING: This file is auto-derived from the mldsa-native source file
+ *   dev/x86_64/src/mldsa_rej_uniform_eta2_avx2_asm.S using scripts/simpasm. Do not modify it directly.
+ */
+
+.text
+.balign 4
+.global MLD_ASM_NAMESPACE(rej_uniform_eta2_avx2_asm)
+MLD_ASM_FN_SYMBOL(rej_uniform_eta2_avx2_asm)
+
+        .cfi_startproc
+        movl $0xf0f0f0f, %r8d        # imm = 0xF0F0F0F
+        vmovd %r8d, %xmm3
+        vpbroadcastd %xmm3, %ymm3
+        movl $0x2020202, %r8d        # imm = 0x2020202
+        vmovd %r8d, %xmm4
+        vpbroadcastd %xmm4, %ymm4
+        movl $0xf0f0f0f, %r8d        # imm = 0xF0F0F0F
+        vmovd %r8d, %xmm5
+        vpbroadcastd %xmm5, %ymm5
+        movl $0xffffe660, %r8d       # imm = 0xFFFFE660
+        vpinsrw $0x0, %r8d, %xmm6, %xmm6
+        vpbroadcastw %xmm6, %ymm6
+        movl $0x5, %r8d
+        vpinsrw $0x0, %r8d, %xmm7, %xmm7
+        vpbroadcastw %xmm7, %ymm7
+        xorl %eax, %eax
+        xorl %ecx, %ecx
+
+Lmld_rej_uniform_eta2_avx2_asm_loop:
+        cmpl $0xf8, %eax
+        ja Lmld_rej_uniform_eta2_avx2_asm_scalar
+        cmpl $0x78, %ecx
+        ja Lmld_rej_uniform_eta2_avx2_asm_scalar
+        vpmovzxbw (%rsi,%rcx), %ymm0
+        vpsllw $0x4, %ymm0, %ymm1
+        vpor %ymm1, %ymm0, %ymm0
+        vpand %ymm3, %ymm0, %ymm0
+        vpsubb %ymm5, %ymm0, %ymm1
+        vpsubb %ymm0, %ymm4, %ymm0
+        vpmovmskb %ymm1, %r8d
+        vextracti128 $0x0, %ymm0, %xmm8
+        movzbl %r8b, %r10d
+        vmovq (%rdx,%r10,8), %xmm9
+        vpshufb %xmm9, %xmm8, %xmm9
+        vpmovsxbd %xmm9, %ymm1
+        vpmulhrsw %ymm6, %ymm1, %ymm2
+        vpmullw %ymm7, %ymm2, %ymm2
+        vpaddd %ymm2, %ymm1, %ymm1
+        vmovdqu %ymm1, (%rdi,%rax,4)
+        popcntl %r10d, %r9d
+        addl %r9d, %eax
+        shrl $0x8, %r8d
+        addl $0x4, %ecx
+        cmpl $0xf8, %eax
+        ja Lmld_rej_uniform_eta2_avx2_asm_scalar
+        vpsrldq $0x8, %xmm8, %xmm8      # xmm8 = xmm8[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero
+        movzbl %r8b, %r10d
+        vmovq (%rdx,%r10,8), %xmm9
+        vpshufb %xmm9, %xmm8, %xmm9
+        vpmovsxbd %xmm9, %ymm1
+        vpmulhrsw %ymm6, %ymm1, %ymm2
+        vpmullw %ymm7, %ymm2, %ymm2
+        vpaddd %ymm2, %ymm1, %ymm1
+        vmovdqu %ymm1, (%rdi,%rax,4)
+        popcntl %r10d, %r9d
+        addl %r9d, %eax
+        shrl $0x8, %r8d
+        addl $0x4, %ecx
+        cmpl $0xf8, %eax
+        ja Lmld_rej_uniform_eta2_avx2_asm_scalar
+        vextracti128 $0x1, %ymm0, %xmm8
+        movzbl %r8b, %r10d
+        vmovq (%rdx,%r10,8), %xmm9
+        vpshufb %xmm9, %xmm8, %xmm9
+        vpmovsxbd %xmm9, %ymm1
+        vpmulhrsw %ymm6, %ymm1, %ymm2
+        vpmullw %ymm7, %ymm2, %ymm2
+        vpaddd %ymm2, %ymm1, %ymm1
+        vmovdqu %ymm1, (%rdi,%rax,4)
+        popcntl %r10d, %r9d
+        addl %r9d, %eax
+        shrl $0x8, %r8d
+        addl $0x4, %ecx
+        cmpl $0xf8, %eax
+        ja Lmld_rej_uniform_eta2_avx2_asm_scalar
+        vpsrldq $0x8, %xmm8, %xmm8      # xmm8 = xmm8[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero
+        movzbl %r8b, %r10d
+        vmovq (%rdx,%r10,8), %xmm9
+        vpshufb %xmm9, %xmm8, %xmm9
+        vpmovsxbd %xmm9, %ymm1
+        vpmulhrsw %ymm6, %ymm1, %ymm2
+        vpmullw %ymm7, %ymm2, %ymm2
+        vpaddd %ymm2, %ymm1, %ymm1
+        vmovdqu %ymm1, (%rdi,%rax,4)
+        popcntl %r10d, %r9d
+        addl %r9d, %eax
+        addl $0x4, %ecx
+        jmp Lmld_rej_uniform_eta2_avx2_asm_loop
+
+Lmld_rej_uniform_eta2_avx2_asm_scalar:
+        cmpl $0x100, %eax            # imm = 0x100
+        jae Lmld_rej_uniform_eta2_avx2_asm_done
+        cmpl $0x88, %ecx
+        jae Lmld_rej_uniform_eta2_avx2_asm_done
+        movzbl (%rsi,%rcx), %r11d
+        incl %ecx
+        movl %r11d, %r10d
+        andl $0xf, %r10d
+        cmpl $0xf, %r10d
+        jae Lmld_rej_uniform_eta2_avx2_asm_high_nibble
+        movl %r10d, %r11d
+        imull $0xcd, %r11d, %r11d
+        shrl $0xa, %r11d
+        imull $0x5, %r11d, %r11d
+        subl %r11d, %r10d
+        movl $0x2, %r11d
+        subl %r10d, %r11d
+        movl %r11d, (%rdi,%rax,4)
+        incl %eax
+        cmpl $0x100, %eax            # imm = 0x100
+        jae Lmld_rej_uniform_eta2_avx2_asm_done
+
+Lmld_rej_uniform_eta2_avx2_asm_high_nibble:
+        movzbl -0x1(%rsi,%rcx), %r11d
+        shrl $0x4, %r11d
+        andl $0xf, %r11d
+        cmpl $0xf, %r11d
+        jae Lmld_rej_uniform_eta2_avx2_asm_scalar
+        movl %r11d, %r10d
+        imull $0xcd, %r10d, %r10d
+        shrl $0xa, %r10d
+        imull $0x5, %r10d, %r10d
+        subl %r10d, %r11d
+        movl $0x2, %r10d
+        subl %r11d, %r10d
+        movl %r10d, (%rdi,%rax,4)
+        incl %eax
+        jmp Lmld_rej_uniform_eta2_avx2_asm_scalar
+
+Lmld_rej_uniform_eta2_avx2_asm_done:
+        retq
+        .cfi_endproc
+
+MLD_ASM_FN_SIZE(rej_uniform_eta2_avx2_asm)
+
+#endif /* MLD_ARITH_BACKEND_X86_64_DEFAULT && !MLD_CONFIG_MULTILEVEL_NO_SHARED \
+        */
+
+#if defined(__ELF__)
+.section .note.GNU-stack,"",%progbits
+#endif