passenger 5.1.4 → 5.1.5

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/atomic_template.hpp

@@ -78,9 +78,9 @@ class base_atomic< T, int >
 private:
     typedef T value_type;
     typedef T difference_type;
-    typedef atomics::detail::operations< storage_size_of< value_type >::value, boost::is_signed< T >::value > operations;
 
 protected:
+    typedef atomics::detail::operations< storage_size_of< value_type >::value, boost::is_signed< T >::value > operations;
     typedef value_type value_arg_type;
 
 public:
@@ -234,9 +234,9 @@ class base_atomic< bool, int >
 {
 private:
     typedef bool value_type;
-    typedef atomics::detail::operations< 1u, false > operations;
 
 protected:
+    typedef atomics::detail::operations< 1u, false > operations;
     typedef value_type value_arg_type;
 
 public:
@@ -321,9 +321,9 @@ class base_atomic< T, void >
 {
 private:
     typedef T value_type;
-    typedef atomics::detail::operations< storage_size_of< value_type >::value, false > operations;
 
 protected:
+    typedef atomics::detail::operations< storage_size_of< value_type >::value, false > operations;
     typedef value_type const& value_arg_type;
 
 public:
@@ -410,9 +410,9 @@ class base_atomic< T*, void* >
 private:
     typedef T* value_type;
     typedef std::ptrdiff_t difference_type;
-    typedef atomics::detail::operations< storage_size_of< value_type >::value, false > operations;
 
 protected:
+    typedef atomics::detail::operations< storage_size_of< value_type >::value, false > operations;
     typedef value_type value_arg_type;
 
 public:
@@ -540,9 +540,9 @@ class base_atomic< void*, void* >
 private:
     typedef void* value_type;
     typedef std::ptrdiff_t difference_type;
-    typedef atomics::detail::operations< storage_size_of< value_type >::value, false > operations;
 
 protected:
+    typedef atomics::detail::operations< storage_size_of< value_type >::value, false > operations;
     typedef value_type value_arg_type;
 
 public:
@@ -676,6 +676,9 @@ private:
 public:
     typedef typename base_type::storage_type storage_type;
 
+public:
+    static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = base_type::operations::is_always_lock_free;
+
 public:
     BOOST_DEFAULTED_FUNCTION(atomic(), BOOST_NOEXCEPT {})
 
@@ -706,6 +709,9 @@ public:
     BOOST_DELETED_FUNCTION(atomic& operator= (atomic const&) volatile)
 };
 
+template< typename T >
+BOOST_CONSTEXPR_OR_CONST bool atomic< T >::is_always_lock_free;
+
 typedef atomic< char > atomic_char;
 typedef atomic< unsigned char > atomic_uchar;
 typedef atomic< signed char > atomic_schar;

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/bitwise_cast.hpp

@@ -29,6 +29,17 @@ namespace boost {
 namespace atomics {
 namespace detail {
 
+template< typename T >
+BOOST_FORCEINLINE T* addressof(T& value) BOOST_NOEXCEPT
+{
+    // Note: The point of using a local struct as the intermediate type instead of char is to avoid gcc warnings
+    // if T is a const volatile char*:
+    // warning: casting ‘const volatile char* const’ to ‘const volatile char&’ does not dereference pointer
+    // The local struct makes sure T is not related to the cast target type.
+    struct opaque_type;
+    return reinterpret_cast< T* >(&const_cast< opaque_type& >(reinterpret_cast< const volatile opaque_type& >(value)));
+}
+
 template< typename To, typename From >
 BOOST_FORCEINLINE To bitwise_cast(From const& from) BOOST_NOEXCEPT
 {
@@ -39,8 +50,8 @@ BOOST_FORCEINLINE To bitwise_cast(From const& from) BOOST_NOEXCEPT
     value = {};
     BOOST_ATOMIC_DETAIL_MEMCPY
     (
-        &reinterpret_cast< char& >(value.to),
-        &reinterpret_cast< const char& >(from),
+        atomics::detail::addressof(value.to),
+        atomics::detail::addressof(from),
         (sizeof(From) < sizeof(To) ? sizeof(From) : sizeof(To))
     );
     return value.to;

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/caps_gcc_x86.hpp

@@ -22,6 +22,8 @@
 #pragma once
 #endif
 
+#if defined(__GNUC__)
+
 #if defined(__i386__) &&\
     (\
         defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8) ||\
@@ -35,6 +37,27 @@
 #define BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG16B 1
 #endif
 
+#if defined(__x86_64__) || defined(__SSE2__)
+// Use mfence only if SSE2 is available
+#define BOOST_ATOMIC_DETAIL_X86_HAS_MFENCE 1
+#endif
+
+#else // defined(__GNUC__)
+
+#if defined(__i386__) && !defined(BOOST_ATOMIC_NO_CMPXCHG8B)
+#define BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG8B 1
+#endif
+
+#if defined(__x86_64__) && !defined(BOOST_ATOMIC_NO_CMPXCHG16B)
+#define BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG16B 1
+#endif
+
+#if !defined(BOOST_ATOMIC_NO_MFENCE)
+#define BOOST_ATOMIC_DETAIL_X86_HAS_MFENCE 1
+#endif
+
+#endif // defined(__GNUC__)
+
 #define BOOST_ATOMIC_INT8_LOCK_FREE 2
 #define BOOST_ATOMIC_INT16_LOCK_FREE 2
 #define BOOST_ATOMIC_INT32_LOCK_FREE 2

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/caps_msvc_x86.hpp

@@ -30,6 +30,11 @@
 #define BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG16B 1
 #endif
 
+#if defined(_MSC_VER) && (defined(_M_AMD64) || (defined(_M_IX86) && defined(_M_IX86_FP) && _M_IX86_FP >= 2))
+// Use mfence only if SSE2 is available
+#define BOOST_ATOMIC_DETAIL_X86_HAS_MFENCE 1
+#endif
+
 #define BOOST_ATOMIC_INT8_LOCK_FREE 2
 #define BOOST_ATOMIC_INT16_LOCK_FREE 2
 #define BOOST_ATOMIC_INT32_LOCK_FREE 2

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/config.hpp

@@ -60,14 +60,15 @@
 #define BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA
 #endif
 
-#if (defined(macintosh) || defined(__APPLE__) || defined(__APPLE_CC__)) && (defined(__GNUC__) && (__GNUC__ * 100 + __GNUC_MINOR__) < 403)
+#if ((defined(macintosh) || defined(__APPLE__) || defined(__APPLE_CC__)) && (defined(__GNUC__) && (__GNUC__ * 100 + __GNUC_MINOR__) < 403)) ||\
+    defined(__SUNPRO_CC)
 // This macro indicates we're using older binutils that don't support implied zero displacements for memory opereands,
 // making code like this invalid:
 //   movl 4+(%%edx), %%eax
 #define BOOST_ATOMIC_DETAIL_NO_ASM_IMPLIED_ZERO_DISPLACEMENTS
 #endif
 
-#if defined(__clang__) || (defined(BOOST_GCC) && (BOOST_GCC+0) < 40500)
+#if defined(__clang__) || (defined(BOOST_GCC) && (BOOST_GCC+0) < 40500) || defined(__SUNPRO_CC)
 // This macro indicates that the compiler does not support allocating rax:rdx register pairs ("A") in asm blocks
 #define BOOST_ATOMIC_DETAIL_NO_ASM_RAX_RDX_PAIRS
 #endif

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/interlocked.hpp

@@ -169,7 +169,7 @@ extern "C" long __cdecl _InterlockedExchange( long volatile *, long );
 
 #endif
 
-#if _MSC_VER >= 1700 && defined(_M_ARM)
+#if _MSC_VER >= 1700 && (defined(_M_ARM) || defined(_M_ARM64))
 
 #if defined(BOOST_MSVC)
 #pragma intrinsic(_InterlockedExchangeAdd64)
@@ -251,10 +251,17 @@ extern "C" long __cdecl _InterlockedExchange( long volatile *, long );
 #define BOOST_ATOMIC_INTERLOCKED_EXCHANGE_ADD64_ACQUIRE(dest, addend) _InterlockedExchangeAdd64_acq((__int64*)(dest), (__int64)(addend))
 #define BOOST_ATOMIC_INTERLOCKED_EXCHANGE_ADD64_RELEASE(dest, addend) _InterlockedExchangeAdd64_rel((__int64*)(dest), (__int64)(addend))
 
+#if defined(_M_ARM64)
+#define BOOST_ATOMIC_INTERLOCKED_EXCHANGE_ADD_POINTER(dest, byte_offset) ((void*)BOOST_ATOMIC_INTERLOCKED_EXCHANGE_ADD64((__int64*)(dest), byte_offset))
+#define BOOST_ATOMIC_INTERLOCKED_EXCHANGE_ADD_POINTER_RELAXED(dest, byte_offset) ((void*)BOOST_ATOMIC_INTERLOCKED_EXCHANGE_ADD64_RELAXED((__int64*)(dest), byte_offset))
+#define BOOST_ATOMIC_INTERLOCKED_EXCHANGE_ADD_POINTER_ACQUIRE(dest, byte_offset) ((void*)BOOST_ATOMIC_INTERLOCKED_EXCHANGE_ADD64_ACQUIRE((__int64*)(dest), byte_offset))
+#define BOOST_ATOMIC_INTERLOCKED_EXCHANGE_ADD_POINTER_RELEASE(dest, byte_offset) ((void*)BOOST_ATOMIC_INTERLOCKED_EXCHANGE_ADD64_RELEASE((__int64*)(dest), byte_offset))
+#else
 #define BOOST_ATOMIC_INTERLOCKED_EXCHANGE_ADD_POINTER(dest, byte_offset) ((void*)BOOST_ATOMIC_INTERLOCKED_EXCHANGE_ADD((long*)(dest), byte_offset))
 #define BOOST_ATOMIC_INTERLOCKED_EXCHANGE_ADD_POINTER_RELAXED(dest, byte_offset) ((void*)BOOST_ATOMIC_INTERLOCKED_EXCHANGE_ADD_RELAXED((long*)(dest), byte_offset))
 #define BOOST_ATOMIC_INTERLOCKED_EXCHANGE_ADD_POINTER_ACQUIRE(dest, byte_offset) ((void*)BOOST_ATOMIC_INTERLOCKED_EXCHANGE_ADD_ACQUIRE((long*)(dest), byte_offset))
 #define BOOST_ATOMIC_INTERLOCKED_EXCHANGE_ADD_POINTER_RELEASE(dest, byte_offset) ((void*)BOOST_ATOMIC_INTERLOCKED_EXCHANGE_ADD_RELEASE((long*)(dest), byte_offset))
+#endif
 
 #if defined(BOOST_MSVC)
 #pragma intrinsic(_InterlockedExchange8_nf)

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/ops_emulated.hpp

@@ -35,6 +35,8 @@ struct emulated_operations
 {
     typedef T storage_type;
 
+    static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = false;
+
     static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
     {
         lockpool::scoped_lock lock(&storage);
@@ -89,7 +91,7 @@ struct emulated_operations
     }
 
     static BOOST_FORCEINLINE bool compare_exchange_weak(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order, memory_order) BOOST_NOEXCEPT
     {
         // Note: This function is the exact copy of compare_exchange_strong. The reason we're not just forwarding the call
         // is that MSVC-12 ICEs in this case.

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/ops_gcc_alpha.hpp

@@ -63,6 +63,8 @@ namespace detail {
 
 struct gcc_alpha_operations_base
 {
+    static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = true;
+
     static BOOST_FORCEINLINE void fence_before(memory_order order) BOOST_NOEXCEPT
     {
         if ((order & memory_order_release) != 0)

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/ops_gcc_arm.hpp

@@ -100,6 +100,8 @@ namespace detail {
 
 struct gcc_arm_operations_base
 {
+    static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = true;
+
     static BOOST_FORCEINLINE void fence_before(memory_order order) BOOST_NOEXCEPT
     {
         if ((order & memory_order_release) != 0)

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/ops_gcc_atomic.hpp

@@ -85,6 +85,11 @@ struct gcc_atomic_operations
 {
     typedef T storage_type;
 
+    // Note: In the current implementation, gcc_atomic_operations are used onlu when the particularly sized __atomic
+    // intrinsics are always lock-free (i.e. the corresponding LOCK_FREE macro is 2). Therefore it is safe to
+    // always set is_always_lock_free to true here.
+    static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = true;
+
     static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
         __atomic_store_n(&storage, v, atomics::detail::convert_memory_order_to_gcc(order));

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/ops_gcc_ppc.hpp

@@ -85,6 +85,8 @@ namespace detail {
 
 struct gcc_ppc_operations_base
 {
+    static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = true;
+
     static BOOST_FORCEINLINE void fence_before(memory_order order) BOOST_NOEXCEPT
     {
 #if defined(__powerpc64__) || defined(__PPC64__)

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/ops_gcc_sparc.hpp

@@ -34,6 +34,8 @@ namespace detail {
 
 struct gcc_sparc_cas_base
 {
+    static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = true;
+
     static BOOST_FORCEINLINE void fence_before(memory_order order) BOOST_NOEXCEPT
     {
         if (order == memory_order_seq_cst)
@@ -66,7 +68,7 @@ struct gcc_sparc_cas32 :
 
     static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        fence_before_store(order);
+        fence_before(order);
         storage = v;
         fence_after_store(order);
     }
@@ -107,7 +109,7 @@ struct gcc_sparc_cas32 :
 
     static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        base_type::fence_before(order);
+        fence_before(order);
         __asm__ __volatile__
         (
             "swap [%1], %0"
@@ -115,7 +117,7 @@ struct gcc_sparc_cas32 :
             : "r" (&storage)
             : "memory"
         );
-        base_type::fence_after(order);
+        fence_after(order);
         return v;
     }
 
@@ -152,7 +154,7 @@ struct gcc_sparc_cas64 :
 
     static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        fence_before_store(order);
+        fence_before(order);
         storage = v;
         fence_after_store(order);
     }

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/ops_gcc_sync.hpp

@@ -33,6 +33,8 @@ namespace detail {
 
 struct gcc_sync_operations_base
 {
+    static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = true;
+
     static BOOST_FORCEINLINE void fence_before_store(memory_order order) BOOST_NOEXCEPT
     {
         if ((order & memory_order_release) != 0)

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/ops_gcc_x86.hpp

@@ -42,6 +42,8 @@ namespace detail {
 
 struct gcc_x86_operations_base
 {
+    static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = true;
+
     static BOOST_FORCEINLINE void fence_before(memory_order order) BOOST_NOEXCEPT
     {
         if ((order & memory_order_release) != 0)
@@ -485,7 +487,7 @@ BOOST_FORCEINLINE void thread_fence(memory_order order) BOOST_NOEXCEPT
     {
         __asm__ __volatile__
         (
-#if defined(__x86_64__) || defined(__SSE2__)
+#if defined(BOOST_ATOMIC_DETAIL_X86_HAS_MFENCE)
             "mfence\n"
 #else
             "lock; addl $0, (%%esp)\n"

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/ops_gcc_x86_dcas.hpp

@@ -38,6 +38,8 @@ struct gcc_dcas_x86
     typedef typename make_storage_type< 8u, Signed >::type storage_type;
     typedef typename make_storage_type< 8u, Signed >::aligned aligned_storage_type;
 
+    static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = true;
+
     static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
     {
         if ((((uint32_t)&storage) & 0x00000007) == 0)
@@ -71,6 +73,7 @@ struct gcc_dcas_x86
         {
 #if !defined(BOOST_ATOMIC_DETAIL_NO_ASM_IMPLIED_ZERO_DISPLACEMENTS)
 #if defined(__PIC__)
+            uint32_t v_lo = (uint32_t)v;
             uint32_t scratch;
             __asm__ __volatile__
             (
@@ -82,8 +85,8 @@ struct gcc_dcas_x86
                 "1: lock; cmpxchg8b %[dest]\n\t"
                 "jne 1b\n\t"
                 "movl %[scratch], %%ebx\n\t"
-                : [scratch] "=m" (scratch), [dest] "=o" (storage)
-                : [value_lo] "a" ((uint32_t)v), "c" ((uint32_t)(v >> 32))
+                : [scratch] "=m" (scratch), [dest] "=o" (storage), [value_lo] "+a" (v_lo)
+                : "c" ((uint32_t)(v >> 32))
                 : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "edx", "memory"
             );
 #else // defined(__PIC__)
@@ -101,6 +104,7 @@ struct gcc_dcas_x86
 #endif // defined(__PIC__)
 #else // !defined(BOOST_ATOMIC_DETAIL_NO_ASM_IMPLIED_ZERO_DISPLACEMENTS)
 #if defined(__PIC__)
+            uint32_t v_lo = (uint32_t)v;
             uint32_t scratch;
             __asm__ __volatile__
             (
@@ -113,11 +117,11 @@ struct gcc_dcas_x86
                 "jne 1b\n\t"
                 "movl %[scratch], %%ebx\n\t"
 #if !defined(BOOST_ATOMIC_DETAIL_NO_ASM_CONSTRAINT_ALTERNATIVES)
-                : [scratch] "=m,m" (scratch)
-                : [value_lo] "a,a" ((uint32_t)v), "c,c" ((uint32_t)(v >> 32)), [dest] "D,S" (&storage)
+                : [scratch] "=m,m" (scratch), [value_lo] "+a,a" (v_lo)
+                : "c,c" ((uint32_t)(v >> 32)), [dest] "D,S" (&storage)
 #else
-                : [scratch] "=m" (scratch)
-                : [value_lo] "a" ((uint32_t)v), "c" ((uint32_t)(v >> 32)), [dest] "D" (&storage)
+                : [scratch] "=m" (scratch), [value_lo] "+a" (v_lo)
+                : "c" ((uint32_t)(v >> 32)), [dest] "D" (&storage)
 #endif
                 : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "edx", "memory"
             );
@@ -367,9 +371,12 @@ struct gcc_dcas_x86_64
     typedef typename make_storage_type< 16u, Signed >::type storage_type;
     typedef typename make_storage_type< 16u, Signed >::aligned aligned_storage_type;
 
+    static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = true;
+
     static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
     {
         uint64_t const* p_value = (uint64_t const*)&v;
+        const uint64_t v_lo = p_value[0], v_hi = p_value[1];
 #if !defined(BOOST_ATOMIC_DETAIL_NO_ASM_IMPLIED_ZERO_DISPLACEMENTS)
         __asm__ __volatile__
         (
@@ -379,7 +386,7 @@ struct gcc_dcas_x86_64
             "1: lock; cmpxchg16b %[dest]\n\t"
             "jne 1b\n\t"
             : [dest] "=o" (storage)
-            : "b" (p_value[0]), "c" (p_value[1])
+            : "b" (v_lo), "c" (v_hi)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "rax", "rdx", "memory"
         );
 #else // !defined(BOOST_ATOMIC_DETAIL_NO_ASM_IMPLIED_ZERO_DISPLACEMENTS)
@@ -391,7 +398,7 @@ struct gcc_dcas_x86_64
             "1: lock; cmpxchg16b 0(%[dest])\n\t"
             "jne 1b\n\t"
             :
-            : "b" (p_value[0]), "c" (p_value[1]), [dest] "r" (&storage)
+            : "b" (v_lo), "c" (v_hi), [dest] "r" (&storage)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "rax", "rdx", "memory"
         );
 #endif // !defined(BOOST_ATOMIC_DETAIL_NO_ASM_IMPLIED_ZERO_DISPLACEMENTS)
@@ -466,6 +473,7 @@ struct gcc_dcas_x86_64
 #elif defined(BOOST_ATOMIC_DETAIL_NO_ASM_RAX_RDX_PAIRS)
         // GCC 4.4 can't allocate rax:rdx register pair either but it also doesn't support 128-bit __sync_val_compare_and_swap
         uint64_t const* p_desired = (uint64_t const*)&desired;
+        const uint64_t desired_lo = p_desired[0], desired_hi = p_desired[1];
         bool success;
 #if !defined(BOOST_ATOMIC_DETAIL_NO_ASM_IMPLIED_ZERO_DISPLACEMENTS)
         __asm__ __volatile__
@@ -477,7 +485,7 @@ struct gcc_dcas_x86_64
             "movq %%rax, %[expected]\n\t"
             "movq %%rdx, 8+%[expected]\n\t"
             : [dest] "+m" (storage), [expected] "+o" (expected), [success] "=q" (success)
-            : "b" (p_desired[0]), "c" (p_desired[1])
+            : "b" (desired_lo), "c" (desired_hi)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory", "rax", "rdx"
         );
 #else // !defined(BOOST_ATOMIC_DETAIL_NO_ASM_IMPLIED_ZERO_DISPLACEMENTS)
@@ -490,7 +498,7 @@ struct gcc_dcas_x86_64
             "movq %%rax, 0(%[expected])\n\t"
             "movq %%rdx, 8(%[expected])\n\t"
             : [dest] "+m" (storage), [success] "=q" (success)
-            : "b" (p_desired[0]), "c" (p_desired[1]), [expected] "r" (&expected)
+            : "b" (desired_lo), "c" (desired_hi), [expected] "r" (&expected)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory", "rax", "rdx"
         );
 #endif // !defined(BOOST_ATOMIC_DETAIL_NO_ASM_IMPLIED_ZERO_DISPLACEMENTS)
@@ -498,6 +506,7 @@ struct gcc_dcas_x86_64
         return success;
 #else // defined(BOOST_ATOMIC_DETAIL_NO_ASM_RAX_RDX_PAIRS)
         uint64_t const* p_desired = (uint64_t const*)&desired;
+        const uint64_t desired_lo = p_desired[0], desired_hi = p_desired[1];
         bool success;
         __asm__ __volatile__
         (
@@ -505,10 +514,10 @@ struct gcc_dcas_x86_64
             "sete %[success]\n\t"
 #if !defined(BOOST_ATOMIC_DETAIL_NO_ASM_CONSTRAINT_ALTERNATIVES)
             : "+A,A" (expected), [dest] "+m,m" (storage), [success] "=q,m" (success)
-            : "b,b" (p_desired[0]), "c,c" (p_desired[1])
+            : "b,b" (desired_lo), "c,c" (desired_hi)
 #else
             : "+A" (expected), [dest] "+m" (storage), [success] "=q" (success)
-            : "b" (p_desired[0]), "c" (p_desired[1])
+            : "b" (desired_lo), "c" (desired_hi)
 #endif
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
         );
@@ -522,7 +531,7 @@ struct gcc_dcas_x86_64
         return compare_exchange_strong(storage, expected, desired, success_order, failure_order);
     }
 
-    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
     {
 #if defined(__clang__)
         // Clang cannot allocate eax:edx register pairs but it has sync intrinsics
@@ -538,6 +547,7 @@ struct gcc_dcas_x86_64
         // GCC 4.4 can't allocate rax:rdx register pair either but it also doesn't support 128-bit __sync_val_compare_and_swap
         storage_type old_value;
         uint64_t const* p_value = (uint64_t const*)&v;
+        const uint64_t v_lo = p_value[0], v_hi = p_value[1];
 #if !defined(BOOST_ATOMIC_DETAIL_NO_ASM_IMPLIED_ZERO_DISPLACEMENTS)
         __asm__ __volatile__
         (
@@ -549,7 +559,7 @@ struct gcc_dcas_x86_64
             "movq %%rax, %[old_value]\n\t"
             "movq %%rdx, 8+%[old_value]\n\t"
             : [dest] "+o" (storage), [old_value] "=o" (old_value)
-            : "b" (p_value[0]), "c" (p_value[1])
+            : "b" (v_lo), "c" (v_hi)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory", "rax", "rdx"
         );
 #else // !defined(BOOST_ATOMIC_DETAIL_NO_ASM_IMPLIED_ZERO_DISPLACEMENTS)
@@ -563,7 +573,7 @@ struct gcc_dcas_x86_64
             "movq %%rax, 0(%[old_value])\n\t"
             "movq %%rdx, 8(%[old_value])\n\t"
             :
-            : "b" (p_value[0]), "c" (p_value[1]), [dest] "r" (&storage), [old_value] "r" (&old_value)
+            : "b" (v_lo), "c" (v_hi), [dest] "r" (&storage), [old_value] "r" (&old_value)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory", "rax", "rdx"
         );
 #endif // !defined(BOOST_ATOMIC_DETAIL_NO_ASM_IMPLIED_ZERO_DISPLACEMENTS)
@@ -571,6 +581,7 @@ struct gcc_dcas_x86_64
         return old_value;
 #else // defined(BOOST_ATOMIC_DETAIL_NO_ASM_RAX_RDX_PAIRS)
         uint64_t const* p_value = (uint64_t const*)&v;
+        const uint64_t v_lo = p_value[0], v_hi = p_value[1];
 #if !defined(BOOST_ATOMIC_DETAIL_NO_ASM_IMPLIED_ZERO_DISPLACEMENTS)
         __asm__ __volatile__
         (
@@ -580,7 +591,7 @@ struct gcc_dcas_x86_64
             "1: lock; cmpxchg16b %[dest]\n\t"
             "jne 1b\n\t"
             : "=&A" (v), [dest] "+o" (storage)
-            : "b" (p_value[0]), "c" (p_value[1])
+            : "b" (v_lo), "c" (v_hi)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
         );
 #else // !defined(BOOST_ATOMIC_DETAIL_NO_ASM_IMPLIED_ZERO_DISPLACEMENTS)
@@ -592,7 +603,7 @@ struct gcc_dcas_x86_64
             "1: lock; cmpxchg16b 0(%[dest])\n\t"
             "jne 1b\n\t"
             : "=&A" (v)
-            : "b" (p_value[0]), "c" (p_value[1]), [dest] "r" (&storage)
+            : "b" (v_lo), "c" (v_hi), [dest] "r" (&storage)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
         );
 #endif // !defined(BOOST_ATOMIC_DETAIL_NO_ASM_IMPLIED_ZERO_DISPLACEMENTS)