origen_sim 0.5.5 → 0.6.0

data/lib/origen_sim_dev/dut.rb

@@ -16,11 +16,12 @@ module OrigenSimDev
       add_pin :trstn, reset: :drive_lo
       add_pin_alias :tclk, :tck
       add_pin :dout, size: 32
+      add_pin :test_bus, size: 16
       add_pin :din_port, size: 32, rtl_name: 'din', reset: :drive_lo
-      add_pin :p1, tie_off: 0
-      add_pin :p2, tie_off: 1
-      add_pin :p3, size: 4, tie_off: 0
-      add_pin :p4, size: 4, tie_off: 1
+      add_pin :p1, force: 0
+      add_pin :p2, force: 1
+      add_pin :p3, size: 4, force: 0
+      add_pin :p4, size: 4, force: 0xA
       add_pin :v1, rtl_name: 'nc'
       add_pin :v2, rtl_name: :nc
 
@@ -68,6 +69,7 @@ module OrigenSimDev
     end
 
     def startup(options = {})
+      # tester.simulator.log_messages = true
       tester.set_timeset('func', 100)
 
       dut.pin(:rstn).drive!(1)

data/pattern/test.rb

@@ -34,27 +34,32 @@ Pattern.create do
   dut.cmd.write!(0x1234_5678)
   dut.cmd.read!(0x1234_5678)
 
-  tester.simulator.poke("dut.cmd", 0x1122_3344)
-  dut.cmd.read!(0x1122_3344)
+  if tester.sim?
+    tester.simulator.poke("dut.cmd", 0x1122_3344)
+    dut.cmd.read!(0x1122_3344)
+  end
 
   ss "Test storing a register"
   dut.cmd.write!(0x2244_6688)
   dut.cmd.store!
 
-  capture_value = tester.simulator.peek("origen.pins.tdo.memory")
-  unless capture_value == 0x11662244 # 0x2244_6688 reversed
-    if capture_value
-      fail "Captured #{capture_value.to_hex} instead of 0x11662244!"
-    else
-      fail "Nothing captured instead of 0x11662244!"
+  if tester.sim?
+    sim = tester.simulator
+    capture_value = sim.peek("origen.pins.tdo.memory").to_i
+    unless capture_value == 0x11662244 # 0x2244_6688 reversed
+      if capture_value
+        fail "Captured #{capture_value.to_hex} instead of 0x11662244!"
+      else
+        fail "Nothing captured instead of 0x11662244!"
+      end
     end
-  end
 
-  ss "Test sync of a register"
-  dut.cmd.write(0) # Make Origen forget the actual value
-  dut.cmd.sync
-  unless dut.cmd.data == 0x2244_6688
-    fail "CMD register did not sync from simulation"
+    ss "Test sync of a register"
+    dut.cmd.write(0) # Make Origen forget the actual value
+    dut.cmd.sync
+    unless dut.cmd.data == 0x2244_6688
+      fail "CMD register did not sync from simulation"
+    end
   end
 
   ss "Do some operations with the counter, just for fun"
@@ -76,9 +81,16 @@ Pattern.create do
   dut.pins(:dout).assert!(0x5555_AAAA)
   dut.pins(:dout).dont_care
 
-  ss "Verify that tying off pins works"
+  ss "Verify that forcing pins works"
   dut.p.p1.assert!(0)
   dut.p.p2.assert!(1)
   dut.p.p3.assert!(0)
-  dut.p.p4.assert!(0xF)
+  dut.p.p4.assert!(0xA)
+
+  ss "Test sim_capture"
+  tester.sim_capture :cmd55, :dout, :test_bus, :tdo do
+    dut.pins(:din_port).drive!(0x1234_5678)
+    dut.cmd.write!(0x55)
+    60.cycles
+  end
 end

data/templates/empty.gtkw

@@ -0,0 +1,26 @@
+[*]
+[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
+[*] Thu Jan 11 09:12:49 2018
+[*]
+[dumpfile] "/home/stephen/Code/github/origen_sim/waves/default/origen.vcd"
+[dumpfile_mtime] "Wed Jan 10 17:49:53 2018"
+[dumpfile_size] 411132
+[savefile] "/home/stephen/Code/github/origen_sim/templates/empty.gtkw"
+[timestart] 0
+[size] 2308 1127
+[pos] -1 -1
+*-25.716982 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] origen.
+[treeopen] origen.debug.
+[treeopen] origen.dut.
+[sst_width] 225
+[signals_width] 158
+[sst_expanded] 1
+[sst_vpaned_height] 337
+@820
+origen.debug.pattern[1023:0]
+origen.debug.comments[1023:0]
+@22
+origen.debug.errors[31:0]
+[pattern_trace] 1
+[pattern_trace] 0

data/templates/rtl_v/origen.v.erb

@@ -63,18 +63,14 @@ module pin_driver(error, pin, sync);
 
 endmodule
 
-module pin_drivers(errors, <%= dut.rtl_pins.map { |n, p, o| "#{p.id}_o" unless p.tie_off }.compact.join(', ') %>);
+module pin_drivers(errors, <%= dut.rtl_pins.map { |n, p, o| "#{p.id}_o" }.join(', ') %>);
 
 % dut.rtl_pins.each do |name, pin, options|
-%   unless pin.tie_off
   output <%= pin.id %>_o;
-%   end
 % end
 
 % dut.rtl_pins.each do |name, pin, options|
-%   unless pin.tie_off
   wire <%= pin.id %>_err;
-%   end
 % end
 
   output reg [31:0] errors = 0;
@@ -83,12 +79,10 @@ module pin_drivers(errors, <%= dut.rtl_pins.map { |n, p, o| "#{p.id}_o" unless p
   always @(
 
 % dut.rtl_pins.each_with_index do |(name, pin, options), i|
-%   unless pin.tie_off
-%     if i == 0
+%   if i == 0
     posedge <%= pin.id %>_err
-%     else
+%   else
     or posedge <%= pin.id %>_err
-%     end
 %   end
 % end
   ) begin
@@ -96,9 +90,7 @@ module pin_drivers(errors, <%= dut.rtl_pins.map { |n, p, o| "#{p.id}_o" unless p
   end
 
 % dut.rtl_pins.each do |name, pin, options|
-%   unless pin.tie_off
   pin_driver <%= pin.driving? ? "#(#{pin.value}) " : '' %><%= pin.id %>(.pin(<%= pin.id %>_o), .error(<%= pin.id %>_err), .sync(sync));
-%   end 
 % end
 
 endmodule
@@ -120,68 +112,37 @@ module origen;
   reg finish = 0;
 
 % dut.rtl_pins.each do |name, pin, options|
-%   unless pin.tie_off
   wire <%= pin.id %>;
-%   end
 % end
 
   wire [31:0] errors;
 
   pin_drivers pins (
 % dut.rtl_pins.each_with_index do |(name, pin, options), i|
-%   unless pin.tie_off
     .<%= pin.id %>_o(<%= pin.id %>),
-%   end
 % end
     .errors(errors)
   );
 
-  // Create wires to tie off DUT signals, initially this was done by hardcoded values when instantiating
-  // below, however the simulator didn't like that if the target pin was defined as an inout
-% dut.rtl_pins.each do |name, pin, options|
-%   if options[:group]
-%     if pin.group_index == 0
-%       if pin.primary_group.tie_off
-  wire [<%= pin.primary_group.size - 1 %>:0] <%= pin.rtl_name %>;
-  assign <%= pin.rtl_name %> = <%= "#{pin.primary_group.size}'b#{pin.tie_off.to_s * pin.primary_group.size}" %>;
-%       end
-%     end
-%   else
-%     if pin.tie_off
-  wire <%= pin.rtl_name %>;
-  assign <%= pin.rtl_name %> = 1'b<%= pin.tie_off %>;
-%     end
-%   end
-% end
-
-
   // Instantiate the DUT
   <%= options[:top].sub(/\..*/, '') %> dut (
 % dut.power_pins.each do |name, pin, options|
-%   unless pin.tie_off
     .<%= pin.id %>(<%= pin.id %>),
-%   end
 % end
 % dut.ground_pins.each do |name, pin, options|
-%   unless pin.tie_off
     .<%= pin.id %>(<%= pin.id %>),
-%   end
 % end
 % dut.rtl_pins.each_with_index do |(name, pin, options), i|
 %   if options[:group]
 %     if pin.group_index == 0
-%       if pin.primary_group.tie_off
-    .<%= pin.rtl_name %>(<%= pin.rtl_name %>)<%= i == (dut.rtl_pins.size - 1) ? '' : ',' %>
-%       else
-    .<%= pin.rtl_name %>({
-%         pin.primary_group.each_with_index do |pin, i|
+    .<%= pin.primary_group.id %>({
+%       pin.primary_group.each_with_index do |pin, i|
       <%= pin.id %><%= i == (pin.primary_group.size - 1) ? '' : ',' %>
-%         end
-    })<%= i == (dut.rtl_pins.size - 1) ? '' : ',' %>
 %       end
+    })<%= i == (dut.rtl_pins.size - 1) ? '' : ',' %>
 %     end
 %   else
-    .<%= pin.rtl_name %>(<%= pin.tie_off ? pin.rtl_name : pin.id %>)<%= i == (dut.rtl_pins.size - 1) ? '' : ',' %>
+    .<%= pin.rtl_name %>(<%= pin.id %>)<%= i == (dut.rtl_pins.size - 1) ? '' : ',' %>
 %   end
 % end
   );
@@ -190,13 +151,13 @@ module origen;
     .errors(errors)
   );
 
-% if options[:vendor] == :icarus  
+`ifdef ICARUS 
   initial
   begin
-    $dumpfile("dut.vcd");
+    $dumpfile("origen.vcd");
     $dumpvars(0,origen);
   end
-% end
+`endif
     
   always @(posedge finish) begin
     $finish(2);

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: origen_sim
 version: !ruby/object:Gem::Version
-  version: 0.5.5
+  version: 0.6.0
 platform: ruby
 authors:
 - Stephen McGinty
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2017-12-07 00:00:00.000000000 Z
+date: 2018-01-19 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: origen
@@ -16,14 +16,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: '0.12'
+        version: '0.29'
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: '0.12'
+        version: '0.29'
 - !ruby/object:Gem::Dependency
   name: origen_testers
   requirement: !ruby/object:Gem::Requirement
@@ -38,6 +38,20 @@ dependencies:
     - - ">="
       - !ruby/object:Gem::Version
         version: '0'
+- !ruby/object:Gem::Dependency
+  name: origen_verilog
+  requirement: !ruby/object:Gem::Requirement
+    requirements:
+    - - ">="
+      - !ruby/object:Gem::Version
+        version: '0.3'
+  type: :runtime
+  prerelease: false
+  version_requirements: !ruby/object:Gem::Requirement
+    requirements:
+    - - ">="
+      - !ruby/object:Gem::Version
+        version: '0.3'
 description: 
 email:
 - stephen.f.mcginty@gmail.com
@@ -48,19 +62,22 @@ files:
 - config/application.rb
 - config/boot.rb
 - config/commands.rb
+- config/global_commands.rb
 - config/shared_commands.rb
 - config/version.rb
-- ext/README.md
 - ext/bridge.c
 - ext/bridge.h
 - ext/client.c
 - ext/client.h
 - ext/common.h
+- ext/defines.h.erb
 - ext/origen.c
 - ext/origen.h
 - ext/vpi_user.h
 - lib/origen_sim.rb
 - lib/origen_sim/commands/build.rb
+- lib/origen_sim/commands/ci.rb
+- lib/origen_sim/commands/co.rb
 - lib/origen_sim/flow.rb
 - lib/origen_sim/generator.rb
 - lib/origen_sim/origen/pins/pin.rb
@@ -72,6 +89,7 @@ files:
 - lib/tasks/origen_sim.rake
 - pattern/test.rb
 - program/p1.rb
+- templates/empty.gtkw
 - templates/empty.svcf
 - templates/probe.tcl.erb
 - templates/rtl_v/origen.v.erb
@@ -98,7 +116,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
       version: 1.8.11
 requirements: []
 rubyforge_project: 
-rubygems_version: 2.6.7
+rubygems_version: 2.6.8
 signing_key: 
 specification_version: 4
 summary: Plugin that provides a testbench environment to simulate Origen test patterns

data/ext/README.md

@@ -1,2 +0,0 @@
-This C library gets included into the Verilog testbench and controls the simulation based on instructions
-from Ruby.