origen_sim 0.5.5 → 0.6.0

checksums.yaml

@@ -1,7 +1,7 @@
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+  data.tar.gz: 6df912a7d278020ba64bda1d203fc3efd7f5d5a1
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data/config/application.rb

@@ -1,5 +1,6 @@
 require 'origen'
 class OrigenSimApplication < Origen::Application
+  attr_accessor :update_sim_captures
 
   # See http://origen-sdk.org/origen/api/Origen/Application/Configuration.html
   # for a full list of the configuration options available
@@ -27,9 +28,19 @@ class OrigenSimApplication < Origen::Application
     #:patterns => "pattern",
     #:templates => "templates",
     #:programs => "program",
-    :command_launcher => "config/shared_commands.rb"
+    :command_launcher => "config/shared_commands.rb",
+    :global_launcher => "config/global_commands.rb"
   }
 
+  config.remotes = [
+    {
+      dir: "example_rtl",
+      rc_url: 'https://github.com/Origen-SDK/example_rtl.git',
+      version: "master",
+      development: true
+    }
+  ]
+
   # See: http://origen-sdk.org/origen/latest/guides/utilities/lint/
   config.lint_test = {
     # Require the lint tests to pass before allowing a release to proceed

data/config/commands.rb

@@ -15,11 +15,34 @@ case @command
 
 # Here is an example of how to implement a command, the logic can go straight
 # in here or you can require an external file if preferred.
-when "my_command"
-  puts "Doing something..."
-  #require "commands/my_command"    # Would load file lib/commands/my_command.rb
-  # You must always exit upon successfully capturing a command to prevent 
-  # control flowing back to Origen
+when "sim:build_example"
+  Dir.chdir(Origen.root) do
+    output = `origen sim:build  #{Origen.app.remotes_dir}/example_rtl/dut1/dut1.v`
+    puts output
+    Origen.load_target
+    FileUtils.mkdir_p "simulation/default/#{tester.simulator.config[:vendor]}"
+    case tester.simulator.config[:vendor]
+    when :icarus
+      output =~ /  (cd .*)\n/
+      system $1
+      FileUtils.mv "#{Origen.config.output_directory}/origen.vpi", "simulation/default/icarus"
+      output =~ /  (iverilog .*)\n/
+      system $1
+      FileUtils.mv "origen.vvp", "simulation/default/icarus"
+
+    when :cadence
+      output =~ /  (irun .*)\n/
+      system = $1
+      FileUtils.mv "INCA_libs", "simulation/default/cadence"
+
+    end
+
+    puts
+    puts "Done, run this command to run a test simulation:"
+    puts
+    puts "  origen g test"
+    puts
+  end
   exit 0
 
 ## Example of how to make a command to run unit tests, this simply invokes RSpec on
@@ -65,10 +88,8 @@ else
   # You probably want to also add the your commands to the help shown via
   # origen -h, you can do this be assigning the required text to @application_commands
   # before handing control back to Origen. Un-comment the example below to get started.
-#  @application_commands = <<-EOT
-# specs        Run the specs (tests), -c will enable coverage
-# examples     Run the examples (tests), -c will enable coverage
-# test         Run both specs and examples, -c will enable coverage
-#  EOT
+  @application_commands = <<-EOT
+ sim:build_example        Build the example simulation object for the current environment setting
+  EOT
 
 end 

data/config/global_commands.rb

@@ -0,0 +1,12 @@
+case @command
+
+when "sim:build", "origen_sim:build"
+  require "#{Origen.root!}/lib/origen_sim/commands/build"
+  exit 0
+
+else
+  @global_commands << <<-EOT
+ sim:build    Build an Origen testbench and simulator extension for a given RTL design
+  EOT
+
+end

data/config/shared_commands.rb

@@ -4,15 +4,22 @@ case @command
 when 'generate'
   $use_fast_probe_depth = false
   @application_options << ["--fast", "Fast simulation, minimum probe depth"]
-  $use_fast_probe_depth = true if ARGV.include?('--fast')
+  $use_fast_probe_depth = ARGV.include?('--fast')
+  @application_options << ["--sim_capture", "Update sim captures (ignored when not running a simulation)"]
+  Origen.app!.update_sim_captures = ARGV.include?('--sim_capture')
 
-when "origen_sim:build", "sim:build"
-  require "origen_sim/commands/build"
+when "sim:ci", "origen_sim:ci"
+  require "#{Origen.root!}/lib/origen_sim/commands/ci"
+  exit 0
+
+when "sim:co", "origen_sim:co"
+  require "#{Origen.root!}/lib/origen_sim/commands/co"
   exit 0
 
 else
   @plugin_commands << <<-EOT
- sim:build       Build the simulation object for the current/given target
+ sim:ci       Checkin a simulation snapshot
+ sim:co       Checkout a simulation snapshot
   EOT
 
 end

data/config/version.rb

@@ -1,7 +1,7 @@
 module OrigenSim
   MAJOR = 0
-  MINOR = 5
-  BUGFIX = 5
+  MINOR = 6
+  BUGFIX = 0
   DEV = nil
 
   VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')

data/ext/bridge.c

@@ -4,6 +4,7 @@
 ///
 #include "bridge.h"
 #include "client.h"
+#include "defines.h"
 #include <stdint.h>
 #include <stdlib.h>
 #include <stdio.h>
@@ -39,7 +40,7 @@ typedef struct Wave {
   int active_pin_count;
 } Wave;
 
-static int period_in_ns;
+static uint64_t period_in_ps;
 static long repeat = 0;
 static Pin pins[MAX_NUMBER_PINS];
 static int number_of_pins = 0;
@@ -261,7 +262,7 @@ static void bridge_clear_waves_and_pins() {
 
 static void bridge_set_period(char * p_in_ns) {
   int p = (int) strtol(p_in_ns, NULL, 10);
-  period_in_ns = p;
+  period_in_ps = p * 1000;
   bridge_clear_waves_and_pins();
 }
 
@@ -472,6 +473,7 @@ PLI_INT32 bridge_apply_wave_event_cb(p_cb_data data) {
 
 /// Registers a callback to apply the given wave during this cycle
 static void bridge_register_wave_event(int wave_ix, int event_ix, int compare, int delay_in_ns) {
+  uint64_t delay_in_ps = delay_in_ns * 1000;
   s_cb_data call;
   s_vpi_time time;
 
@@ -487,8 +489,9 @@ static void bridge_register_wave_event(int wave_ix, int event_ix, int compare, i
   *d2 = compare;
 
   time.type = vpiSimTime;
-  time.high = (uint32_t)(0);
-  time.low  = (uint32_t)(delay_in_ns);
+
+  time.high = (uint32_t)(delay_in_ps >> 32);
+  time.low  = (uint32_t)(delay_in_ps);
 
   call.reason    = cbAfterDelay;
   call.cb_rtn    = bridge_apply_wave_event_cb;
@@ -512,7 +515,7 @@ PLI_INT32 bridge_init() {
 /// When Origen requests a cycle, time will be advanced and this func will be called again.
 PLI_INT32 bridge_wait_for_msg(p_cb_data data) {
   UNUSED(data);
-  int max_msg_len = 100;
+  int max_msg_len = 1024;
   char msg[max_msg_len];
   int err;
   char *opcode, *arg1, *arg2, *arg3, *arg4;
@@ -646,8 +649,10 @@ PLI_INT32 bridge_wait_for_msg(p_cb_data data) {
         arg1 = strtok(NULL, "^");
         handle = vpi_handle_by_name(arg1, NULL);
         if (handle) {
-          v.format = vpiDecStrVal; // Seems important to set this before get
+          //v.format = vpiDecStrVal; // Seems important to set this before get
+          v.format = vpiBinStrVal;
           vpi_get_value(handle, &v);
+          //DEBUG("%s\n", v.value.str);
           sprintf(msg, "%s\n", v.value.str);
           client_put(msg);
         } else {
@@ -726,6 +731,11 @@ PLI_INT32 bridge_wait_for_msg(p_cb_data data) {
         arg1 = strtok(NULL, "^");
         bridge_stop_capture_pin(arg1);
         break;
+      // Get version, returns the version of OrigenSim the DUT object was compiled with
+      //   i^
+      case 'i' :
+        client_put(ORIGEN_SIM_VERSION"\n");
+        break;
       default :
         vpi_printf("ERROR: Illegal message received from Origen: %s\n", orig_msg);
         runtime_errors += 1;
@@ -768,8 +778,8 @@ static void bridge_cycle() {
   s_vpi_time time;
 
   time.type = vpiSimTime;
-  time.high = (uint32_t)(0);
-  time.low  = (uint32_t)(period_in_ns);
+  time.high = (uint32_t)(period_in_ps >> 32);
+  time.low  = (uint32_t)(period_in_ps);
 
   call.reason    = cbAfterDelay;
   call.obj       = 0;

data/ext/client.c

@@ -9,6 +9,7 @@
 #include <sys/un.h>
 #include <unistd.h>
 #include <time.h>
+#include <string.h>
 
 static int sock;
 static uint64_t msg_count = 0;
@@ -62,7 +63,6 @@ bool is_server_alive() {
 /// Send a message to the master Origen process.
 /// NOTE: THE CALLER IS RESPONSIBLE FOR ADDING A \n TERMINATOR TO
 ///       THE MESSAGE
-/// to the data as this function will do it for you.
 int client_put(char* data) {
   if(send(sock, data , strlen(data), 0) < 0) {
     return 1;

data/ext/defines.h.erb

@@ -0,0 +1,6 @@
+#ifndef DEFINES_H
+#define DEFINES_H
+
+#define ORIGEN_SIM_VERSION "<%= OrigenSim::VERSION %>"
+
+#endif

data/ext/origen.c

@@ -110,12 +110,12 @@ static void register_callback(PLI_INT32 aReason, PLI_INT32 (*aHandler)(p_cb_data
 void (*vlog_startup_routines[])(void) = { init, 0 };
 
 #if defined(CVER) || defined(VCS) || defined(NCSIM)
-    void vlog_startup_routines_bootstrap()
+void vlog_startup_routines_bootstrap()
+{
+    unsigned int i;
+    for (i = 0; vlog_startup_routines[i]; i++)
     {
-        unsigned int i;
-        for (i = 0; vlog_startup_routines[i]; i++)
-        {
-            vlog_startup_routines[i]();
-        }
+        vlog_startup_routines[i]();
     }
+}
 #endif

data/lib/origen_sim/commands/build.rb

@@ -1,25 +1,26 @@
 require 'optparse'
 require 'origen_sim'
+require_relative '../../../config/version'
+require 'origen_verilog'
 
-options = {}
+options = { source_dirs: [] }
 
 # App options are options that the application can supply to extend this command
 app_options = @application_options || []
 opt_parser = OptionParser.new do |opts|
   opts.banner = <<-EOT
-Compile an RTL design into an object that Origen can simulate.
+Build an Origen testbench and simulator VPI extension for the given top-level RTL design.
 
-All configuration apart from target selection should be done when instantiating the
-OrigenSim::Tester in an environment file. This encourages the configuration to be
-checked in, enabling repeatable builds in future.
+The created artifacts should be included in a compilation of the given design to create
+an Origen-enabled simulation object that can be used to simulate Origen-based test patterns.
 
-Usage: origen origen_sim:build [options]
+Usage: origen sim:build TOP_LEVEL_RTL_FILE [options]
   EOT
-  opts.on('-e', '--environment NAME', String, 'Override the default environment, NAME can be a full path or a fragment of an environment file name') { |e| options[:environment] = e }
-  opts.on('-t', '--target NAME', String, 'Override the default target, NAME can be a full path or a fragment of a target file name') { |t| options[:target] = t }
-  opts.on('-pl', '--plugin PLUGIN_NAME', String, 'Set current plugin') { |pl_n|  options[:current_plugin] = pl_n }
-  opts.on('--testrun', 'Displays the commands that will be generated but does not execute them') { options[:testrun] = true }
-  opts.on('-i', '--incremental', 'Preserve existing compiled files to do an incremental build instead of starting from scratch') { options[:incremental] = true }
+  opts.on('-o', '--output DIR', String, 'Override the default output directory') { |t| options[:output] = t }
+  opts.on('-t', '--top NAME', String, 'Specify the top-level Verilog module name if OrigenSim can\'t work it out') { |t| options[:top_level_name] = t }
+  opts.on('-s', '--source_dir PATH', 'Directories to look for include files in (the directory containing the top-level is already considered)') do |path|
+    options[:source_dirs] << path
+  end
   opts.on('-d', '--debugger', 'Enable the debugger') {  options[:debugger] = true }
   app_options.each do |app_option|
     opts.on(*app_option) {}
@@ -29,83 +30,120 @@ Usage: origen origen_sim:build [options]
 end
 
 opt_parser.parse! ARGV
-Origen.app.plugins.temporary = options[:current_plugin] if options[:current_plugin]
-Origen.environment.temporary = options[:environment] if options[:environment]
-Origen.target.temporary = options[:target] if options[:target]
-Origen.app.load_target!
-
-unless tester.is_a?(OrigenSim::Tester)
-  puts 'The target/environment does not instantiate an OrigenSim::Tester instance!'
-  exit
+
+unless ARGV.size > 0
+  puts 'You must supply a path to the top-level RTL file'
+  exit 1
+end
+rtl_top = ARGV.first
+unless File.exist?(rtl_top)
+  puts "File does not exist: #{rtl_top}"
+  exit 1
 end
 
-simulator = OrigenSim.simulator
-config = simulator.configuration
-tmp_dir = simulator.tmp_dir
-
-unless options[:testrun]
-  FileUtils.rm_rf(tmp_dir) unless options[:incremental]
-  FileUtils.mkdir_p(tmp_dir)
-  FileUtils.rm_rf(simulator.compiled_dir) unless options[:incremental]
-  FileUtils.mkdir_p(simulator.compiled_dir)
-  FileUtils.rm_rf(simulator.artifacts_dir)
-  FileUtils.mkdir_p(simulator.artifacts_dir)
-  Array(config[:artifacts] || config[:artifact]).each do |f|
-    FileUtils.cp(f, simulator.artifacts_dir)
-  end
+ast = OrigenVerilog.parse_file(rtl_top)
 
-  # Create the testbench for the current Origen target and simulator vendor
-  Origen.app.runner.launch action:            :compile,
-                           files:             "#{Origen.root!}/templates/rtl_v/origen.v.erb",
-                           output:            tmp_dir,
-                           check_for_changes: false,
-                           options:           { vendor: config[:vendor], top: config[:rtl_top], incl: config[:incl_files] }
+unless ast
+  puts 'Sorry, but the given top-level RTL file failed to parse'
+  exit 1
 end
 
-case config[:vendor]
-when :icarus
-  # Compile the VPI extension first
-  Dir.chdir tmp_dir do
-    system "iverilog-vpi #{Origen.root!}/ext/*.c -DICARUS --name=origen"
-    system "mv origen.vpi #{simulator.compiled_dir}"
-  end
-  # Build the object containing the DUT and testbench
-  cmd = "iverilog -o #{simulator.compiled_dir}/dut.vvp"
-  Array(config[:rtl_dir] || config[:rtl_dirs]).each do |dir|
-    cmd += " -I #{dir}"
-  end
-  Array(config[:rtl_file] || config[:rtl_files]).each do |f|
-    cmd += " #{f}"
-  end
-  cmd += " #{tmp_dir}/origen.v"
+candidates = ast.top_level_modules
+candidates = ast.modules if candidates.empty?
 
-when :cadence
-  cmd = config[:irun] || 'irun'
-  Array(config[:rtl_file] || config[:rtl_files]).each do |f|
-    cmd += " #{f}"
-  end
-  Array(config[:lib_file] || config[:lib_files]).each do |f|
-    cmd += " -v #{f}"
-  end
-  Array(config[:rtl_dir] || config[:rtl_dirs]).each do |dir|
-    cmd += " -incdir #{dir}"
+if candidates.size == 0
+  puts "Sorry, couldn't find any Verilog module declarations in that file"
+  exit 1
+elsif candidates.size > 1
+  if options[:top_level_name]
+    mod = candidates.find { |c| c.name == options[:top_level_name] }
   end
-  cmd += " #{tmp_dir}/origen.v"
-  if config[:alt_top]
-    cmd += " -top #{config[:alt_top]}"
-  else
-    cmd += ' -top origen'
+  unless mod
+    puts "Sorry, couldn't work out what the top-level module is, please help by running again and specifying it via the --top switch with one of the following names:"
+    candidates.each do |c|
+      puts "  #{c.name}"
+    end
+    exit 1
   end
-  cmd += ' -timescale 1ns/1ns'
-  cmd += " -nclibdirpath #{simulator.compiled_dir}"
-  cmd += " #{Origen.root!}/ext/*.c -ccargs \"-std=c99\""
-  cmd += ' -elaborate -snapshot origen -access +rw'
-  cmd += " #{config[:explicit].strip.gsub(/\s+/, ' ')}" if  config[:explicit]
+else
+  mod = candidates.first
 end
 
-puts cmd
-unless options[:testrun]
-  Dir.chdir tmp_dir do
-    system cmd
-  end
-end
+rtl_top_module = mod.name
+
+mod.to_top_level # Creates dut
+
+output_directory = options[:output] || Origen.config.output_directory
+
+Origen.app.runner.launch action:            :compile,
+                         files:             "#{Origen.root!}/templates/rtl_v/origen.v.erb",
+                         output:            output_directory,
+                         check_for_changes: false,
+                         quiet:             true,
+                         options:           { vendor: :cadence, top: dut.name, incl: options[:incl_files] }
+
+Origen.app.runner.launch action:            :compile,
+                         files:             "#{Origen.root!}/ext",
+                         output:            output_directory,
+                         check_for_changes: false,
+                         quiet:             true
+
+dut.export(rtl_top_module, file_path: "#{output_directory}")
+
+puts
+puts
+puts 'Testbench and VPI extension created!'
+puts
+puts 'This file can be imported into an Origen top-level DUT model to define the pins:'
+puts
+puts "  #{output_directory}/#{rtl_top_module}.rb"
+puts
+puts 'See below for what to do now to create an Origen-enabled simulation object for your particular simulator:'
+puts
+puts '-----------------------------------------------------------'
+puts 'Cadence Incisive (irun)'
+puts '-----------------------------------------------------------'
+puts
+puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
+puts
+puts "  #{output_directory}/origen.v \\"
+puts "  #{output_directory}/*.c \\"
+puts '  -ccargs "-std=c99" \\'
+puts '  -top origen \\'
+puts '  -elaborate  \\'
+puts '  -snapshot origen \\'
+puts '  -access +rw \\'
+puts '  -timescale 1ns/1ns'
+puts
+puts 'Here is an example which may work for the file you just parsed (add additional -incdir options at the end if required):'
+puts
+puts "  irun #{rtl_top} #{output_directory}/origen.v #{output_directory}/*.c -ccargs \"-std=c99\" -top origen -elaborate -snapshot origen -access +rw -timescale 1ns/1ns -incdir #{Pathname.new(rtl_top).dirname}"
+puts
+puts 'Copy the following directory (produced by irun) to simulation/<target>/cadence/. within your Origen application:'
+puts
+puts '  INCA_libs'
+puts
+puts '-----------------------------------------------------------'
+puts 'Icarus Verilog'
+puts '-----------------------------------------------------------'
+puts
+puts 'Compile the VPI extension using the following command:'
+puts
+puts "  cd #{output_directory} && iverilog-vpi *.c -DICARUS --name=origen && cd #{Pathname.pwd}"
+puts
+puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
+puts
+puts "  #{output_directory}/origen.v \\"
+puts '  -o origen.vvp \\'
+puts '  -DICARUS'
+puts
+puts 'Here is an example which may work for the file you just parsed (add additional source dirs with more -I options at the end if required):'
+puts
+puts "  iverilog #{rtl_top} #{output_directory}/origen.v -o origen.vvp -DICARUS -I #{Pathname.new(rtl_top).dirname}"
+puts
+puts 'Copy the following files to simulation/<target>/icarus/. within your Origen application:'
+puts
+puts "  #{output_directory}/origen.vpi"
+puts '  origen.vvp   (produced by the iverilog command)'
+puts
+puts