origen_arm_debug 0.8.4 → 0.9.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA1:
-  metadata.gz: a4ce85678b97c90ebf41f4dff8b8fad020fe9cfa
-  data.tar.gz: ca74317b6cd30d1145571c337b842351ad401ef8
+  metadata.gz: f4a9f1dc701be4b75209634978ffff6e9c608ea6
+  data.tar.gz: f4ac35a546afb37109a02b46fdd099cdb51c2b74
 SHA512:
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-  data.tar.gz: d93cc73c36b6761ec33fd8da7f79b5ac5964d11a0b3be4f5632520f36a69fbc5edc467a2cea9bf1b3ec06bc9dbd9f9a6b77eb30cce3292bccf71237a62591104
+  metadata.gz: 9bd87b22a6ba0fa200c94b42554cf365461f845f71823579069c986aedda124dcd9c225d0e5a1fab77bae6a1684fc579e7a82c6e2fdb9878bb58c286db0ea45e
+  data.tar.gz: d1e8c9efbbd74db7d121a900781ba5e245473d8acb1bc78f1655dca5df9bb0937417bdbb173c8103708deb3963a5d7bb6b0aba3cf18b923f1839817b6f7923f2

data/config/commands.rb

@@ -28,9 +28,9 @@ when "examples"
   # Pattern generator tests
   ARGV = %w(read_write_reg -t debug -r approved)
   load "#{Origen.top}/lib/origen/commands/generate.rb"
-  ARGV = %w(read_write_reg_jtag -t debug -r approved)
+  ARGV = %w(read_write_reg_jtag -t jtag -r approved)
   load "#{Origen.top}/lib/origen/commands/generate.rb"
-  ARGV = %w(read_write_reg_swd -t debug -r approved)
+  ARGV = %w(read_write_reg_swd -t swd -r approved)
   load "#{Origen.top}/lib/origen/commands/generate.rb"
     
   if Origen.app.stats.changed_files == 0 &&

data/config/version.rb

@@ -1,7 +1,7 @@
 module OrigenARMDebug
   MAJOR = 0
-  MINOR = 8
-  BUGFIX = 4
+  MINOR = 9
+  BUGFIX = 0
   DEV = nil
 
   VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')

data/lib/origen_arm_debug/driver.rb

@@ -5,34 +5,37 @@ module OrigenARMDebug
   #   include SWD
   #
   class Driver
+    include Origen::Model
+
     # Returns the parent object that instantiated the driver, could be
     # either a DUT object or a protocol abstraction
     attr_reader :owner
 
     # Initialize class variables
     #
-    # @param [Object] owner Parent object
     # @param [Hash] options Options to customize the operation
     #
     # @example
     #   DUT.new.arm_debug
     #
-    def initialize(owner, options = {})
-      @owner = owner
-    end
+    def initialize(options = {})
+      # 'buffer' register to bridge the actual memory-mapped register to the internal DAP transactions
+      #   (also used to support case on non-register based calls)
+      add_reg :buffer, 0x00, 32, data: { pos: 0, bits: 32 }
 
-    # Create and/or return the SWJ_DP object with specified protocol
-    def swj_dp
-      if owner.respond_to?(:swd)
-        @swj_dp ||= SWJ_DP.new(self, :swd)
-      elsif owner.respond_to?(:jtag)
-        @swj_dp ||= SWJ_DP.new(self, :jtag)
-      end
+      instantiate_subblocks(options)
     end
 
-    # Returns an instance of the OrigenARMDebug::MemAP
-    def mem_ap
-      @mem_ap ||= MemAP.new(self)
+    def instantiate_subblocks(options = {})
+      sub_block :swj_dp, class_name: 'OrigenARMDebug::SWJ_DP'
+
+      if options[:aps].nil?
+        add_mem_ap('mem_ap', 0x00000000)
+      else
+        options[:aps].each do |key, value|
+          add_mem_ap(key, value)
+        end
+      end
     end
 
     # Method to add additional Memory Access Ports (MEM-AP) with specified base address
@@ -44,10 +47,24 @@ module OrigenARMDebug
     #   arm_debug.add_mem_ap('alt_ahbapi', 0x02000000)
     #
     def add_mem_ap(name, base_address)
-      instance_variable_set("@#{name}", MemAP.new(self, name: name, base_address: base_address))
-      self.class.send(:attr_accessor, name)
+      domain name.to_sym
+      sub_block name.to_sym, class_name: 'OrigenARMDebug::MemAP', base_address: base_address
     end
 
+    # Create and/or return the SWJ_DP object with specified protocol
+    # def swj_dp
+    #  if parent.respond_to?(:swd)
+    #    @swj_dp ||= SWJ_DP.new(self, :swd)
+    #  elsif parent.respond_to?(:jtag)
+    #    @swj_dp ||= SWJ_DP.new(self, :jtag)
+    #  end
+    # end
+    def abs_if
+      swj_dp
+    end
+    alias_method :apapi, :abs_if
+    alias_method :dpapi, :abs_if
+
     # Read from a MEM-AP register
     #
     # @param [Integer, Origen::Register::Reg, Origen::Register::BitCollection, Origen::Register::Bit] reg_or_val
@@ -59,7 +76,7 @@ module OrigenARMDebug
       if options[:ap].nil?
         ap = mem_ap           # default to 'mem_ap' if no AP is specified as an option
       else
-        ap = options[:ap]
+        ap = eval(options[:ap].to_s)
       end
       ap.read_register(reg_or_val, options)
     end
@@ -75,33 +92,17 @@ module OrigenARMDebug
       if options[:ap].nil?
         ap = mem_ap           # default to 'mem_ap' if no AP is specified as an option
       else
-        ap = options[:ap]
+        ap = eval(options[:ap].to_s)
       end
       ap.write_register(reg_or_val, options)
     end
 
-    def inspect_driver
-      Origen.log.info "ARM Debug Driver = #{arm_debug_driver}"
+    def jtag
+      parent.jtag
     end
 
-    private
-
-    # Short-cut to protocol driver
-    def arm_debug_driver
-      return @arm_debug_driver if @arm_debug_driver
-      if owner.respond_to?(:jtag)
-        @arm_debug_driver = owner.jtag
-      elsif owner.respond_to?(:swd)
-        @arm_debug_driver = owner.swd
-      else
-        puts 'Cannot find a compatible physical driver!'
-        puts 'The ARM debug protocol supports the following phyiscal drivers:'
-        puts '  JTAG - http://origen-sdk.org/origen_jtag'
-        puts '  Single Wire Debug - http://origen-sdk.org/origen_swd'
-        puts '  Background Debug - http://origen-sdk.org/origen_bdm'
-        puts "Add one to your #{owner.class} to resolve this error."
-        fail 'ARM Debug error!'
-      end
+    def swd
+      parent.swd
     end
   end
 end

data/lib/origen_arm_debug/dut.rb

@@ -5,9 +5,8 @@ module OrigenARMDebug
   #
   # It is not included when this library is imported.
   class DUT
+    include Origen::TopLevel
     include OrigenARMDebug
-    include Origen::Callbacks
-    include Origen::Registers
 
     # Initializes simple dut model with test register and required jtag/swd pins
     #
@@ -20,9 +19,12 @@ module OrigenARMDebug
       add_reg :test, 0x0, 32, data: { pos: 0, bits: 32 },
                               bit:  { pos: 0 }
 
-      arm_debug.add_mem_ap('mem_ap', 0x00000000)
-      arm_debug.add_mem_ap('mdm_ap', 0x01000000)
+      sub_block :arm_debug, class_name: 'OrigenARMDebug::Driver', aps: { mem_ap: 0x00000000, mdm_ap: 0x01000000 }
       arm_debug.add_mem_ap('alt_ahbapi', 0x02000000)
+
+      # arm_debug.add_mem_ap('mem_ap', 0x00000000)
+      # arm_debug.add_mem_ap('mdm_ap', 0x01000000)
+      # arm_debug.add_mem_ap('alt_ahbapi', 0x02000000)
     end
 
     # Add any custom startup business here.

data/lib/origen_arm_debug/dut_jtag.rb

@@ -2,7 +2,6 @@ module OrigenARMDebug
   # Simple JTAG-specific dut model that inherits from protocol-agnostic DUT model
   class JTAG_DUT < DUT
     include OrigenJTAG
-    include Origen::Pins
 
     # Adds jtag-required pins to the simple dut model
     # Returns nothing.
@@ -13,6 +12,8 @@ module OrigenARMDebug
       add_pin :tdo
       add_pin :tms
       add_pin :trst
+      add_pin :swd_clk
+      add_pin :swd_dio
     end
   end
 end

data/lib/origen_arm_debug/dut_swd.rb

@@ -2,12 +2,16 @@ module OrigenARMDebug
   # Simple SWD-specific dut model that inherits from protocol-agnostic DUT model
   class SWD_DUT < DUT
     include OrigenSWD
-    include Origen::Pins
 
     # Adds swd-required pins to the simple dut model
     # Returns nothing.
     def initialize
       super
+      add_pin :tclk
+      add_pin :tdi
+      add_pin :tdo
+      add_pin :tms
+      add_pin :trst
       add_pin :swd_clk
       add_pin :swd_dio
     end