origen_arm_debug 0.8.4 → 0.9.0

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
checksums.yaml CHANGED
@@ -1,7 +1,7 @@
1
1
  ---
2
2
  SHA1:
3
- metadata.gz: a4ce85678b97c90ebf41f4dff8b8fad020fe9cfa
4
- data.tar.gz: ca74317b6cd30d1145571c337b842351ad401ef8
3
+ metadata.gz: f4a9f1dc701be4b75209634978ffff6e9c608ea6
4
+ data.tar.gz: f4ac35a546afb37109a02b46fdd099cdb51c2b74
5
5
  SHA512:
6
- metadata.gz: 2579e71201e40ffb48f66196c3eac4c7cb0f94828b0a158ffbb8f62f84fb800c3f70590e9f83f4f6e6b138cc849c96a1e0e003ae733d84087e320cde771a15b7
7
- data.tar.gz: d93cc73c36b6761ec33fd8da7f79b5ac5964d11a0b3be4f5632520f36a69fbc5edc467a2cea9bf1b3ec06bc9dbd9f9a6b77eb30cce3292bccf71237a62591104
6
+ metadata.gz: 9bd87b22a6ba0fa200c94b42554cf365461f845f71823579069c986aedda124dcd9c225d0e5a1fab77bae6a1684fc579e7a82c6e2fdb9878bb58c286db0ea45e
7
+ data.tar.gz: d1e8c9efbbd74db7d121a900781ba5e245473d8acb1bc78f1655dca5df9bb0937417bdbb173c8103708deb3963a5d7bb6b0aba3cf18b923f1839817b6f7923f2
data/config/commands.rb CHANGED
@@ -28,9 +28,9 @@ when "examples"
28
28
  # Pattern generator tests
29
29
  ARGV = %w(read_write_reg -t debug -r approved)
30
30
  load "#{Origen.top}/lib/origen/commands/generate.rb"
31
- ARGV = %w(read_write_reg_jtag -t debug -r approved)
31
+ ARGV = %w(read_write_reg_jtag -t jtag -r approved)
32
32
  load "#{Origen.top}/lib/origen/commands/generate.rb"
33
- ARGV = %w(read_write_reg_swd -t debug -r approved)
33
+ ARGV = %w(read_write_reg_swd -t swd -r approved)
34
34
  load "#{Origen.top}/lib/origen/commands/generate.rb"
35
35
 
36
36
  if Origen.app.stats.changed_files == 0 &&
data/config/version.rb CHANGED
@@ -1,7 +1,7 @@
1
1
  module OrigenARMDebug
2
2
  MAJOR = 0
3
- MINOR = 8
4
- BUGFIX = 4
3
+ MINOR = 9
4
+ BUGFIX = 0
5
5
  DEV = nil
6
6
 
7
7
  VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')
@@ -5,34 +5,37 @@ module OrigenARMDebug
5
5
  # include SWD
6
6
  #
7
7
  class Driver
8
+ include Origen::Model
9
+
8
10
  # Returns the parent object that instantiated the driver, could be
9
11
  # either a DUT object or a protocol abstraction
10
12
  attr_reader :owner
11
13
 
12
14
  # Initialize class variables
13
15
  #
14
- # @param [Object] owner Parent object
15
16
  # @param [Hash] options Options to customize the operation
16
17
  #
17
18
  # @example
18
19
  # DUT.new.arm_debug
19
20
  #
20
- def initialize(owner, options = {})
21
- @owner = owner
22
- end
21
+ def initialize(options = {})
22
+ # 'buffer' register to bridge the actual memory-mapped register to the internal DAP transactions
23
+ # (also used to support case on non-register based calls)
24
+ add_reg :buffer, 0x00, 32, data: { pos: 0, bits: 32 }
23
25
 
24
- # Create and/or return the SWJ_DP object with specified protocol
25
- def swj_dp
26
- if owner.respond_to?(:swd)
27
- @swj_dp ||= SWJ_DP.new(self, :swd)
28
- elsif owner.respond_to?(:jtag)
29
- @swj_dp ||= SWJ_DP.new(self, :jtag)
30
- end
26
+ instantiate_subblocks(options)
31
27
  end
32
28
 
33
- # Returns an instance of the OrigenARMDebug::MemAP
34
- def mem_ap
35
- @mem_ap ||= MemAP.new(self)
29
+ def instantiate_subblocks(options = {})
30
+ sub_block :swj_dp, class_name: 'OrigenARMDebug::SWJ_DP'
31
+
32
+ if options[:aps].nil?
33
+ add_mem_ap('mem_ap', 0x00000000)
34
+ else
35
+ options[:aps].each do |key, value|
36
+ add_mem_ap(key, value)
37
+ end
38
+ end
36
39
  end
37
40
 
38
41
  # Method to add additional Memory Access Ports (MEM-AP) with specified base address
@@ -44,10 +47,24 @@ module OrigenARMDebug
44
47
  # arm_debug.add_mem_ap('alt_ahbapi', 0x02000000)
45
48
  #
46
49
  def add_mem_ap(name, base_address)
47
- instance_variable_set("@#{name}", MemAP.new(self, name: name, base_address: base_address))
48
- self.class.send(:attr_accessor, name)
50
+ domain name.to_sym
51
+ sub_block name.to_sym, class_name: 'OrigenARMDebug::MemAP', base_address: base_address
49
52
  end
50
53
 
54
+ # Create and/or return the SWJ_DP object with specified protocol
55
+ # def swj_dp
56
+ # if parent.respond_to?(:swd)
57
+ # @swj_dp ||= SWJ_DP.new(self, :swd)
58
+ # elsif parent.respond_to?(:jtag)
59
+ # @swj_dp ||= SWJ_DP.new(self, :jtag)
60
+ # end
61
+ # end
62
+ def abs_if
63
+ swj_dp
64
+ end
65
+ alias_method :apapi, :abs_if
66
+ alias_method :dpapi, :abs_if
67
+
51
68
  # Read from a MEM-AP register
52
69
  #
53
70
  # @param [Integer, Origen::Register::Reg, Origen::Register::BitCollection, Origen::Register::Bit] reg_or_val
@@ -59,7 +76,7 @@ module OrigenARMDebug
59
76
  if options[:ap].nil?
60
77
  ap = mem_ap # default to 'mem_ap' if no AP is specified as an option
61
78
  else
62
- ap = options[:ap]
79
+ ap = eval(options[:ap].to_s)
63
80
  end
64
81
  ap.read_register(reg_or_val, options)
65
82
  end
@@ -75,33 +92,17 @@ module OrigenARMDebug
75
92
  if options[:ap].nil?
76
93
  ap = mem_ap # default to 'mem_ap' if no AP is specified as an option
77
94
  else
78
- ap = options[:ap]
95
+ ap = eval(options[:ap].to_s)
79
96
  end
80
97
  ap.write_register(reg_or_val, options)
81
98
  end
82
99
 
83
- def inspect_driver
84
- Origen.log.info "ARM Debug Driver = #{arm_debug_driver}"
100
+ def jtag
101
+ parent.jtag
85
102
  end
86
103
 
87
- private
88
-
89
- # Short-cut to protocol driver
90
- def arm_debug_driver
91
- return @arm_debug_driver if @arm_debug_driver
92
- if owner.respond_to?(:jtag)
93
- @arm_debug_driver = owner.jtag
94
- elsif owner.respond_to?(:swd)
95
- @arm_debug_driver = owner.swd
96
- else
97
- puts 'Cannot find a compatible physical driver!'
98
- puts 'The ARM debug protocol supports the following phyiscal drivers:'
99
- puts ' JTAG - http://origen-sdk.org/origen_jtag'
100
- puts ' Single Wire Debug - http://origen-sdk.org/origen_swd'
101
- puts ' Background Debug - http://origen-sdk.org/origen_bdm'
102
- puts "Add one to your #{owner.class} to resolve this error."
103
- fail 'ARM Debug error!'
104
- end
104
+ def swd
105
+ parent.swd
105
106
  end
106
107
  end
107
108
  end
@@ -5,9 +5,8 @@ module OrigenARMDebug
5
5
  #
6
6
  # It is not included when this library is imported.
7
7
  class DUT
8
+ include Origen::TopLevel
8
9
  include OrigenARMDebug
9
- include Origen::Callbacks
10
- include Origen::Registers
11
10
 
12
11
  # Initializes simple dut model with test register and required jtag/swd pins
13
12
  #
@@ -20,9 +19,12 @@ module OrigenARMDebug
20
19
  add_reg :test, 0x0, 32, data: { pos: 0, bits: 32 },
21
20
  bit: { pos: 0 }
22
21
 
23
- arm_debug.add_mem_ap('mem_ap', 0x00000000)
24
- arm_debug.add_mem_ap('mdm_ap', 0x01000000)
22
+ sub_block :arm_debug, class_name: 'OrigenARMDebug::Driver', aps: { mem_ap: 0x00000000, mdm_ap: 0x01000000 }
25
23
  arm_debug.add_mem_ap('alt_ahbapi', 0x02000000)
24
+
25
+ # arm_debug.add_mem_ap('mem_ap', 0x00000000)
26
+ # arm_debug.add_mem_ap('mdm_ap', 0x01000000)
27
+ # arm_debug.add_mem_ap('alt_ahbapi', 0x02000000)
26
28
  end
27
29
 
28
30
  # Add any custom startup business here.
@@ -2,7 +2,6 @@ module OrigenARMDebug
2
2
  # Simple JTAG-specific dut model that inherits from protocol-agnostic DUT model
3
3
  class JTAG_DUT < DUT
4
4
  include OrigenJTAG
5
- include Origen::Pins
6
5
 
7
6
  # Adds jtag-required pins to the simple dut model
8
7
  # Returns nothing.
@@ -13,6 +12,8 @@ module OrigenARMDebug
13
12
  add_pin :tdo
14
13
  add_pin :tms
15
14
  add_pin :trst
15
+ add_pin :swd_clk
16
+ add_pin :swd_dio
16
17
  end
17
18
  end
18
19
  end
@@ -2,12 +2,16 @@ module OrigenARMDebug
2
2
  # Simple SWD-specific dut model that inherits from protocol-agnostic DUT model
3
3
  class SWD_DUT < DUT
4
4
  include OrigenSWD
5
- include Origen::Pins
6
5
 
7
6
  # Adds swd-required pins to the simple dut model
8
7
  # Returns nothing.
9
8
  def initialize
10
9
  super
10
+ add_pin :tclk
11
+ add_pin :tdi
12
+ add_pin :tdo
13
+ add_pin :tms
14
+ add_pin :trst
11
15
  add_pin :swd_clk
12
16
  add_pin :swd_dio
13
17
  end