origen_arm_debug 1.1.3 → 1.3.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: e80b1afc8a982d2a7ec2041ad61d4f4eedb011abc09a4931d669747c7dc3230c
-  data.tar.gz: 9e4712df2359e3c55674282f9c0ac0169d47e9e7138a59e4a66773d1b087b223
+  metadata.gz: 45cc30ad35c5f7785831b3fa516ce4784e43170ccc21229d5d6744adaa7f08fb
+  data.tar.gz: 3962dec63e6fcdc94de242557b36a34472f152ded5d95a1354e16e61fc04af10
 SHA512:
-  metadata.gz: e3b956766978d89be7ebdeba678195ae916542f1c3b861bc35ec224966f02aea2b3fc4ec3bff87d0809f288a355b745a1334a957c710040a595265e11d4574e6
-  data.tar.gz: 1607a271f01f25ab358205b51bfd9d0837c413041f2c2b57a5f43f8282ccba417d90eb24d32b02b4863343dc41707b155549ea6c54c9d7d370fdde04f67aaaef
+  metadata.gz: a2060517cd1db17b6ef02d89355c0816f9ebe422b03277dc5a7783bb2cb4bca0ebb6aa795e8e6926800bdbd524ec5d9cc1565ded06ed75626ee4fb130dfe991f
+  data.tar.gz: 78a07d7c55c782ee78b025c20b3caf30956f8a550229479c53b53e6b0049f1fe1cb32525e8fbafd44d69ba691ff7d05e7c87d0e5f0747b786af6268394cf3a2e

data/config/boot.rb

@@ -3,3 +3,5 @@ require "origen_arm_debug"
 require "origen_arm_debug_dev/dut"
 require "origen_arm_debug_dev/dut_jtag"
 require "origen_arm_debug_dev/dut_swd"
+require "origen_arm_debug_dev/dut_dual_dp"
+require "origen_arm_debug_dev/dut_jtag_axi"

data/config/commands.rb

@@ -17,19 +17,25 @@ aliases ={
 # Now branch to the specific task code
 case @command
 
-# when "specs"
-#   require "rspec"
-#   exit RSpec::Core::Runner.run(['spec'])
+when "specs"
+  require "rspec"
+  exit RSpec::Core::Runner.run(['spec'])
 
-when "examples"    # , "test"  
+when "examples", "test"  
   Origen.load_application
   status = 0
   
   # Pattern generator tests
-  ARGV = %w(workout -t jtag -e j750 -r approved)
+  ARGV = %w(workout -t jtag.rb -e j750 -r approved)
+  load "#{Origen.top}/lib/origen/commands/generate.rb"
+  ARGV = %w(workout -t jtag_axi.rb -e j750 -r approved)
+  load "#{Origen.top}/lib/origen/commands/generate.rb"
+  ARGV = %w(v6_workout -t jtag_axi.rb -e j750 -r approved)
   load "#{Origen.top}/lib/origen/commands/generate.rb"
   ARGV = %w(workout -t swd -e j750 -r approved)
   load "#{Origen.top}/lib/origen/commands/generate.rb"
+  ARGV = %w(workout -t dual_dp -e j750 -r approved)
+  load "#{Origen.top}/lib/origen/commands/generate.rb"
   ARGV = %w(workout -t config_test -e j750 -r approved/config_test)
   load "#{Origen.top}/lib/origen/commands/generate.rb"
     
@@ -44,12 +50,12 @@ when "examples"    # , "test"
      status = 1
   end
   puts
-#  if @command == "test"
-#    Origen.app.unload_target!
-#    require "rspec"
-#    result = RSpec::Core::Runner.run(['spec'])
-#    status = status == 1 ? 1 : result
-#  end
+  if @command == "test"
+    Origen.app.unload_target!
+    require "rspec"
+    result = RSpec::Core::Runner.run(['spec'])
+    status = status == 1 ? 1 : result
+  end
   exit status
 
 # Always leave an else clause to allow control to fall back through to the

data/config/version.rb

@@ -1,8 +1,7 @@
 module OrigenARMDebug
   MAJOR = 1
-  MINOR = 1
-  BUGFIX = 3
+  MINOR = 3
+  BUGFIX = 0
   DEV = nil
-
   VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')
 end

data/lib/origen_arm_debug/dap.rb

@@ -20,7 +20,11 @@ module OrigenARMDebug
       end
 
       if options[:jtag] || parent.respond_to?(:jtag)
-        options[:class_name] = 'JTAG_DP'
+        if options[:dapv6]
+          options[:class_name] = 'JTAG_DPV6'
+        else
+          options[:class_name] = 'JTAG_DP'
+        end
         dps << sub_block(:jtag_dp, options)
       end
 
@@ -70,11 +74,13 @@ module OrigenARMDebug
     #
     def add_ap(name, options)
       domain name.to_sym
+      # class name is deleted from options in sub_block call
+      class_name = options[:class_name]
       ap = sub_block(name.to_sym, options)
 
-      if options[:class_name] == 'MemAP'
+      if class_name == 'MemAP'
         mem_aps << ap
-      elsif options[:class_name] == 'JTAGAP'
+      elsif class_name == 'JTAGAP'
         jtag_aps << ap
       else
         ext_aps << ap

data/lib/origen_arm_debug/dap_controller.rb

@@ -3,12 +3,41 @@ module OrigenARMDebug
     include Origen::Controller
     include Helpers
 
+    attr_accessor :dp
+
     # Returns the currently enabled DP (or the only DP if only one
     # of them).
     # If no dp is enabled before calling this, it will choose the
     # SW_DP by default.
     def dp
-      dps.first
+      @dp ||= dps.first
+    end
+
+    def set_dp(dp)
+      if dps.size > 1
+        if dp == :swd || dp == :sw
+          @dp = dps.first
+        elsif dp == :jtag
+          @dp = dps.last
+        else
+          Origen.log.error 'origen_arm_debug: Only SWD and JTAG DP available'
+        end
+      else
+        Origen.log.warn 'origen_arm_debug: Ignoring set_dp call since only one DP is available'
+      end
+    end
+
+    def reset_dp
+      @dp = nil
+    end
+
+    def is_jtag?
+      dp.is_jtag?
+    end
+
+    def is_swd?
+      dp.is_swd?
     end
+    alias_method :is_sw?, :is_swd?
   end
 end

data/lib/origen_arm_debug/dp_controller.rb

@@ -9,8 +9,14 @@ module OrigenARMDebug
     # @api private
     def select_ap_reg(reg)
       address = reg.address & 0xFFFF_FFF0
-      if model.select.data != address
-        model.select.write!(address)
+      apsel = (reg.address & 0xFF00_0000) >> 24
+      apbanksel = (reg.address & 0xF0) >> 4
+      # if model.select.data != address
+      if model.select.apsel.data != apsel || model.select.apbanksel.data != apbanksel
+        model.select.write! do |r|
+          r.apsel.write apsel
+          r.apbanksel.write apbanksel
+        end
       end
     end
   end

data/lib/origen_arm_debug/dp_controller_v6.rb

@@ -0,0 +1,17 @@
+module OrigenARMDebug
+  # Common methods shared between the SW and JTAG DP controllers
+  module DPControllerV6
+    # Alias for the ctrlstat register
+    def ctrl_stat
+      ctrlstat
+    end
+
+    # @api private
+    def select_ap_reg(reg)
+      address = (reg.address & 0xFFFF_FFF0) >> 4
+      address1 = (reg.address & 0xFFFF_FFFF_0000_0000) >> 32
+      model.select1.write! address1 if model.select1.data != address1
+      model.select.bits(:addr).write! address if model.select.bits(:addr).data != address
+    end
+  end
+end

data/lib/origen_arm_debug/jtag_dp.rb

@@ -48,9 +48,12 @@ module OrigenARMDebug
 
       reg :select, 0x8 do |reg|
         reg.bit 31..24, :apsel
+        reg.bit 23..8,  :reserved
         reg.bit 7..4, :apbanksel
       end
 
+      select.write options[:dp_select_reset] if options[:dp_select_reset]
+
       add_reg :rdbuff, 0xC, access: :ro, reset: 0
 
       reg :abort, options[:abort_select], access: :wo do |reg|
@@ -65,5 +68,14 @@ module OrigenARMDebug
     def abort
       reg(:abort)
     end
+
+    def is_jtag?
+      true
+    end
+
+    def is_swd?
+      false
+    end
+    alias_method :is_sw?, :is_swd?
   end
 end

data/lib/origen_arm_debug/jtag_dp_v6.rb

@@ -0,0 +1,86 @@
+module OrigenARMDebug
+  class JTAG_DPV6
+    include Origen::Model
+
+    attr_reader :dpacc_select, :apacc_select
+
+    def initialize(options = {})
+      options = {
+        ir_size:       4,
+        idcode_select: 0b1110,
+        abort_select:  0b1000,
+        dpacc_select:  0b1010,
+        apacc_select:  0b1011
+      }.merge(options)
+      @dpacc_select = options[:dpacc_select]
+      @apacc_select = options[:apacc_select]
+      add_reg :ir, 0, size: options[:ir_size]
+
+      # Virtual reg used to represent all of the various 35-bit scan chains
+      reg :dr, 0, size: 35 do |reg|
+        reg.bit 34..3, :data
+        reg.bit 2..1, :a
+        reg.bit 0, :rnw
+      end
+
+      reg :idcode, options[:idcode_select], access: :ro do |reg|
+        reg.bit 31..28, :version
+        reg.bit 27..12, :partno
+        reg.bit 11..1, :designer
+        reg.bit 0, :bit0, reset: 1
+      end
+
+      reg :ctrlstat, 0x4, dpbanksel: 0 do |reg|
+        reg.bit 31, :csyspwrupack
+        reg.bit 30, :csyspwrupreq
+        reg.bit 29, :cdbgpwrupack
+        reg.bit 28, :cdbgpwrupreq
+        reg.bit 27, :cdbgrstack
+        reg.bit 26, :cdbgrstreq
+        reg.bit 23..12, :trncnt
+        reg.bit 11..8, :masklane
+        reg.bit 7, :wdataerr
+        reg.bit 6, :readok
+        reg.bit 5, :stickyerr
+        reg.bit 4, :stickycmp
+        reg.bit 3..2, :trnmode
+        reg.bit 1, :stickyorun
+        reg.bit 0, :orundetect
+      end
+
+      reg :select, 0x8 do |reg|
+        reg.bit 31..4, :addr
+        reg.bit 3..0, :dpbanksel
+      end
+
+      reg :select1, 0x4, dpbanksel: 5 do |reg|
+        reg.bit 31..0, :addr
+      end
+
+      select.write options[:dp_select_reset] if options[:dp_select_reset]
+
+      add_reg :rdbuff, 0xC, access: :ro, reset: 0
+
+      reg :abort, options[:abort_select], access: :wo do |reg|
+        reg.bit 0, :dapabort
+      end
+    end
+
+    def select
+      reg(:select)
+    end
+
+    def abort
+      reg(:abort)
+    end
+
+    def is_jtag?
+      true
+    end
+
+    def is_swd?
+      false
+    end
+    alias_method :is_sw?, :is_swd?
+  end
+end

data/lib/origen_arm_debug/jtag_dp_v6_controller.rb

@@ -0,0 +1,168 @@
+module OrigenARMDebug
+  class JTAG_DPV6Controller
+    include Origen::Controller
+    include Helpers
+    include DPControllerV6
+
+    def write_register(reg, options = {})
+      unless reg.writable?
+        fail "The :#{reg.name} register is not writeable!"
+      end
+
+      # DP register write
+      if reg.owner == model
+        # Don't log this one, not really a DP reg and will be included
+        # in the JTAG driver log anyway
+        if reg.name == :ir
+          dut.jtag.write_ir(reg)
+        else
+
+          log "Write JTAG-DP register #{reg.name.to_s.upcase}: #{reg.data.to_hex}" do
+            if reg.name == :abort
+              ir.write!(reg.offset)
+              dr.reset
+              dr.overlay(nil)
+              dr[2..0].write(0)
+              dr[34..3].copy_all(reg)
+              dut.jtag.write_dr(dr)
+
+            # DPACC
+            elsif reg.name == :select
+              dp_write(reg)
+
+            # Some other debug register
+            elsif reg.meta.include?(:dpbanksel)
+              if model.reg(:select).bits(:dpbanksel).data != reg.meta[:dpbanksel]
+                model.reg(:select).bits(:dpbanksel).write! reg.meta[:dpbanksel]
+              end
+              dp_write(reg)
+
+            else
+              fail "Can't write #{reg.name}"
+            end
+          end
+        end
+
+      # AP register write
+      else
+
+        unless reg.owner.is_a?(AP)
+          fail 'The JTAG-DP can only write to DP or AP registers!'
+        end
+
+        select_ap_reg(reg)
+        dr.reset
+        dr.overlay(nil)
+        dr[0].write(0)
+        dr[2..1].write(reg.offset >> 2)
+        dr[34..3].copy_all(reg)
+        ir.write!(apacc_select)
+        dut.jtag.write_dr(dr, options)
+      end
+    end
+
+    def read_register(reg, options = {})
+      unless reg.readable?
+        fail "The :#{reg.name} register is not readable!"
+      end
+
+      if reg.owner == model
+        # Don't log this one, not really a DP reg and will be included
+        # in the JTAG driver log anyway
+        if reg.name == :ir
+          dut.jtag.read_ir(reg)
+        else
+
+          log "Read JTAG-DP register #{reg.name.to_s.upcase}: #{Origen::Utility.read_hex(reg)}" do
+            if reg.name == :idcode
+              ir.write!(reg.offset)
+              dut.jtag.read_dr(reg)
+
+            # DPACC
+            elsif reg.name == :select || reg.name == :rdbuff
+              dp_read(reg, options)
+
+            # Some other register
+            elsif reg.meta.include?(:dpbanksel)
+              # Part 1 - Set dpbanksel if required
+              if model.reg(:select).bits(:dpbanksel).data != reg.meta[:dpbanksel]
+                model.reg(:select).bits(:dpbanksel).write! reg.meta[:dpbanksel]
+              end
+
+              dp_read(reg, options)
+
+            else
+              fail "Can't read #{reg.name}"
+            end
+          end
+        end
+
+      # AP register read
+      else
+        unless reg.owner.is_a?(AP)
+          fail 'The JTAG-DP can only write to DP or AP registers!'
+        end
+
+        # Part 1 - Request read from AP-Register by writing to APACC with RnW=1
+        select_ap_reg(reg)
+        dr.reset
+        dr.overlay(nil)
+        dr[0].write(1)
+        dr[2..1].write(reg.offset >> 2)
+        dr[34..3].write(0)
+        ir.write!(apacc_select)
+        dut.jtag.write_dr(dr)
+
+        # Calling AP should provide any delay parameter for wait states between AP read request
+        #   and when the data is available at the RDBUFF DP-Reg
+        if options[:apacc_wait_states]
+          options[:apacc_wait_states].cycles
+        end
+
+        # Part 2 - Now read real data from RDBUFF (DP-Reg)
+        dr.reset
+        dr.overlay(nil)
+        dr[0].write(1)
+        dr[2..1].write(rdbuff.offset >> 2)
+        dr[34..3].copy_all(reg)
+        options[:mask] = options[:mask] << 3 unless options[:mask].nil?
+        ir.write!(dpacc_select)
+        dut.jtag.read_dr(dr, options)
+      end
+    end
+
+    def dp_read(reg, options = {})
+      # Part 1 - Request read from DP-Register by writing to DPACC with RnW=1
+      dr.reset
+      dr.overlay(nil)
+      dr[0].write(1)
+      dr[2..1].write(reg.offset >> 2)
+      dr[34..3].write(0)
+      ir.write!(dpacc_select)
+      dut.jtag.write_dr(dr)
+
+      # Part 2 - Now read real data from RDBUFF (DP-Reg)
+      dr.reset
+      dr.overlay(nil)
+      dr[0].write(1)
+      dr[2..1].write(rdbuff.offset >> 2)
+      dr[34..3].copy_all(reg)
+      options[:mask] = options[:mask] << 3 unless options[:mask].nil?
+      dut.jtag.read_dr(dr, options)
+    end
+
+    def dp_write(reg)
+      dr.reset
+      dr.overlay(nil)
+      dr[0].write(0)
+      dr[2..1].write(reg.offset >> 2)
+      dr[34..3].copy_all(reg)
+      ir.write!(dpacc_select)
+      dut.jtag.write_dr(dr)
+    end
+
+    def base_address
+      model.base_address
+    end
+  end
+end

data/lib/origen_arm_debug/mem_ap.rb

@@ -14,21 +14,52 @@ module OrigenARMDebug
     #   For SWD, this is the wait states in between setting the AP, initiating and completing a dummy read, and beginning the actual read transaction.
     attr_accessor :apacc_wait_states
 
+    # Boolean value indicating whether this is an AXI-AP
+    attr_accessor :is_axi
+
+    # Value to be read from DP CSW for interleaved status checks (debug feature)
+    attr_accessor :csw_status_check
+
+    # Boolean value indicating whether to interleave status checks during transactions (debug feature)
+    attr_accessor :interleave_status_check
+
     def initialize(options = {})
       super
 
+      @is_axi = options[:is_axi]
+      @csw_status_check = options[:csw_status_check]
+      @interleave_status_check = options[:interleave_status_check]
+
       @latency = options[:latency] || 0
       @apmem_access_wait = options[:apmem_access_wait] || 0
 
-      reg :csw, 0x0 do |reg|
-        reg.bit 31,     :dbg_sw_enable
-        reg.bit 30..24, :prot
-        reg.bit 23,     :spiden
-        reg.bit 11..8,  :mode
-        reg.bit 7,      :tr_in_prog
-        reg.bit 6,      :device_en
-        reg.bit 5..4,   :addr_inc
-        reg.bit 2..0,   :size
+      if @is_axi
+        reg :csw, 0x0 do |reg|
+          reg.bit 31,     :reserved
+          reg.bit 30..28, :prot, res: 3
+          reg.bit 27..24, :cache
+          reg.bit 23,     :spiden
+          reg.bit 22..15, :reserved2
+          reg.bit 14..13, :domain, res: 3
+          reg.bit 12,     :ace_enable
+          reg.bit 11..8,  :mode
+          reg.bit 7,      :tr_in_prog
+          reg.bit 6,      :dbg_status, res: 1
+          reg.bit 5..4,   :addr_inc
+          reg.bit 3,      :reserved3
+          reg.bit 2..0,   :size, res: 2
+        end
+      else
+        reg :csw, 0x0 do |reg|
+          reg.bit 31,     :dbg_sw_enable
+          reg.bit 30..24, :prot
+          reg.bit 23,     :spiden
+          reg.bit 11..8,  :mode
+          reg.bit 7,      :tr_in_prog
+          reg.bit 6,      :device_en
+          reg.bit 5..4,   :addr_inc
+          reg.bit 2..0,   :size
+        end
       end
       reg(:csw).write(options[:csw_reset]) if options[:csw_reset]
 

data/lib/origen_arm_debug/mem_ap_controller.rb

@@ -18,11 +18,13 @@ module OrigenARMDebug
         log "Write MEM-AP (#{model.name}) address #{addr.to_hex}: #{data.to_hex}" do
           csw.bits(:size).write!(0b010) if csw.bits(:size).data != 0b010
           tar.write!(addr) unless tar.data == addr
+          parent.dp.ctrlstat.read! model.csw_status_check if model.interleave_status_check
           drw.reset
           drw.overlay(nil)
           drw.copy_all(reg_or_val)
           drw.write!(options)
           latency.cycles
+          parent.dp.ctrlstat.read! model.csw_status_check if model.interleave_status_check
         end
         increment_addr
       end
@@ -43,11 +45,13 @@ module OrigenARMDebug
           csw.bits(:size).write!(0b010) if csw.bits(:size).data != 0b010
           unless tar.data == addr
             tar.write!(addr)
+            parent.dp.ctrlstat.read! model.csw_status_check if model.interleave_status_check
           end
           drw.reset
           drw.overlay(nil)
           drw.copy_all(reg_or_val)
           parent.dp.read_register(drw, options.merge(apacc_wait_states: (apmem_access_wait + apreg_access_wait)))
+          parent.dp.ctrlstat.read! model.csw_status_check if model.interleave_status_check
         end
         increment_addr
       end

data/lib/origen_arm_debug/sw_dp.rb

@@ -60,5 +60,14 @@ module OrigenARMDebug
     def abort
       reg(:abort)
     end
+
+    def is_jtag?
+      false
+    end
+
+    def is_swd?
+      true
+    end
+    alias_method :is_sw?, :is_swd?
   end
 end

data/lib/origen_arm_debug.rb

@@ -8,8 +8,11 @@ module OrigenARMDebug
   require 'origen_arm_debug/dap'
   require 'origen_arm_debug/dap_controller'
   require 'origen_arm_debug/dp_controller'
+  require 'origen_arm_debug/dp_controller_v6'
   require 'origen_arm_debug/jtag_dp'
   require 'origen_arm_debug/jtag_dp_controller'
+  require 'origen_arm_debug/jtag_dp_v6'
+  require 'origen_arm_debug/jtag_dp_v6_controller'
   require 'origen_arm_debug/sw_dp'
   require 'origen_arm_debug/sw_dp_controller'
   require 'origen_arm_debug/ap'

data/lib/origen_arm_debug_dev/dut_dual_dp.rb

@@ -0,0 +1,34 @@
+module OrigenARMDebugDev
+  # Simple JTAG-specific dut model that inherits from protocol-agnostic DUT model
+  class DUAL_DP_DUT < DUT
+    include OrigenSWD
+    include OrigenJTAG
+
+    # Adds jtag-required pins to the simple dut model
+    # Returns nothing.
+    def initialize(options = {})
+      super
+      add_pin :tclk
+      add_pin :tdi
+      add_pin :tdo
+      add_pin :tms
+      add_pin :trst
+      add_pin :swd_clk
+      add_pin :swd_dio
+
+      options[:class_name] = 'OrigenARMDebug::DAP'
+      options[:mem_aps] = {
+        mem_ap: {
+          base_address:      0x00000000,
+          latency:           16,
+          apreg_access_wait: 8,
+          apmem_access_wait: 8,
+          csw_reset:         0x23000040
+        },
+        mdm_ap: 0x01000000
+      }
+      # Specify (customize) ARM Debug implementation details
+      sub_block :arm_debug, options
+    end
+  end
+end

data/lib/origen_arm_debug_dev/dut_jtag_axi.rb

@@ -0,0 +1,50 @@
+module OrigenARMDebugDev
+  # Simple JTAG-specific dut model that inherits from protocol-agnostic DUT model
+  class JTAG_AXI_DUT < DUT
+    include OrigenJTAG
+
+    # Adds jtag-required pins to the simple dut model
+    # Returns nothing.
+    def initialize(options = {})
+      super
+      add_pin :tclk
+      add_pin :tdi
+      add_pin :tdo
+      add_pin :tms
+      add_pin :trst
+      add_pin :swd_clk
+      add_pin :swd_dio
+
+      options[:class_name] = 'OrigenARMDebug::DAP'
+      options[:mem_aps] = {
+        mem_ap: {
+          base_address:      0x00000000,
+          latency:           16,
+          apreg_access_wait: 8,
+          apmem_access_wait: 8,
+          is_axi:            true,
+          csw_reset:         0x1080_6002
+        },
+        mdm_ap: 0x01000000
+      }
+      options[:dp_select_reset] = 0xC2_0D00
+      # Specify (customize) ARM Debug implementation details
+      sub_block :arm_debug, options
+
+      options[:dapv6] = true
+      options[:class_name] = 'OrigenARMDebug::DAP'
+      options[:mem_aps] = {
+        mem_ap: {
+          base_address:      0x00C2_0000,
+          latency:           16,
+          apreg_access_wait: 8,
+          apmem_access_wait: 8,
+          is_axi:            true,
+          csw_reset:         0x1080_6002
+        },
+        mdm_ap: 0x00C3_0000
+      }
+      sub_block :arm_debugv6, options
+    end
+  end
+end

data/pattern/v6_workout.rb

@@ -0,0 +1,114 @@
+pattern_name = "v6_workout_#{dut.arm_debugv6.dp.name}"
+
+Pattern.create name: pattern_name do
+
+  ss "Tests of direct DP API"
+  dp = dut.arm_debugv6.dp
+
+  dp.idcode.partno.read!(0x12)
+
+  dp.ctrlstat.write!(0x50000000)
+  dp.ctrlstat.read!(0xF0000000)
+
+  dp.select.bits(:addr).write!(0xF)
+  dp.select.read!
+  dp.select1.write! 4
+  dp.select1.read! 4
+
+  dp.abort.dapabort.write!(1)
+
+  ss "Tests of direct AP API"
+  ap = dut.arm_debugv6.mem_ap
+
+  ap.tar.write!(0x1234_0000)
+
+  ap.tar.read!
+
+  ss "Tests of high-level register API"
+
+  ss "Test write register, should write value 0xFF01"
+  dut.reg(:test).write!(0x0000FF01)
+
+  ss "Test write register with overlay, no subroutine"
+  dut.reg(:test).overlay('write_overlay')
+  dut.reg(:test).write!(0x0000FF01, no_subr: true)
+  dut.reg(:test).overlay(nil)
+
+  ss "Test write register with overlay, use subroutine if available"
+  dut.reg(:test).overlay('write_overlay_subr')
+  dut.reg(:test).write!(0x0000FF01)
+  dut.reg(:test).overlay(nil)
+
+  ss "Test read register, should read value 0x0000FF01"
+  dut.reg(:test).read!
+ 
+  ss "Test read register, with overlay, no subroutine, should read value 0x0000FF01"
+  dut.reg(:test).overlay('read_overlay')
+  dut.reg(:test).read!(no_subr: true)
+  dut.reg(:test).overlay(nil)
+
+  ss "Test read register, with overlay, use subroutine if available"
+  dut.reg(:test).overlay('read_overlay_subr')
+  dut.reg(:test).read!
+  dut.reg(:test).overlay(nil)
+  
+  ss "Test read register with mask, should read value 0xXXXxxx1"
+  dut.reg(:test).read!(mask: 0x0000_000F)
+
+  ss "Test read register with store"
+  dut.reg(:test).store!
+
+  ss "Test bit level read, should read value 0xXXXxxx1"
+  dut.reg(:test).reset
+  dut.reg(:test).data = 0x0000FF01
+  dut.reg(:test)[0].read!
+
+  if Origen.app.target.name == 'dual_dp'
+    ss "SWITCHING DP"
+    dut.arm_debugv6.set_dp(:jtag)
+
+    ss "Test write register, should write value 0xFF01"
+    dut.reg(:test).write!(0x0000FF01)
+
+    ss "Test write register with overlay, no subroutine"
+    dut.reg(:test).overlay('write_overlay')
+    dut.reg(:test).write!(0x0000FF01, no_subr: true)
+    dut.reg(:test).overlay(nil)
+
+    ss "Test write register with overlay, use subroutine if available"
+    dut.reg(:test).overlay('write_overlay_subr')
+    dut.reg(:test).write!(0x0000FF01)
+    dut.reg(:test).overlay(nil)
+
+    ss "Test read register, should read value 0x0000FF01"
+    dut.reg(:test).read!
+   
+    ss "Test read register, with overlay, no subroutine, should read value 0x0000FF01"
+    dut.reg(:test).overlay('read_overlay')
+    dut.reg(:test).read!(no_subr: true)
+    dut.reg(:test).overlay(nil)
+
+    ss "Test read register, with overlay, use subroutine if available"
+    dut.reg(:test).overlay('read_overlay_subr')
+    dut.reg(:test).read!
+    dut.reg(:test).overlay(nil)
+    
+    ss "Test read register with mask, should read value 0xXXXxxx1"
+    dut.reg(:test).read!(mask: 0x0000_000F)
+
+    ss "Test read register with store"
+    dut.reg(:test).store!
+
+    ss "Test bit level read, should read value 0xXXXxxx1"
+    dut.reg(:test).reset
+    dut.reg(:test).data = 0x0000FF01
+    dut.reg(:test)[0].read!
+
+    ss "RESETTING DP (to default)"
+    dut.arm_debugv6.reset_dp
+    ss "Test bit level read, should read value 0xXXXxxx1"
+    dut.reg(:test).reset
+    dut.reg(:test).data = 0x0000FF01
+    dut.reg(:test)[0].read!
+  end
+end

data/pattern/workout.rb

@@ -1,4 +1,12 @@
-Pattern.create name: "workout_#{dut.arm_debug.dp.name}" do
+if Origen.app.target.name == 'dual_dp'
+  pattern_name = 'workout_dual_dp'
+elsif Origen.app.target.name == 'jtag_axi'
+  pattern_name = 'workout_jtag_axi'
+else
+  pattern_name = "workout_#{dut.arm_debug.dp.name}"
+end
+
+Pattern.create name: pattern_name do
 
   ss "Tests of direct DP API"
   dp = dut.arm_debug.dp
@@ -8,7 +16,11 @@ Pattern.create name: "workout_#{dut.arm_debug.dp.name}" do
   dp.ctrlstat.write!(0x50000000)
   dp.ctrlstat.read!(0xF0000000)
 
-  dp.select.apbanksel.write!(0xF)
+  if dp.select.has_bits?(:apbanksel)
+    dp.select.apbanksel.write!(0xF)
+  else
+    dp.select.bits(31..24).write!(0xF)
+  end
 
   dp.abort.dapabort.write!(1)
 
@@ -58,4 +70,52 @@ Pattern.create name: "workout_#{dut.arm_debug.dp.name}" do
   dut.reg(:test).data = 0x0000FF01
   dut.reg(:test)[0].read!
 
+  if Origen.app.target.name == 'dual_dp'
+    ss "SWITCHING DP"
+    dut.arm_debug.set_dp(:jtag)
+
+    ss "Test write register, should write value 0xFF01"
+    dut.reg(:test).write!(0x0000FF01)
+
+    ss "Test write register with overlay, no subroutine"
+    dut.reg(:test).overlay('write_overlay')
+    dut.reg(:test).write!(0x0000FF01, no_subr: true)
+    dut.reg(:test).overlay(nil)
+
+    ss "Test write register with overlay, use subroutine if available"
+    dut.reg(:test).overlay('write_overlay_subr')
+    dut.reg(:test).write!(0x0000FF01)
+    dut.reg(:test).overlay(nil)
+
+    ss "Test read register, should read value 0x0000FF01"
+    dut.reg(:test).read!
+   
+    ss "Test read register, with overlay, no subroutine, should read value 0x0000FF01"
+    dut.reg(:test).overlay('read_overlay')
+    dut.reg(:test).read!(no_subr: true)
+    dut.reg(:test).overlay(nil)
+
+    ss "Test read register, with overlay, use subroutine if available"
+    dut.reg(:test).overlay('read_overlay_subr')
+    dut.reg(:test).read!
+    dut.reg(:test).overlay(nil)
+    
+    ss "Test read register with mask, should read value 0xXXXxxx1"
+    dut.reg(:test).read!(mask: 0x0000_000F)
+
+    ss "Test read register with store"
+    dut.reg(:test).store!
+
+    ss "Test bit level read, should read value 0xXXXxxx1"
+    dut.reg(:test).reset
+    dut.reg(:test).data = 0x0000FF01
+    dut.reg(:test)[0].read!
+
+    ss "RESETTING DP (to default)"
+    dut.arm_debug.reset_dp
+    ss "Test bit level read, should read value 0xXXXxxx1"
+    dut.reg(:test).reset
+    dut.reg(:test).data = 0x0000FF01
+    dut.reg(:test)[0].read!
+  end
 end

data/templates/web/index.md.erb

@@ -52,7 +52,7 @@ class DUT
     
     # Simple example using default wait-states and latency:
     #   mem_ap:  APSEL = 0x00 (base_address[31:24])
-    #   mem2_ap: APSEL = 0x01 (base_address[31:24])
+    #   mem2_ap: APSEL = 0x01 (base_address[31:24], is_axi: true)	# is_axi: true for AXI-AP
     mem_aps = {
       mem_ap: { base_address: 0x00000000 },
       mem2_ap: { base_address: 0x10000000 }
@@ -133,6 +133,22 @@ instantiation_options[:idcode_select] = 0xFE
 instantiation_options[:abort_select] = 0xF8
 instantiation_options[:dpacc_select] = 0xFA
 instantiation_options[:apacc_select] = 0xFB
+instantiation_options[:dp_select_reset] = 0xC2_0D00
+
+sub_block :arm_debug, instantiation_options
+~~~
+
+DAP Version 6 instantiation example:
+
+~~~ruby
+mem_aps = {
+  mem_ap: { base_address: 0x001C_1000 }
+  mem2_ap: { base_address: 0x001C_2000 }
+}
+instantiation_options[:class_name] = 'OrigenARMDebug::DAP'
+instantiation_options[:mem_aps] = mem_aps
+
+instantiation_options[:dapv6] = true
 
 sub_block :arm_debug, instantiation_options
 ~~~

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: origen_arm_debug
 version: !ruby/object:Gem::Version
-  version: 1.1.3
+  version: 1.3.0
 platform: ruby
 authors:
 - Ronnie Lajaunie
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2019-01-21 00:00:00.000000000 Z
+date: 2022-02-28 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: origen
@@ -87,18 +87,24 @@ files:
 - lib/origen_arm_debug/dap.rb
 - lib/origen_arm_debug/dap_controller.rb
 - lib/origen_arm_debug/dp_controller.rb
+- lib/origen_arm_debug/dp_controller_v6.rb
 - lib/origen_arm_debug/helpers.rb
 - lib/origen_arm_debug/jtag_ap.rb
 - lib/origen_arm_debug/jtag_ap_controller.rb
 - lib/origen_arm_debug/jtag_dp.rb
 - lib/origen_arm_debug/jtag_dp_controller.rb
+- lib/origen_arm_debug/jtag_dp_v6.rb
+- lib/origen_arm_debug/jtag_dp_v6_controller.rb
 - lib/origen_arm_debug/mem_ap.rb
 - lib/origen_arm_debug/mem_ap_controller.rb
 - lib/origen_arm_debug/sw_dp.rb
 - lib/origen_arm_debug/sw_dp_controller.rb
 - lib/origen_arm_debug_dev/dut.rb
+- lib/origen_arm_debug_dev/dut_dual_dp.rb
 - lib/origen_arm_debug_dev/dut_jtag.rb
+- lib/origen_arm_debug_dev/dut_jtag_axi.rb
 - lib/origen_arm_debug_dev/dut_swd.rb
+- pattern/v6_workout.rb
 - pattern/workout.rb
 - templates/web/index.md.erb
 - templates/web/layouts/_basic.html.erb
@@ -123,8 +129,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: 1.8.11
 requirements: []
-rubyforge_project: 
-rubygems_version: 2.7.7
+rubygems_version: 3.1.4
 signing_key: 
 specification_version: 4
 summary: Provides an Origen API to perform register read and write operations via