origen_arm_debug 1.1.3 → 1.3.0
Sign up to get free protection for your applications and to get access to all the features.
- checksums.yaml +4 -4
- data/config/boot.rb +2 -0
- data/config/commands.rb +17 -11
- data/config/version.rb +2 -3
- data/lib/origen_arm_debug/dap.rb +9 -3
- data/lib/origen_arm_debug/dap_controller.rb +30 -1
- data/lib/origen_arm_debug/dp_controller.rb +8 -2
- data/lib/origen_arm_debug/dp_controller_v6.rb +17 -0
- data/lib/origen_arm_debug/jtag_dp.rb +12 -0
- data/lib/origen_arm_debug/jtag_dp_v6.rb +86 -0
- data/lib/origen_arm_debug/jtag_dp_v6_controller.rb +168 -0
- data/lib/origen_arm_debug/mem_ap.rb +40 -9
- data/lib/origen_arm_debug/mem_ap_controller.rb +4 -0
- data/lib/origen_arm_debug/sw_dp.rb +9 -0
- data/lib/origen_arm_debug.rb +3 -0
- data/lib/origen_arm_debug_dev/dut_dual_dp.rb +34 -0
- data/lib/origen_arm_debug_dev/dut_jtag_axi.rb +50 -0
- data/pattern/v6_workout.rb +114 -0
- data/pattern/workout.rb +62 -2
- data/templates/web/index.md.erb +17 -1
- metadata +9 -4
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
|
|
1
1
|
---
|
2
2
|
SHA256:
|
3
|
-
metadata.gz:
|
4
|
-
data.tar.gz:
|
3
|
+
metadata.gz: 45cc30ad35c5f7785831b3fa516ce4784e43170ccc21229d5d6744adaa7f08fb
|
4
|
+
data.tar.gz: 3962dec63e6fcdc94de242557b36a34472f152ded5d95a1354e16e61fc04af10
|
5
5
|
SHA512:
|
6
|
-
metadata.gz:
|
7
|
-
data.tar.gz:
|
6
|
+
metadata.gz: a2060517cd1db17b6ef02d89355c0816f9ebe422b03277dc5a7783bb2cb4bca0ebb6aa795e8e6926800bdbd524ec5d9cc1565ded06ed75626ee4fb130dfe991f
|
7
|
+
data.tar.gz: 78a07d7c55c782ee78b025c20b3caf30956f8a550229479c53b53e6b0049f1fe1cb32525e8fbafd44d69ba691ff7d05e7c87d0e5f0747b786af6268394cf3a2e
|
data/config/boot.rb
CHANGED
data/config/commands.rb
CHANGED
@@ -17,19 +17,25 @@ aliases ={
|
|
17
17
|
# Now branch to the specific task code
|
18
18
|
case @command
|
19
19
|
|
20
|
-
|
21
|
-
|
22
|
-
|
20
|
+
when "specs"
|
21
|
+
require "rspec"
|
22
|
+
exit RSpec::Core::Runner.run(['spec'])
|
23
23
|
|
24
|
-
when "examples"
|
24
|
+
when "examples", "test"
|
25
25
|
Origen.load_application
|
26
26
|
status = 0
|
27
27
|
|
28
28
|
# Pattern generator tests
|
29
|
-
ARGV = %w(workout -t jtag -e j750 -r approved)
|
29
|
+
ARGV = %w(workout -t jtag.rb -e j750 -r approved)
|
30
|
+
load "#{Origen.top}/lib/origen/commands/generate.rb"
|
31
|
+
ARGV = %w(workout -t jtag_axi.rb -e j750 -r approved)
|
32
|
+
load "#{Origen.top}/lib/origen/commands/generate.rb"
|
33
|
+
ARGV = %w(v6_workout -t jtag_axi.rb -e j750 -r approved)
|
30
34
|
load "#{Origen.top}/lib/origen/commands/generate.rb"
|
31
35
|
ARGV = %w(workout -t swd -e j750 -r approved)
|
32
36
|
load "#{Origen.top}/lib/origen/commands/generate.rb"
|
37
|
+
ARGV = %w(workout -t dual_dp -e j750 -r approved)
|
38
|
+
load "#{Origen.top}/lib/origen/commands/generate.rb"
|
33
39
|
ARGV = %w(workout -t config_test -e j750 -r approved/config_test)
|
34
40
|
load "#{Origen.top}/lib/origen/commands/generate.rb"
|
35
41
|
|
@@ -44,12 +50,12 @@ when "examples" # , "test"
|
|
44
50
|
status = 1
|
45
51
|
end
|
46
52
|
puts
|
47
|
-
|
48
|
-
|
49
|
-
|
50
|
-
|
51
|
-
|
52
|
-
|
53
|
+
if @command == "test"
|
54
|
+
Origen.app.unload_target!
|
55
|
+
require "rspec"
|
56
|
+
result = RSpec::Core::Runner.run(['spec'])
|
57
|
+
status = status == 1 ? 1 : result
|
58
|
+
end
|
53
59
|
exit status
|
54
60
|
|
55
61
|
# Always leave an else clause to allow control to fall back through to the
|
data/config/version.rb
CHANGED
data/lib/origen_arm_debug/dap.rb
CHANGED
@@ -20,7 +20,11 @@ module OrigenARMDebug
|
|
20
20
|
end
|
21
21
|
|
22
22
|
if options[:jtag] || parent.respond_to?(:jtag)
|
23
|
-
options[:
|
23
|
+
if options[:dapv6]
|
24
|
+
options[:class_name] = 'JTAG_DPV6'
|
25
|
+
else
|
26
|
+
options[:class_name] = 'JTAG_DP'
|
27
|
+
end
|
24
28
|
dps << sub_block(:jtag_dp, options)
|
25
29
|
end
|
26
30
|
|
@@ -70,11 +74,13 @@ module OrigenARMDebug
|
|
70
74
|
#
|
71
75
|
def add_ap(name, options)
|
72
76
|
domain name.to_sym
|
77
|
+
# class name is deleted from options in sub_block call
|
78
|
+
class_name = options[:class_name]
|
73
79
|
ap = sub_block(name.to_sym, options)
|
74
80
|
|
75
|
-
if
|
81
|
+
if class_name == 'MemAP'
|
76
82
|
mem_aps << ap
|
77
|
-
elsif
|
83
|
+
elsif class_name == 'JTAGAP'
|
78
84
|
jtag_aps << ap
|
79
85
|
else
|
80
86
|
ext_aps << ap
|
@@ -3,12 +3,41 @@ module OrigenARMDebug
|
|
3
3
|
include Origen::Controller
|
4
4
|
include Helpers
|
5
5
|
|
6
|
+
attr_accessor :dp
|
7
|
+
|
6
8
|
# Returns the currently enabled DP (or the only DP if only one
|
7
9
|
# of them).
|
8
10
|
# If no dp is enabled before calling this, it will choose the
|
9
11
|
# SW_DP by default.
|
10
12
|
def dp
|
11
|
-
dps.first
|
13
|
+
@dp ||= dps.first
|
14
|
+
end
|
15
|
+
|
16
|
+
def set_dp(dp)
|
17
|
+
if dps.size > 1
|
18
|
+
if dp == :swd || dp == :sw
|
19
|
+
@dp = dps.first
|
20
|
+
elsif dp == :jtag
|
21
|
+
@dp = dps.last
|
22
|
+
else
|
23
|
+
Origen.log.error 'origen_arm_debug: Only SWD and JTAG DP available'
|
24
|
+
end
|
25
|
+
else
|
26
|
+
Origen.log.warn 'origen_arm_debug: Ignoring set_dp call since only one DP is available'
|
27
|
+
end
|
28
|
+
end
|
29
|
+
|
30
|
+
def reset_dp
|
31
|
+
@dp = nil
|
32
|
+
end
|
33
|
+
|
34
|
+
def is_jtag?
|
35
|
+
dp.is_jtag?
|
36
|
+
end
|
37
|
+
|
38
|
+
def is_swd?
|
39
|
+
dp.is_swd?
|
12
40
|
end
|
41
|
+
alias_method :is_sw?, :is_swd?
|
13
42
|
end
|
14
43
|
end
|
@@ -9,8 +9,14 @@ module OrigenARMDebug
|
|
9
9
|
# @api private
|
10
10
|
def select_ap_reg(reg)
|
11
11
|
address = reg.address & 0xFFFF_FFF0
|
12
|
-
|
13
|
-
|
12
|
+
apsel = (reg.address & 0xFF00_0000) >> 24
|
13
|
+
apbanksel = (reg.address & 0xF0) >> 4
|
14
|
+
# if model.select.data != address
|
15
|
+
if model.select.apsel.data != apsel || model.select.apbanksel.data != apbanksel
|
16
|
+
model.select.write! do |r|
|
17
|
+
r.apsel.write apsel
|
18
|
+
r.apbanksel.write apbanksel
|
19
|
+
end
|
14
20
|
end
|
15
21
|
end
|
16
22
|
end
|
@@ -0,0 +1,17 @@
|
|
1
|
+
module OrigenARMDebug
|
2
|
+
# Common methods shared between the SW and JTAG DP controllers
|
3
|
+
module DPControllerV6
|
4
|
+
# Alias for the ctrlstat register
|
5
|
+
def ctrl_stat
|
6
|
+
ctrlstat
|
7
|
+
end
|
8
|
+
|
9
|
+
# @api private
|
10
|
+
def select_ap_reg(reg)
|
11
|
+
address = (reg.address & 0xFFFF_FFF0) >> 4
|
12
|
+
address1 = (reg.address & 0xFFFF_FFFF_0000_0000) >> 32
|
13
|
+
model.select1.write! address1 if model.select1.data != address1
|
14
|
+
model.select.bits(:addr).write! address if model.select.bits(:addr).data != address
|
15
|
+
end
|
16
|
+
end
|
17
|
+
end
|
@@ -48,9 +48,12 @@ module OrigenARMDebug
|
|
48
48
|
|
49
49
|
reg :select, 0x8 do |reg|
|
50
50
|
reg.bit 31..24, :apsel
|
51
|
+
reg.bit 23..8, :reserved
|
51
52
|
reg.bit 7..4, :apbanksel
|
52
53
|
end
|
53
54
|
|
55
|
+
select.write options[:dp_select_reset] if options[:dp_select_reset]
|
56
|
+
|
54
57
|
add_reg :rdbuff, 0xC, access: :ro, reset: 0
|
55
58
|
|
56
59
|
reg :abort, options[:abort_select], access: :wo do |reg|
|
@@ -65,5 +68,14 @@ module OrigenARMDebug
|
|
65
68
|
def abort
|
66
69
|
reg(:abort)
|
67
70
|
end
|
71
|
+
|
72
|
+
def is_jtag?
|
73
|
+
true
|
74
|
+
end
|
75
|
+
|
76
|
+
def is_swd?
|
77
|
+
false
|
78
|
+
end
|
79
|
+
alias_method :is_sw?, :is_swd?
|
68
80
|
end
|
69
81
|
end
|
@@ -0,0 +1,86 @@
|
|
1
|
+
module OrigenARMDebug
|
2
|
+
class JTAG_DPV6
|
3
|
+
include Origen::Model
|
4
|
+
|
5
|
+
attr_reader :dpacc_select, :apacc_select
|
6
|
+
|
7
|
+
def initialize(options = {})
|
8
|
+
options = {
|
9
|
+
ir_size: 4,
|
10
|
+
idcode_select: 0b1110,
|
11
|
+
abort_select: 0b1000,
|
12
|
+
dpacc_select: 0b1010,
|
13
|
+
apacc_select: 0b1011
|
14
|
+
}.merge(options)
|
15
|
+
@dpacc_select = options[:dpacc_select]
|
16
|
+
@apacc_select = options[:apacc_select]
|
17
|
+
add_reg :ir, 0, size: options[:ir_size]
|
18
|
+
|
19
|
+
# Virtual reg used to represent all of the various 35-bit scan chains
|
20
|
+
reg :dr, 0, size: 35 do |reg|
|
21
|
+
reg.bit 34..3, :data
|
22
|
+
reg.bit 2..1, :a
|
23
|
+
reg.bit 0, :rnw
|
24
|
+
end
|
25
|
+
|
26
|
+
reg :idcode, options[:idcode_select], access: :ro do |reg|
|
27
|
+
reg.bit 31..28, :version
|
28
|
+
reg.bit 27..12, :partno
|
29
|
+
reg.bit 11..1, :designer
|
30
|
+
reg.bit 0, :bit0, reset: 1
|
31
|
+
end
|
32
|
+
|
33
|
+
reg :ctrlstat, 0x4, dpbanksel: 0 do |reg|
|
34
|
+
reg.bit 31, :csyspwrupack
|
35
|
+
reg.bit 30, :csyspwrupreq
|
36
|
+
reg.bit 29, :cdbgpwrupack
|
37
|
+
reg.bit 28, :cdbgpwrupreq
|
38
|
+
reg.bit 27, :cdbgrstack
|
39
|
+
reg.bit 26, :cdbgrstreq
|
40
|
+
reg.bit 23..12, :trncnt
|
41
|
+
reg.bit 11..8, :masklane
|
42
|
+
reg.bit 7, :wdataerr
|
43
|
+
reg.bit 6, :readok
|
44
|
+
reg.bit 5, :stickyerr
|
45
|
+
reg.bit 4, :stickycmp
|
46
|
+
reg.bit 3..2, :trnmode
|
47
|
+
reg.bit 1, :stickyorun
|
48
|
+
reg.bit 0, :orundetect
|
49
|
+
end
|
50
|
+
|
51
|
+
reg :select, 0x8 do |reg|
|
52
|
+
reg.bit 31..4, :addr
|
53
|
+
reg.bit 3..0, :dpbanksel
|
54
|
+
end
|
55
|
+
|
56
|
+
reg :select1, 0x4, dpbanksel: 5 do |reg|
|
57
|
+
reg.bit 31..0, :addr
|
58
|
+
end
|
59
|
+
|
60
|
+
select.write options[:dp_select_reset] if options[:dp_select_reset]
|
61
|
+
|
62
|
+
add_reg :rdbuff, 0xC, access: :ro, reset: 0
|
63
|
+
|
64
|
+
reg :abort, options[:abort_select], access: :wo do |reg|
|
65
|
+
reg.bit 0, :dapabort
|
66
|
+
end
|
67
|
+
end
|
68
|
+
|
69
|
+
def select
|
70
|
+
reg(:select)
|
71
|
+
end
|
72
|
+
|
73
|
+
def abort
|
74
|
+
reg(:abort)
|
75
|
+
end
|
76
|
+
|
77
|
+
def is_jtag?
|
78
|
+
true
|
79
|
+
end
|
80
|
+
|
81
|
+
def is_swd?
|
82
|
+
false
|
83
|
+
end
|
84
|
+
alias_method :is_sw?, :is_swd?
|
85
|
+
end
|
86
|
+
end
|
@@ -0,0 +1,168 @@
|
|
1
|
+
module OrigenARMDebug
|
2
|
+
class JTAG_DPV6Controller
|
3
|
+
include Origen::Controller
|
4
|
+
include Helpers
|
5
|
+
include DPControllerV6
|
6
|
+
|
7
|
+
def write_register(reg, options = {})
|
8
|
+
unless reg.writable?
|
9
|
+
fail "The :#{reg.name} register is not writeable!"
|
10
|
+
end
|
11
|
+
|
12
|
+
# DP register write
|
13
|
+
if reg.owner == model
|
14
|
+
# Don't log this one, not really a DP reg and will be included
|
15
|
+
# in the JTAG driver log anyway
|
16
|
+
if reg.name == :ir
|
17
|
+
dut.jtag.write_ir(reg)
|
18
|
+
else
|
19
|
+
|
20
|
+
log "Write JTAG-DP register #{reg.name.to_s.upcase}: #{reg.data.to_hex}" do
|
21
|
+
if reg.name == :abort
|
22
|
+
ir.write!(reg.offset)
|
23
|
+
dr.reset
|
24
|
+
dr.overlay(nil)
|
25
|
+
dr[2..0].write(0)
|
26
|
+
dr[34..3].copy_all(reg)
|
27
|
+
dut.jtag.write_dr(dr)
|
28
|
+
|
29
|
+
# DPACC
|
30
|
+
elsif reg.name == :select
|
31
|
+
dp_write(reg)
|
32
|
+
|
33
|
+
# Some other debug register
|
34
|
+
elsif reg.meta.include?(:dpbanksel)
|
35
|
+
if model.reg(:select).bits(:dpbanksel).data != reg.meta[:dpbanksel]
|
36
|
+
model.reg(:select).bits(:dpbanksel).write! reg.meta[:dpbanksel]
|
37
|
+
end
|
38
|
+
dp_write(reg)
|
39
|
+
|
40
|
+
else
|
41
|
+
fail "Can't write #{reg.name}"
|
42
|
+
end
|
43
|
+
end
|
44
|
+
end
|
45
|
+
|
46
|
+
# AP register write
|
47
|
+
else
|
48
|
+
|
49
|
+
unless reg.owner.is_a?(AP)
|
50
|
+
fail 'The JTAG-DP can only write to DP or AP registers!'
|
51
|
+
end
|
52
|
+
|
53
|
+
select_ap_reg(reg)
|
54
|
+
dr.reset
|
55
|
+
dr.overlay(nil)
|
56
|
+
dr[0].write(0)
|
57
|
+
dr[2..1].write(reg.offset >> 2)
|
58
|
+
dr[34..3].copy_all(reg)
|
59
|
+
ir.write!(apacc_select)
|
60
|
+
dut.jtag.write_dr(dr, options)
|
61
|
+
end
|
62
|
+
end
|
63
|
+
|
64
|
+
def read_register(reg, options = {})
|
65
|
+
unless reg.readable?
|
66
|
+
fail "The :#{reg.name} register is not readable!"
|
67
|
+
end
|
68
|
+
|
69
|
+
if reg.owner == model
|
70
|
+
# Don't log this one, not really a DP reg and will be included
|
71
|
+
# in the JTAG driver log anyway
|
72
|
+
if reg.name == :ir
|
73
|
+
dut.jtag.read_ir(reg)
|
74
|
+
else
|
75
|
+
|
76
|
+
log "Read JTAG-DP register #{reg.name.to_s.upcase}: #{Origen::Utility.read_hex(reg)}" do
|
77
|
+
if reg.name == :idcode
|
78
|
+
ir.write!(reg.offset)
|
79
|
+
dut.jtag.read_dr(reg)
|
80
|
+
|
81
|
+
# DPACC
|
82
|
+
elsif reg.name == :select || reg.name == :rdbuff
|
83
|
+
dp_read(reg, options)
|
84
|
+
|
85
|
+
# Some other register
|
86
|
+
elsif reg.meta.include?(:dpbanksel)
|
87
|
+
# Part 1 - Set dpbanksel if required
|
88
|
+
if model.reg(:select).bits(:dpbanksel).data != reg.meta[:dpbanksel]
|
89
|
+
model.reg(:select).bits(:dpbanksel).write! reg.meta[:dpbanksel]
|
90
|
+
end
|
91
|
+
|
92
|
+
dp_read(reg, options)
|
93
|
+
|
94
|
+
else
|
95
|
+
fail "Can't read #{reg.name}"
|
96
|
+
end
|
97
|
+
end
|
98
|
+
end
|
99
|
+
|
100
|
+
# AP register read
|
101
|
+
else
|
102
|
+
unless reg.owner.is_a?(AP)
|
103
|
+
fail 'The JTAG-DP can only write to DP or AP registers!'
|
104
|
+
end
|
105
|
+
|
106
|
+
# Part 1 - Request read from AP-Register by writing to APACC with RnW=1
|
107
|
+
select_ap_reg(reg)
|
108
|
+
dr.reset
|
109
|
+
dr.overlay(nil)
|
110
|
+
dr[0].write(1)
|
111
|
+
dr[2..1].write(reg.offset >> 2)
|
112
|
+
dr[34..3].write(0)
|
113
|
+
ir.write!(apacc_select)
|
114
|
+
dut.jtag.write_dr(dr)
|
115
|
+
|
116
|
+
# Calling AP should provide any delay parameter for wait states between AP read request
|
117
|
+
# and when the data is available at the RDBUFF DP-Reg
|
118
|
+
if options[:apacc_wait_states]
|
119
|
+
options[:apacc_wait_states].cycles
|
120
|
+
end
|
121
|
+
|
122
|
+
# Part 2 - Now read real data from RDBUFF (DP-Reg)
|
123
|
+
dr.reset
|
124
|
+
dr.overlay(nil)
|
125
|
+
dr[0].write(1)
|
126
|
+
dr[2..1].write(rdbuff.offset >> 2)
|
127
|
+
dr[34..3].copy_all(reg)
|
128
|
+
options[:mask] = options[:mask] << 3 unless options[:mask].nil?
|
129
|
+
ir.write!(dpacc_select)
|
130
|
+
dut.jtag.read_dr(dr, options)
|
131
|
+
end
|
132
|
+
end
|
133
|
+
|
134
|
+
def dp_read(reg, options = {})
|
135
|
+
# Part 1 - Request read from DP-Register by writing to DPACC with RnW=1
|
136
|
+
dr.reset
|
137
|
+
dr.overlay(nil)
|
138
|
+
dr[0].write(1)
|
139
|
+
dr[2..1].write(reg.offset >> 2)
|
140
|
+
dr[34..3].write(0)
|
141
|
+
ir.write!(dpacc_select)
|
142
|
+
dut.jtag.write_dr(dr)
|
143
|
+
|
144
|
+
# Part 2 - Now read real data from RDBUFF (DP-Reg)
|
145
|
+
dr.reset
|
146
|
+
dr.overlay(nil)
|
147
|
+
dr[0].write(1)
|
148
|
+
dr[2..1].write(rdbuff.offset >> 2)
|
149
|
+
dr[34..3].copy_all(reg)
|
150
|
+
options[:mask] = options[:mask] << 3 unless options[:mask].nil?
|
151
|
+
dut.jtag.read_dr(dr, options)
|
152
|
+
end
|
153
|
+
|
154
|
+
def dp_write(reg)
|
155
|
+
dr.reset
|
156
|
+
dr.overlay(nil)
|
157
|
+
dr[0].write(0)
|
158
|
+
dr[2..1].write(reg.offset >> 2)
|
159
|
+
dr[34..3].copy_all(reg)
|
160
|
+
ir.write!(dpacc_select)
|
161
|
+
dut.jtag.write_dr(dr)
|
162
|
+
end
|
163
|
+
|
164
|
+
def base_address
|
165
|
+
model.base_address
|
166
|
+
end
|
167
|
+
end
|
168
|
+
end
|
@@ -14,21 +14,52 @@ module OrigenARMDebug
|
|
14
14
|
# For SWD, this is the wait states in between setting the AP, initiating and completing a dummy read, and beginning the actual read transaction.
|
15
15
|
attr_accessor :apacc_wait_states
|
16
16
|
|
17
|
+
# Boolean value indicating whether this is an AXI-AP
|
18
|
+
attr_accessor :is_axi
|
19
|
+
|
20
|
+
# Value to be read from DP CSW for interleaved status checks (debug feature)
|
21
|
+
attr_accessor :csw_status_check
|
22
|
+
|
23
|
+
# Boolean value indicating whether to interleave status checks during transactions (debug feature)
|
24
|
+
attr_accessor :interleave_status_check
|
25
|
+
|
17
26
|
def initialize(options = {})
|
18
27
|
super
|
19
28
|
|
29
|
+
@is_axi = options[:is_axi]
|
30
|
+
@csw_status_check = options[:csw_status_check]
|
31
|
+
@interleave_status_check = options[:interleave_status_check]
|
32
|
+
|
20
33
|
@latency = options[:latency] || 0
|
21
34
|
@apmem_access_wait = options[:apmem_access_wait] || 0
|
22
35
|
|
23
|
-
|
24
|
-
reg
|
25
|
-
|
26
|
-
|
27
|
-
|
28
|
-
|
29
|
-
|
30
|
-
|
31
|
-
|
36
|
+
if @is_axi
|
37
|
+
reg :csw, 0x0 do |reg|
|
38
|
+
reg.bit 31, :reserved
|
39
|
+
reg.bit 30..28, :prot, res: 3
|
40
|
+
reg.bit 27..24, :cache
|
41
|
+
reg.bit 23, :spiden
|
42
|
+
reg.bit 22..15, :reserved2
|
43
|
+
reg.bit 14..13, :domain, res: 3
|
44
|
+
reg.bit 12, :ace_enable
|
45
|
+
reg.bit 11..8, :mode
|
46
|
+
reg.bit 7, :tr_in_prog
|
47
|
+
reg.bit 6, :dbg_status, res: 1
|
48
|
+
reg.bit 5..4, :addr_inc
|
49
|
+
reg.bit 3, :reserved3
|
50
|
+
reg.bit 2..0, :size, res: 2
|
51
|
+
end
|
52
|
+
else
|
53
|
+
reg :csw, 0x0 do |reg|
|
54
|
+
reg.bit 31, :dbg_sw_enable
|
55
|
+
reg.bit 30..24, :prot
|
56
|
+
reg.bit 23, :spiden
|
57
|
+
reg.bit 11..8, :mode
|
58
|
+
reg.bit 7, :tr_in_prog
|
59
|
+
reg.bit 6, :device_en
|
60
|
+
reg.bit 5..4, :addr_inc
|
61
|
+
reg.bit 2..0, :size
|
62
|
+
end
|
32
63
|
end
|
33
64
|
reg(:csw).write(options[:csw_reset]) if options[:csw_reset]
|
34
65
|
|
@@ -18,11 +18,13 @@ module OrigenARMDebug
|
|
18
18
|
log "Write MEM-AP (#{model.name}) address #{addr.to_hex}: #{data.to_hex}" do
|
19
19
|
csw.bits(:size).write!(0b010) if csw.bits(:size).data != 0b010
|
20
20
|
tar.write!(addr) unless tar.data == addr
|
21
|
+
parent.dp.ctrlstat.read! model.csw_status_check if model.interleave_status_check
|
21
22
|
drw.reset
|
22
23
|
drw.overlay(nil)
|
23
24
|
drw.copy_all(reg_or_val)
|
24
25
|
drw.write!(options)
|
25
26
|
latency.cycles
|
27
|
+
parent.dp.ctrlstat.read! model.csw_status_check if model.interleave_status_check
|
26
28
|
end
|
27
29
|
increment_addr
|
28
30
|
end
|
@@ -43,11 +45,13 @@ module OrigenARMDebug
|
|
43
45
|
csw.bits(:size).write!(0b010) if csw.bits(:size).data != 0b010
|
44
46
|
unless tar.data == addr
|
45
47
|
tar.write!(addr)
|
48
|
+
parent.dp.ctrlstat.read! model.csw_status_check if model.interleave_status_check
|
46
49
|
end
|
47
50
|
drw.reset
|
48
51
|
drw.overlay(nil)
|
49
52
|
drw.copy_all(reg_or_val)
|
50
53
|
parent.dp.read_register(drw, options.merge(apacc_wait_states: (apmem_access_wait + apreg_access_wait)))
|
54
|
+
parent.dp.ctrlstat.read! model.csw_status_check if model.interleave_status_check
|
51
55
|
end
|
52
56
|
increment_addr
|
53
57
|
end
|
data/lib/origen_arm_debug.rb
CHANGED
@@ -8,8 +8,11 @@ module OrigenARMDebug
|
|
8
8
|
require 'origen_arm_debug/dap'
|
9
9
|
require 'origen_arm_debug/dap_controller'
|
10
10
|
require 'origen_arm_debug/dp_controller'
|
11
|
+
require 'origen_arm_debug/dp_controller_v6'
|
11
12
|
require 'origen_arm_debug/jtag_dp'
|
12
13
|
require 'origen_arm_debug/jtag_dp_controller'
|
14
|
+
require 'origen_arm_debug/jtag_dp_v6'
|
15
|
+
require 'origen_arm_debug/jtag_dp_v6_controller'
|
13
16
|
require 'origen_arm_debug/sw_dp'
|
14
17
|
require 'origen_arm_debug/sw_dp_controller'
|
15
18
|
require 'origen_arm_debug/ap'
|
@@ -0,0 +1,34 @@
|
|
1
|
+
module OrigenARMDebugDev
|
2
|
+
# Simple JTAG-specific dut model that inherits from protocol-agnostic DUT model
|
3
|
+
class DUAL_DP_DUT < DUT
|
4
|
+
include OrigenSWD
|
5
|
+
include OrigenJTAG
|
6
|
+
|
7
|
+
# Adds jtag-required pins to the simple dut model
|
8
|
+
# Returns nothing.
|
9
|
+
def initialize(options = {})
|
10
|
+
super
|
11
|
+
add_pin :tclk
|
12
|
+
add_pin :tdi
|
13
|
+
add_pin :tdo
|
14
|
+
add_pin :tms
|
15
|
+
add_pin :trst
|
16
|
+
add_pin :swd_clk
|
17
|
+
add_pin :swd_dio
|
18
|
+
|
19
|
+
options[:class_name] = 'OrigenARMDebug::DAP'
|
20
|
+
options[:mem_aps] = {
|
21
|
+
mem_ap: {
|
22
|
+
base_address: 0x00000000,
|
23
|
+
latency: 16,
|
24
|
+
apreg_access_wait: 8,
|
25
|
+
apmem_access_wait: 8,
|
26
|
+
csw_reset: 0x23000040
|
27
|
+
},
|
28
|
+
mdm_ap: 0x01000000
|
29
|
+
}
|
30
|
+
# Specify (customize) ARM Debug implementation details
|
31
|
+
sub_block :arm_debug, options
|
32
|
+
end
|
33
|
+
end
|
34
|
+
end
|
@@ -0,0 +1,50 @@
|
|
1
|
+
module OrigenARMDebugDev
|
2
|
+
# Simple JTAG-specific dut model that inherits from protocol-agnostic DUT model
|
3
|
+
class JTAG_AXI_DUT < DUT
|
4
|
+
include OrigenJTAG
|
5
|
+
|
6
|
+
# Adds jtag-required pins to the simple dut model
|
7
|
+
# Returns nothing.
|
8
|
+
def initialize(options = {})
|
9
|
+
super
|
10
|
+
add_pin :tclk
|
11
|
+
add_pin :tdi
|
12
|
+
add_pin :tdo
|
13
|
+
add_pin :tms
|
14
|
+
add_pin :trst
|
15
|
+
add_pin :swd_clk
|
16
|
+
add_pin :swd_dio
|
17
|
+
|
18
|
+
options[:class_name] = 'OrigenARMDebug::DAP'
|
19
|
+
options[:mem_aps] = {
|
20
|
+
mem_ap: {
|
21
|
+
base_address: 0x00000000,
|
22
|
+
latency: 16,
|
23
|
+
apreg_access_wait: 8,
|
24
|
+
apmem_access_wait: 8,
|
25
|
+
is_axi: true,
|
26
|
+
csw_reset: 0x1080_6002
|
27
|
+
},
|
28
|
+
mdm_ap: 0x01000000
|
29
|
+
}
|
30
|
+
options[:dp_select_reset] = 0xC2_0D00
|
31
|
+
# Specify (customize) ARM Debug implementation details
|
32
|
+
sub_block :arm_debug, options
|
33
|
+
|
34
|
+
options[:dapv6] = true
|
35
|
+
options[:class_name] = 'OrigenARMDebug::DAP'
|
36
|
+
options[:mem_aps] = {
|
37
|
+
mem_ap: {
|
38
|
+
base_address: 0x00C2_0000,
|
39
|
+
latency: 16,
|
40
|
+
apreg_access_wait: 8,
|
41
|
+
apmem_access_wait: 8,
|
42
|
+
is_axi: true,
|
43
|
+
csw_reset: 0x1080_6002
|
44
|
+
},
|
45
|
+
mdm_ap: 0x00C3_0000
|
46
|
+
}
|
47
|
+
sub_block :arm_debugv6, options
|
48
|
+
end
|
49
|
+
end
|
50
|
+
end
|
@@ -0,0 +1,114 @@
|
|
1
|
+
pattern_name = "v6_workout_#{dut.arm_debugv6.dp.name}"
|
2
|
+
|
3
|
+
Pattern.create name: pattern_name do
|
4
|
+
|
5
|
+
ss "Tests of direct DP API"
|
6
|
+
dp = dut.arm_debugv6.dp
|
7
|
+
|
8
|
+
dp.idcode.partno.read!(0x12)
|
9
|
+
|
10
|
+
dp.ctrlstat.write!(0x50000000)
|
11
|
+
dp.ctrlstat.read!(0xF0000000)
|
12
|
+
|
13
|
+
dp.select.bits(:addr).write!(0xF)
|
14
|
+
dp.select.read!
|
15
|
+
dp.select1.write! 4
|
16
|
+
dp.select1.read! 4
|
17
|
+
|
18
|
+
dp.abort.dapabort.write!(1)
|
19
|
+
|
20
|
+
ss "Tests of direct AP API"
|
21
|
+
ap = dut.arm_debugv6.mem_ap
|
22
|
+
|
23
|
+
ap.tar.write!(0x1234_0000)
|
24
|
+
|
25
|
+
ap.tar.read!
|
26
|
+
|
27
|
+
ss "Tests of high-level register API"
|
28
|
+
|
29
|
+
ss "Test write register, should write value 0xFF01"
|
30
|
+
dut.reg(:test).write!(0x0000FF01)
|
31
|
+
|
32
|
+
ss "Test write register with overlay, no subroutine"
|
33
|
+
dut.reg(:test).overlay('write_overlay')
|
34
|
+
dut.reg(:test).write!(0x0000FF01, no_subr: true)
|
35
|
+
dut.reg(:test).overlay(nil)
|
36
|
+
|
37
|
+
ss "Test write register with overlay, use subroutine if available"
|
38
|
+
dut.reg(:test).overlay('write_overlay_subr')
|
39
|
+
dut.reg(:test).write!(0x0000FF01)
|
40
|
+
dut.reg(:test).overlay(nil)
|
41
|
+
|
42
|
+
ss "Test read register, should read value 0x0000FF01"
|
43
|
+
dut.reg(:test).read!
|
44
|
+
|
45
|
+
ss "Test read register, with overlay, no subroutine, should read value 0x0000FF01"
|
46
|
+
dut.reg(:test).overlay('read_overlay')
|
47
|
+
dut.reg(:test).read!(no_subr: true)
|
48
|
+
dut.reg(:test).overlay(nil)
|
49
|
+
|
50
|
+
ss "Test read register, with overlay, use subroutine if available"
|
51
|
+
dut.reg(:test).overlay('read_overlay_subr')
|
52
|
+
dut.reg(:test).read!
|
53
|
+
dut.reg(:test).overlay(nil)
|
54
|
+
|
55
|
+
ss "Test read register with mask, should read value 0xXXXxxx1"
|
56
|
+
dut.reg(:test).read!(mask: 0x0000_000F)
|
57
|
+
|
58
|
+
ss "Test read register with store"
|
59
|
+
dut.reg(:test).store!
|
60
|
+
|
61
|
+
ss "Test bit level read, should read value 0xXXXxxx1"
|
62
|
+
dut.reg(:test).reset
|
63
|
+
dut.reg(:test).data = 0x0000FF01
|
64
|
+
dut.reg(:test)[0].read!
|
65
|
+
|
66
|
+
if Origen.app.target.name == 'dual_dp'
|
67
|
+
ss "SWITCHING DP"
|
68
|
+
dut.arm_debugv6.set_dp(:jtag)
|
69
|
+
|
70
|
+
ss "Test write register, should write value 0xFF01"
|
71
|
+
dut.reg(:test).write!(0x0000FF01)
|
72
|
+
|
73
|
+
ss "Test write register with overlay, no subroutine"
|
74
|
+
dut.reg(:test).overlay('write_overlay')
|
75
|
+
dut.reg(:test).write!(0x0000FF01, no_subr: true)
|
76
|
+
dut.reg(:test).overlay(nil)
|
77
|
+
|
78
|
+
ss "Test write register with overlay, use subroutine if available"
|
79
|
+
dut.reg(:test).overlay('write_overlay_subr')
|
80
|
+
dut.reg(:test).write!(0x0000FF01)
|
81
|
+
dut.reg(:test).overlay(nil)
|
82
|
+
|
83
|
+
ss "Test read register, should read value 0x0000FF01"
|
84
|
+
dut.reg(:test).read!
|
85
|
+
|
86
|
+
ss "Test read register, with overlay, no subroutine, should read value 0x0000FF01"
|
87
|
+
dut.reg(:test).overlay('read_overlay')
|
88
|
+
dut.reg(:test).read!(no_subr: true)
|
89
|
+
dut.reg(:test).overlay(nil)
|
90
|
+
|
91
|
+
ss "Test read register, with overlay, use subroutine if available"
|
92
|
+
dut.reg(:test).overlay('read_overlay_subr')
|
93
|
+
dut.reg(:test).read!
|
94
|
+
dut.reg(:test).overlay(nil)
|
95
|
+
|
96
|
+
ss "Test read register with mask, should read value 0xXXXxxx1"
|
97
|
+
dut.reg(:test).read!(mask: 0x0000_000F)
|
98
|
+
|
99
|
+
ss "Test read register with store"
|
100
|
+
dut.reg(:test).store!
|
101
|
+
|
102
|
+
ss "Test bit level read, should read value 0xXXXxxx1"
|
103
|
+
dut.reg(:test).reset
|
104
|
+
dut.reg(:test).data = 0x0000FF01
|
105
|
+
dut.reg(:test)[0].read!
|
106
|
+
|
107
|
+
ss "RESETTING DP (to default)"
|
108
|
+
dut.arm_debugv6.reset_dp
|
109
|
+
ss "Test bit level read, should read value 0xXXXxxx1"
|
110
|
+
dut.reg(:test).reset
|
111
|
+
dut.reg(:test).data = 0x0000FF01
|
112
|
+
dut.reg(:test)[0].read!
|
113
|
+
end
|
114
|
+
end
|
data/pattern/workout.rb
CHANGED
@@ -1,4 +1,12 @@
|
|
1
|
-
|
1
|
+
if Origen.app.target.name == 'dual_dp'
|
2
|
+
pattern_name = 'workout_dual_dp'
|
3
|
+
elsif Origen.app.target.name == 'jtag_axi'
|
4
|
+
pattern_name = 'workout_jtag_axi'
|
5
|
+
else
|
6
|
+
pattern_name = "workout_#{dut.arm_debug.dp.name}"
|
7
|
+
end
|
8
|
+
|
9
|
+
Pattern.create name: pattern_name do
|
2
10
|
|
3
11
|
ss "Tests of direct DP API"
|
4
12
|
dp = dut.arm_debug.dp
|
@@ -8,7 +16,11 @@ Pattern.create name: "workout_#{dut.arm_debug.dp.name}" do
|
|
8
16
|
dp.ctrlstat.write!(0x50000000)
|
9
17
|
dp.ctrlstat.read!(0xF0000000)
|
10
18
|
|
11
|
-
dp.select.apbanksel
|
19
|
+
if dp.select.has_bits?(:apbanksel)
|
20
|
+
dp.select.apbanksel.write!(0xF)
|
21
|
+
else
|
22
|
+
dp.select.bits(31..24).write!(0xF)
|
23
|
+
end
|
12
24
|
|
13
25
|
dp.abort.dapabort.write!(1)
|
14
26
|
|
@@ -58,4 +70,52 @@ Pattern.create name: "workout_#{dut.arm_debug.dp.name}" do
|
|
58
70
|
dut.reg(:test).data = 0x0000FF01
|
59
71
|
dut.reg(:test)[0].read!
|
60
72
|
|
73
|
+
if Origen.app.target.name == 'dual_dp'
|
74
|
+
ss "SWITCHING DP"
|
75
|
+
dut.arm_debug.set_dp(:jtag)
|
76
|
+
|
77
|
+
ss "Test write register, should write value 0xFF01"
|
78
|
+
dut.reg(:test).write!(0x0000FF01)
|
79
|
+
|
80
|
+
ss "Test write register with overlay, no subroutine"
|
81
|
+
dut.reg(:test).overlay('write_overlay')
|
82
|
+
dut.reg(:test).write!(0x0000FF01, no_subr: true)
|
83
|
+
dut.reg(:test).overlay(nil)
|
84
|
+
|
85
|
+
ss "Test write register with overlay, use subroutine if available"
|
86
|
+
dut.reg(:test).overlay('write_overlay_subr')
|
87
|
+
dut.reg(:test).write!(0x0000FF01)
|
88
|
+
dut.reg(:test).overlay(nil)
|
89
|
+
|
90
|
+
ss "Test read register, should read value 0x0000FF01"
|
91
|
+
dut.reg(:test).read!
|
92
|
+
|
93
|
+
ss "Test read register, with overlay, no subroutine, should read value 0x0000FF01"
|
94
|
+
dut.reg(:test).overlay('read_overlay')
|
95
|
+
dut.reg(:test).read!(no_subr: true)
|
96
|
+
dut.reg(:test).overlay(nil)
|
97
|
+
|
98
|
+
ss "Test read register, with overlay, use subroutine if available"
|
99
|
+
dut.reg(:test).overlay('read_overlay_subr')
|
100
|
+
dut.reg(:test).read!
|
101
|
+
dut.reg(:test).overlay(nil)
|
102
|
+
|
103
|
+
ss "Test read register with mask, should read value 0xXXXxxx1"
|
104
|
+
dut.reg(:test).read!(mask: 0x0000_000F)
|
105
|
+
|
106
|
+
ss "Test read register with store"
|
107
|
+
dut.reg(:test).store!
|
108
|
+
|
109
|
+
ss "Test bit level read, should read value 0xXXXxxx1"
|
110
|
+
dut.reg(:test).reset
|
111
|
+
dut.reg(:test).data = 0x0000FF01
|
112
|
+
dut.reg(:test)[0].read!
|
113
|
+
|
114
|
+
ss "RESETTING DP (to default)"
|
115
|
+
dut.arm_debug.reset_dp
|
116
|
+
ss "Test bit level read, should read value 0xXXXxxx1"
|
117
|
+
dut.reg(:test).reset
|
118
|
+
dut.reg(:test).data = 0x0000FF01
|
119
|
+
dut.reg(:test)[0].read!
|
120
|
+
end
|
61
121
|
end
|
data/templates/web/index.md.erb
CHANGED
@@ -52,7 +52,7 @@ class DUT
|
|
52
52
|
|
53
53
|
# Simple example using default wait-states and latency:
|
54
54
|
# mem_ap: APSEL = 0x00 (base_address[31:24])
|
55
|
-
# mem2_ap: APSEL = 0x01 (base_address[31:24])
|
55
|
+
# mem2_ap: APSEL = 0x01 (base_address[31:24], is_axi: true) # is_axi: true for AXI-AP
|
56
56
|
mem_aps = {
|
57
57
|
mem_ap: { base_address: 0x00000000 },
|
58
58
|
mem2_ap: { base_address: 0x10000000 }
|
@@ -133,6 +133,22 @@ instantiation_options[:idcode_select] = 0xFE
|
|
133
133
|
instantiation_options[:abort_select] = 0xF8
|
134
134
|
instantiation_options[:dpacc_select] = 0xFA
|
135
135
|
instantiation_options[:apacc_select] = 0xFB
|
136
|
+
instantiation_options[:dp_select_reset] = 0xC2_0D00
|
137
|
+
|
138
|
+
sub_block :arm_debug, instantiation_options
|
139
|
+
~~~
|
140
|
+
|
141
|
+
DAP Version 6 instantiation example:
|
142
|
+
|
143
|
+
~~~ruby
|
144
|
+
mem_aps = {
|
145
|
+
mem_ap: { base_address: 0x001C_1000 }
|
146
|
+
mem2_ap: { base_address: 0x001C_2000 }
|
147
|
+
}
|
148
|
+
instantiation_options[:class_name] = 'OrigenARMDebug::DAP'
|
149
|
+
instantiation_options[:mem_aps] = mem_aps
|
150
|
+
|
151
|
+
instantiation_options[:dapv6] = true
|
136
152
|
|
137
153
|
sub_block :arm_debug, instantiation_options
|
138
154
|
~~~
|
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: origen_arm_debug
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 1.
|
4
|
+
version: 1.3.0
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Ronnie Lajaunie
|
8
8
|
autorequire:
|
9
9
|
bindir: bin
|
10
10
|
cert_chain: []
|
11
|
-
date:
|
11
|
+
date: 2022-02-28 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: origen
|
@@ -87,18 +87,24 @@ files:
|
|
87
87
|
- lib/origen_arm_debug/dap.rb
|
88
88
|
- lib/origen_arm_debug/dap_controller.rb
|
89
89
|
- lib/origen_arm_debug/dp_controller.rb
|
90
|
+
- lib/origen_arm_debug/dp_controller_v6.rb
|
90
91
|
- lib/origen_arm_debug/helpers.rb
|
91
92
|
- lib/origen_arm_debug/jtag_ap.rb
|
92
93
|
- lib/origen_arm_debug/jtag_ap_controller.rb
|
93
94
|
- lib/origen_arm_debug/jtag_dp.rb
|
94
95
|
- lib/origen_arm_debug/jtag_dp_controller.rb
|
96
|
+
- lib/origen_arm_debug/jtag_dp_v6.rb
|
97
|
+
- lib/origen_arm_debug/jtag_dp_v6_controller.rb
|
95
98
|
- lib/origen_arm_debug/mem_ap.rb
|
96
99
|
- lib/origen_arm_debug/mem_ap_controller.rb
|
97
100
|
- lib/origen_arm_debug/sw_dp.rb
|
98
101
|
- lib/origen_arm_debug/sw_dp_controller.rb
|
99
102
|
- lib/origen_arm_debug_dev/dut.rb
|
103
|
+
- lib/origen_arm_debug_dev/dut_dual_dp.rb
|
100
104
|
- lib/origen_arm_debug_dev/dut_jtag.rb
|
105
|
+
- lib/origen_arm_debug_dev/dut_jtag_axi.rb
|
101
106
|
- lib/origen_arm_debug_dev/dut_swd.rb
|
107
|
+
- pattern/v6_workout.rb
|
102
108
|
- pattern/workout.rb
|
103
109
|
- templates/web/index.md.erb
|
104
110
|
- templates/web/layouts/_basic.html.erb
|
@@ -123,8 +129,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
|
|
123
129
|
- !ruby/object:Gem::Version
|
124
130
|
version: 1.8.11
|
125
131
|
requirements: []
|
126
|
-
|
127
|
-
rubygems_version: 2.7.7
|
132
|
+
rubygems_version: 3.1.4
|
128
133
|
signing_key:
|
129
134
|
specification_version: 4
|
130
135
|
summary: Provides an Origen API to perform register read and write operations via
|