origen_arm_debug 0.6.0 → 0.7.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA1:
-  metadata.gz: 2e004df0c8d145be274dae133a25750de5d4775d
-  data.tar.gz: 661b0086a39ef3e4287cd97e7c551ee35f81fc01
+  metadata.gz: 528eb3303524b33d1916c73c72a003e9ab5b2880
+  data.tar.gz: fb08b4c3360b61dc8732ad9bcf6065896fc638c3
 SHA512:
-  metadata.gz: f3b76b470b1247868e15f9fafd851401fa747b504df323ffb3d9c593c18401ce8ad69da7b4b92c4f38a994b7483d78c22a1c37b6d2a81f0368ce4e327244d043
-  data.tar.gz: b09cb03684e736f2f7f9adc80ae8dc05f35ae03771b4bbcabca4aebfc04442daf8532a9eb4e97cb1dfca95c69466c0034317f579188cbb9690b16e652dbc8127
+  metadata.gz: 19abcb44c8b1fed4d00f1cab8828dccd640b2ee2bdf0f903867fd179e720e5d1ada1fcaf57691735238e606eac71237ee0cbc0f0991840b533e82433b4005345
+  data.tar.gz: a8daf8a46d1d3f2c9c68bc66a1ab94aa828c074e24e7d05e26749cd774bca47a30b8fc57bda31b08614a05e05925b2639efb080408fb8afa02c7c90b5f304d1b

data/config/application.rb

@@ -30,7 +30,7 @@ class OrigenARMDebugApplication < Origen::Application
   
   # Ensure that all tests pass before allowing a release to continue 
   def validate_release 
-    if !system("origen examples") #|| !system("origen specs") 
+    if !system("origen examples") || !system("origen specs") 
       puts "Sorry but you can't release with failing tests, please fix them and try again." 
       exit 1 
     else 

data/config/commands.rb

@@ -17,6 +17,10 @@ aliases ={
 # Now branch to the specific task code
 case @command
 
+when "specs"
+  require "rspec"
+  exit RSpec::Core::Runner.run(['spec'])
+
 when "examples"  
   Origen.load_application
   status = 0
@@ -49,6 +53,7 @@ when "examples"
 # before handing control back to Origen. Un-comment the example below to get started.
 else
   @application_commands = <<-EOT
+ specs        Run the specs (unit tests), -c will enable coverage
  examples     Run the examples (tests), -c will enable coverage
   EOT
 

data/config/version.rb

@@ -1,6 +1,6 @@
 module OrigenARMDebug
   MAJOR = 0
-  MINOR = 6
+  MINOR = 7
   BUGFIX = 0
   DEV = nil
 

data/lib/origen_arm_debug/driver.rb

@@ -56,7 +56,12 @@ module OrigenARMDebug
     #   the cycles corresponding to those bits only (don't care cycles will be generated for the others).
     # @param [Hash] options Options to customize the operation
     def read_register(reg_or_val, options = {})
-      mem_ap.read(reg_or_val.address, size: reg_or_val.size, compare_data: reg_or_val.data)
+      if options[:ap].nil?
+        ap = mem_ap           # default to 'mem_ap' if no AP is specified as an option
+      else
+        ap = options[:ap]
+      end
+      ap.read_register(reg_or_val, options)
     end
 
     # Write data to a MEM-AP register
@@ -67,7 +72,16 @@ module OrigenARMDebug
     #   the cycles corresponding to those bits only (don't care cycles will be generated for the others).
     # @param [Hash] options Options to customize the operation
     def write_register(reg_or_val, options = {})
-      mem_ap.write(reg_or_val.address, reg_or_val.data, size: reg_or_val.size)
+      if options[:ap].nil?
+        ap = mem_ap           # default to 'mem_ap' if no AP is specified as an option
+      else
+        ap = options[:ap]
+      end
+      ap.write_register(reg_or_val, options)
+    end
+
+    def inspect_driver
+      Origen.log.info "ARM Debug Driver = #{arm_debug_driver}"
     end
 
     private

data/lib/origen_arm_debug/mem_ap.rb

@@ -65,6 +65,55 @@ module OrigenARMDebug
     # -----------------------------------------------------------------------------
     # User API
     # -----------------------------------------------------------------------------
+    def read_register(reg_or_val, options = {})
+      if reg_or_val.respond_to?(:data)
+        addr = reg_or_val.addr
+        options = { reg: reg_or_val }.merge(options)
+      else
+        addr = reg_or_val                 # if not a register, use the 'val' as target addr
+      end
+
+      options = { size: 32 }.merge(options)
+      options = { r_mask: 'mask', r_attempts: 1 }.merge(options)
+      msg = 'Arm Debug: Shift out data for reading'
+      options = { arm_debug_comment: msg }.merge(options)
+      size = options[:size]
+
+      set_size(size)
+      set_addr(addr)
+      debug_port.read_ap(drw_reg_addr, options)
+      rdata = get_rdata(size, addr, rdata)
+      increment_addr
+
+      cc "MEM-AP(#{@name}): R-#{size.to_s(10)}: "\
+        "addr=0x#{addr.to_s(16).rjust(size / 4, '0')}"
+    end
+
+    def write_register(reg_or_val, options = {});
+      if reg_or_val.respond_to?(:data)
+        addr = reg_or_val.addr
+        wdata = reg_or_val.data
+        options = { reg: reg_or_val }.merge(options)
+      else
+        addr = reg_or_val                 # if not a register, use the 'val' as target addr
+        wdata = options[:wdata]
+      end
+      options = { size: 32 }.merge(options)
+      options = { w_attempts: 1 }.merge(options)
+      msg = "Arm Debug: Shift in data to write: #{wdata.to_hex}"
+      options = { arm_debug_comment: msg }.merge(options)
+      size = options[:size]
+
+      set_size(size)
+      set_addr(addr)
+      wdata = get_wdata(size, addr, wdata)
+      debug_port.write_ap(drw_reg_addr, wdata, options)
+      increment_addr
+
+      cc "MEM-AP(#{@name}): WR-#{size.to_s(10)}: "\
+        "addr=0x#{addr.to_s(16).rjust(size / 4, '0')}, "\
+        "data=0x#{wdata.to_s(16).rjust(size / 4, '0')}"
+    end
 
     # Method to read from a mem_ap register
     #

data/lib/origen_arm_debug/swj_dp.rb

@@ -34,10 +34,7 @@ module OrigenARMDebug
         @imp = implementation
       else
         msg = "SWJ-DP: '#{implementation}' implementation not supported.  JTAG and SWD only"
-        Origen.log.error msg
-
-        # Just default to jtag for now
-        @imp = :jtag
+        fail msg
       end
 
       @write_ap_dly = 8
@@ -145,7 +142,7 @@ module OrigenARMDebug
       # Create another copy of options with select keys removed.
       # This first read is junk so we do not want to store it or compare it.
       junk_options = options.clone.delete_if do |key, val|
-        (key.eql?(:r_mask) && val.eql?('store')) || key.eql?(:compare_data)
+        (key.eql?(:r_mask) && val.eql?('store')) || key.eql?(:compare_data) || key.eql?(:reg)
       end
 
       apacc_access(addr, rwb, random, 0, junk_options)
@@ -165,7 +162,7 @@ module OrigenARMDebug
     # @param [Hash] options Options to customize the operation
     def read_expect_ap(addr, edata, options = {})
       options[:edata] = edata
-      read_ap(name, options)
+      read_ap(addr, options)
     end
     alias_method :wait_read_expect_ap, :read_expect_ap
 
@@ -339,9 +336,9 @@ module OrigenARMDebug
     # @param [Hash] options Options to customize the operation
     def acc_access(addr, rwb, ap_dp, wdata, options = {})
       if @imp == :swd
-        acc_access_swd(addr, rwb, ap_dp, wdata, options = {})
+        acc_access_swd(addr, rwb, ap_dp, wdata, options)
       else
-        acc_access_jtag(addr, rwb, ap_dp, wdata, options = {})
+        acc_access_jtag(addr, rwb, ap_dp, wdata, options)
       end
     end
 
@@ -354,7 +351,13 @@ module OrigenARMDebug
     # @param [Hash] options Options to customize the operation
     def acc_access_swd(addr, rwb, ap_dp, wdata, options = {})
       if (rwb == 1)
-        swd.read(ap_dp, addr, options)
+        if options[:reg].nil?
+          swd.read(ap_dp, addr, options)
+        else
+          # make sure reg.addr = addr
+          Origen.log.error 'SWJ_DP ERROR: In acc_access_swd, addr does not match options[:reg].addr'
+          swd.read(ap_dp, options[:reg], options)
+        end
       else
         swd.write(ap_dp, addr, wdata, options)
       end
@@ -379,12 +382,27 @@ module OrigenARMDebug
       end
 
       attempts.times do
-        if name == 'RDBUFF'
-          r = $dut.reg(:dap)
-          if options[:r_mask] == 'store'
-            r.bits(3..34).store
-          elsif options.key?(:compare_data)
-            r.bits(3..34).data = options[:compare_data]
+        if rwb == 1
+          if options[:reg].nil?
+            r = $dut.reg(:dap)
+            if options[:r_mask] == 'store'
+              r.bits(3..34).store
+            elsif options.key?(:compare_data)
+              r.bits(3..34).data = options[:compare_data]
+            elsif options.key?(:edata)
+              options[:compare_data] = options[:edata]
+              r.bits(3..34).data = options[:edata]
+            end
+          else
+            r = $dut.reg(:dap)
+            r.reset
+            r.bits(3..34).data = options[:reg].data
+            (3..34).each do |i|
+              r.bits(i).read if options[:reg].bits(i - 3).is_to_be_read?
+            end
+            (3..34).each do |i|
+              r.bits(i).store if options[:reg].bits(i - 3).is_to_be_stored?
+            end
           end
 
           options = options.merge(size: r.size)

data/pattern/read_write_reg.rb

@@ -1,17 +1,29 @@
 Pattern.create do
 
   ss "Test write register, should write value 0xFF01"
-  $dut.reg(:test).write!(0xFF01)
-  ss "Test read register, should read value 0xFF01"
+  $dut.reg(:test).write!(0x0000FF01)
+
+  ss "Test read register, should read value 0x0000FF01"
   $dut.reg(:test).read!
+
+  ss "Test read register with mask, should read value 0xXXXxxx1"
+  $dut.reg(:test).read!(mask: 0x0000_000F)
+
+  ss "Test read register with store"
+  $dut.reg(:test).store!
+
   ss "Test bit level read, should read value 0xXXXxxx1"
+  $dut.reg(:test).reset
+  $dut.reg(:test).data = 0x0000FF01
   $dut.reg(:test).bit(:bit).read!
 
-
+  ss "Test read register"
   $dut.read_register($dut.reg(:test))
-  $dut.write_register($dut.reg(:test), 0xFF02)
 
-  $dut.arm_debug.mem_ap.R(0x10000004, 0x00000000)
+  ss "Test write register"
+  $dut.write_register($dut.reg(:test))
+
+  $dut.arm_debug.mem_ap.R(0x10000004, 0x00000000, compare_data: 0x00000000)
   $dut.arm_debug.mem_ap.W(0x10000004, 0x55555555)
   $dut.arm_debug.mem_ap.WR(0x10000004, 0x55555555)
 

data/pattern/read_write_reg_jtag.rb

@@ -5,6 +5,6 @@ Pattern.create do
   $dut_jtag.arm_debug.swj_dp.write_read_dp("CTRL/STAT", 0x50000000, edata: 0xf0000000)
   $dut_jtag.arm_debug.swj_dp.read_ap(0x010000FC)
   $dut_jtag.arm_debug.swj_dp.write_read_ap(0x01000004, 0x10101010)
-  #$dut_jtag.arm_debug.swj_dp.read_expect_ap(0x01000004, 0x10101010)
+  $dut_jtag.arm_debug.swj_dp.read_expect_ap(0x01000004, 0x10101010)
 
 end

data/pattern/read_write_reg_swd.rb

@@ -5,6 +5,6 @@ Pattern.create do
   $dut_swd.arm_debug.swj_dp.write_read_dp("CTRL/STAT", 0x50000000, edata: 0xf0000000)
   $dut_swd.arm_debug.swj_dp.read_ap(0x010000FC)
   $dut_swd.arm_debug.swj_dp.write_read_ap(0x01000004, 0x10101010)
-  #$dut_swd.arm_debug.swj_dp.read_expect_ap(0x01000004, 0x10101010)
+  $dut_swd.arm_debug.swj_dp.read_expect_ap(0x01000004, 0x10101010)
 
 end

metadata

@@ -1,7 +1,7 @@
 --- !ruby/object:Gem::Specification
 name: origen_arm_debug
 version: !ruby/object:Gem::Version
-  version: 0.6.0
+  version: 0.7.0
 platform: ruby
 authors:
 - Ronnie Lajaunie