origen_arm_debug 0.6.0 → 0.7.0
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- checksums.yaml +4 -4
- data/config/application.rb +1 -1
- data/config/commands.rb +5 -0
- data/config/version.rb +1 -1
- data/lib/origen_arm_debug/driver.rb +16 -2
- data/lib/origen_arm_debug/mem_ap.rb +49 -0
- data/lib/origen_arm_debug/swj_dp.rb +33 -15
- data/pattern/read_write_reg.rb +17 -5
- data/pattern/read_write_reg_jtag.rb +1 -1
- data/pattern/read_write_reg_swd.rb +1 -1
- metadata +1 -1
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
|
|
1
1
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---
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2
2
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SHA1:
|
3
|
-
metadata.gz:
|
4
|
-
data.tar.gz:
|
3
|
+
metadata.gz: 528eb3303524b33d1916c73c72a003e9ab5b2880
|
4
|
+
data.tar.gz: fb08b4c3360b61dc8732ad9bcf6065896fc638c3
|
5
5
|
SHA512:
|
6
|
-
metadata.gz:
|
7
|
-
data.tar.gz:
|
6
|
+
metadata.gz: 19abcb44c8b1fed4d00f1cab8828dccd640b2ee2bdf0f903867fd179e720e5d1ada1fcaf57691735238e606eac71237ee0cbc0f0991840b533e82433b4005345
|
7
|
+
data.tar.gz: a8daf8a46d1d3f2c9c68bc66a1ab94aa828c074e24e7d05e26749cd774bca47a30b8fc57bda31b08614a05e05925b2639efb080408fb8afa02c7c90b5f304d1b
|
data/config/application.rb
CHANGED
@@ -30,7 +30,7 @@ class OrigenARMDebugApplication < Origen::Application
|
|
30
30
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|
31
31
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# Ensure that all tests pass before allowing a release to continue
|
32
32
|
def validate_release
|
33
|
-
if !system("origen examples")
|
33
|
+
if !system("origen examples") || !system("origen specs")
|
34
34
|
puts "Sorry but you can't release with failing tests, please fix them and try again."
|
35
35
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exit 1
|
36
36
|
else
|
data/config/commands.rb
CHANGED
@@ -17,6 +17,10 @@ aliases ={
|
|
17
17
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# Now branch to the specific task code
|
18
18
|
case @command
|
19
19
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|
20
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+
when "specs"
|
21
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+
require "rspec"
|
22
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+
exit RSpec::Core::Runner.run(['spec'])
|
23
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+
|
20
24
|
when "examples"
|
21
25
|
Origen.load_application
|
22
26
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status = 0
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@@ -49,6 +53,7 @@ when "examples"
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|
49
53
|
# before handing control back to Origen. Un-comment the example below to get started.
|
50
54
|
else
|
51
55
|
@application_commands = <<-EOT
|
56
|
+
specs Run the specs (unit tests), -c will enable coverage
|
52
57
|
examples Run the examples (tests), -c will enable coverage
|
53
58
|
EOT
|
54
59
|
|
data/config/version.rb
CHANGED
@@ -56,7 +56,12 @@ module OrigenARMDebug
|
|
56
56
|
# the cycles corresponding to those bits only (don't care cycles will be generated for the others).
|
57
57
|
# @param [Hash] options Options to customize the operation
|
58
58
|
def read_register(reg_or_val, options = {})
|
59
|
-
|
59
|
+
if options[:ap].nil?
|
60
|
+
ap = mem_ap # default to 'mem_ap' if no AP is specified as an option
|
61
|
+
else
|
62
|
+
ap = options[:ap]
|
63
|
+
end
|
64
|
+
ap.read_register(reg_or_val, options)
|
60
65
|
end
|
61
66
|
|
62
67
|
# Write data to a MEM-AP register
|
@@ -67,7 +72,16 @@ module OrigenARMDebug
|
|
67
72
|
# the cycles corresponding to those bits only (don't care cycles will be generated for the others).
|
68
73
|
# @param [Hash] options Options to customize the operation
|
69
74
|
def write_register(reg_or_val, options = {})
|
70
|
-
|
75
|
+
if options[:ap].nil?
|
76
|
+
ap = mem_ap # default to 'mem_ap' if no AP is specified as an option
|
77
|
+
else
|
78
|
+
ap = options[:ap]
|
79
|
+
end
|
80
|
+
ap.write_register(reg_or_val, options)
|
81
|
+
end
|
82
|
+
|
83
|
+
def inspect_driver
|
84
|
+
Origen.log.info "ARM Debug Driver = #{arm_debug_driver}"
|
71
85
|
end
|
72
86
|
|
73
87
|
private
|
@@ -65,6 +65,55 @@ module OrigenARMDebug
|
|
65
65
|
# -----------------------------------------------------------------------------
|
66
66
|
# User API
|
67
67
|
# -----------------------------------------------------------------------------
|
68
|
+
def read_register(reg_or_val, options = {})
|
69
|
+
if reg_or_val.respond_to?(:data)
|
70
|
+
addr = reg_or_val.addr
|
71
|
+
options = { reg: reg_or_val }.merge(options)
|
72
|
+
else
|
73
|
+
addr = reg_or_val # if not a register, use the 'val' as target addr
|
74
|
+
end
|
75
|
+
|
76
|
+
options = { size: 32 }.merge(options)
|
77
|
+
options = { r_mask: 'mask', r_attempts: 1 }.merge(options)
|
78
|
+
msg = 'Arm Debug: Shift out data for reading'
|
79
|
+
options = { arm_debug_comment: msg }.merge(options)
|
80
|
+
size = options[:size]
|
81
|
+
|
82
|
+
set_size(size)
|
83
|
+
set_addr(addr)
|
84
|
+
debug_port.read_ap(drw_reg_addr, options)
|
85
|
+
rdata = get_rdata(size, addr, rdata)
|
86
|
+
increment_addr
|
87
|
+
|
88
|
+
cc "MEM-AP(#{@name}): R-#{size.to_s(10)}: "\
|
89
|
+
"addr=0x#{addr.to_s(16).rjust(size / 4, '0')}"
|
90
|
+
end
|
91
|
+
|
92
|
+
def write_register(reg_or_val, options = {});
|
93
|
+
if reg_or_val.respond_to?(:data)
|
94
|
+
addr = reg_or_val.addr
|
95
|
+
wdata = reg_or_val.data
|
96
|
+
options = { reg: reg_or_val }.merge(options)
|
97
|
+
else
|
98
|
+
addr = reg_or_val # if not a register, use the 'val' as target addr
|
99
|
+
wdata = options[:wdata]
|
100
|
+
end
|
101
|
+
options = { size: 32 }.merge(options)
|
102
|
+
options = { w_attempts: 1 }.merge(options)
|
103
|
+
msg = "Arm Debug: Shift in data to write: #{wdata.to_hex}"
|
104
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+
options = { arm_debug_comment: msg }.merge(options)
|
105
|
+
size = options[:size]
|
106
|
+
|
107
|
+
set_size(size)
|
108
|
+
set_addr(addr)
|
109
|
+
wdata = get_wdata(size, addr, wdata)
|
110
|
+
debug_port.write_ap(drw_reg_addr, wdata, options)
|
111
|
+
increment_addr
|
112
|
+
|
113
|
+
cc "MEM-AP(#{@name}): WR-#{size.to_s(10)}: "\
|
114
|
+
"addr=0x#{addr.to_s(16).rjust(size / 4, '0')}, "\
|
115
|
+
"data=0x#{wdata.to_s(16).rjust(size / 4, '0')}"
|
116
|
+
end
|
68
117
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|
69
118
|
# Method to read from a mem_ap register
|
70
119
|
#
|
@@ -34,10 +34,7 @@ module OrigenARMDebug
|
|
34
34
|
@imp = implementation
|
35
35
|
else
|
36
36
|
msg = "SWJ-DP: '#{implementation}' implementation not supported. JTAG and SWD only"
|
37
|
-
|
38
|
-
|
39
|
-
# Just default to jtag for now
|
40
|
-
@imp = :jtag
|
37
|
+
fail msg
|
41
38
|
end
|
42
39
|
|
43
40
|
@write_ap_dly = 8
|
@@ -145,7 +142,7 @@ module OrigenARMDebug
|
|
145
142
|
# Create another copy of options with select keys removed.
|
146
143
|
# This first read is junk so we do not want to store it or compare it.
|
147
144
|
junk_options = options.clone.delete_if do |key, val|
|
148
|
-
(key.eql?(:r_mask) && val.eql?('store')) || key.eql?(:compare_data)
|
145
|
+
(key.eql?(:r_mask) && val.eql?('store')) || key.eql?(:compare_data) || key.eql?(:reg)
|
149
146
|
end
|
150
147
|
|
151
148
|
apacc_access(addr, rwb, random, 0, junk_options)
|
@@ -165,7 +162,7 @@ module OrigenARMDebug
|
|
165
162
|
# @param [Hash] options Options to customize the operation
|
166
163
|
def read_expect_ap(addr, edata, options = {})
|
167
164
|
options[:edata] = edata
|
168
|
-
read_ap(
|
165
|
+
read_ap(addr, options)
|
169
166
|
end
|
170
167
|
alias_method :wait_read_expect_ap, :read_expect_ap
|
171
168
|
|
@@ -339,9 +336,9 @@ module OrigenARMDebug
|
|
339
336
|
# @param [Hash] options Options to customize the operation
|
340
337
|
def acc_access(addr, rwb, ap_dp, wdata, options = {})
|
341
338
|
if @imp == :swd
|
342
|
-
acc_access_swd(addr, rwb, ap_dp, wdata, options
|
339
|
+
acc_access_swd(addr, rwb, ap_dp, wdata, options)
|
343
340
|
else
|
344
|
-
acc_access_jtag(addr, rwb, ap_dp, wdata, options
|
341
|
+
acc_access_jtag(addr, rwb, ap_dp, wdata, options)
|
345
342
|
end
|
346
343
|
end
|
347
344
|
|
@@ -354,7 +351,13 @@ module OrigenARMDebug
|
|
354
351
|
# @param [Hash] options Options to customize the operation
|
355
352
|
def acc_access_swd(addr, rwb, ap_dp, wdata, options = {})
|
356
353
|
if (rwb == 1)
|
357
|
-
|
354
|
+
if options[:reg].nil?
|
355
|
+
swd.read(ap_dp, addr, options)
|
356
|
+
else
|
357
|
+
# make sure reg.addr = addr
|
358
|
+
Origen.log.error 'SWJ_DP ERROR: In acc_access_swd, addr does not match options[:reg].addr'
|
359
|
+
swd.read(ap_dp, options[:reg], options)
|
360
|
+
end
|
358
361
|
else
|
359
362
|
swd.write(ap_dp, addr, wdata, options)
|
360
363
|
end
|
@@ -379,12 +382,27 @@ module OrigenARMDebug
|
|
379
382
|
end
|
380
383
|
|
381
384
|
attempts.times do
|
382
|
-
if
|
383
|
-
|
384
|
-
|
385
|
-
|
386
|
-
|
387
|
-
|
385
|
+
if rwb == 1
|
386
|
+
if options[:reg].nil?
|
387
|
+
r = $dut.reg(:dap)
|
388
|
+
if options[:r_mask] == 'store'
|
389
|
+
r.bits(3..34).store
|
390
|
+
elsif options.key?(:compare_data)
|
391
|
+
r.bits(3..34).data = options[:compare_data]
|
392
|
+
elsif options.key?(:edata)
|
393
|
+
options[:compare_data] = options[:edata]
|
394
|
+
r.bits(3..34).data = options[:edata]
|
395
|
+
end
|
396
|
+
else
|
397
|
+
r = $dut.reg(:dap)
|
398
|
+
r.reset
|
399
|
+
r.bits(3..34).data = options[:reg].data
|
400
|
+
(3..34).each do |i|
|
401
|
+
r.bits(i).read if options[:reg].bits(i - 3).is_to_be_read?
|
402
|
+
end
|
403
|
+
(3..34).each do |i|
|
404
|
+
r.bits(i).store if options[:reg].bits(i - 3).is_to_be_stored?
|
405
|
+
end
|
388
406
|
end
|
389
407
|
|
390
408
|
options = options.merge(size: r.size)
|
data/pattern/read_write_reg.rb
CHANGED
@@ -1,17 +1,29 @@
|
|
1
1
|
Pattern.create do
|
2
2
|
|
3
3
|
ss "Test write register, should write value 0xFF01"
|
4
|
-
$dut.reg(:test).write!(
|
5
|
-
|
4
|
+
$dut.reg(:test).write!(0x0000FF01)
|
5
|
+
|
6
|
+
ss "Test read register, should read value 0x0000FF01"
|
6
7
|
$dut.reg(:test).read!
|
8
|
+
|
9
|
+
ss "Test read register with mask, should read value 0xXXXxxx1"
|
10
|
+
$dut.reg(:test).read!(mask: 0x0000_000F)
|
11
|
+
|
12
|
+
ss "Test read register with store"
|
13
|
+
$dut.reg(:test).store!
|
14
|
+
|
7
15
|
ss "Test bit level read, should read value 0xXXXxxx1"
|
16
|
+
$dut.reg(:test).reset
|
17
|
+
$dut.reg(:test).data = 0x0000FF01
|
8
18
|
$dut.reg(:test).bit(:bit).read!
|
9
19
|
|
10
|
-
|
20
|
+
ss "Test read register"
|
11
21
|
$dut.read_register($dut.reg(:test))
|
12
|
-
$dut.write_register($dut.reg(:test), 0xFF02)
|
13
22
|
|
14
|
-
|
23
|
+
ss "Test write register"
|
24
|
+
$dut.write_register($dut.reg(:test))
|
25
|
+
|
26
|
+
$dut.arm_debug.mem_ap.R(0x10000004, 0x00000000, compare_data: 0x00000000)
|
15
27
|
$dut.arm_debug.mem_ap.W(0x10000004, 0x55555555)
|
16
28
|
$dut.arm_debug.mem_ap.WR(0x10000004, 0x55555555)
|
17
29
|
|
@@ -5,6 +5,6 @@ Pattern.create do
|
|
5
5
|
$dut_jtag.arm_debug.swj_dp.write_read_dp("CTRL/STAT", 0x50000000, edata: 0xf0000000)
|
6
6
|
$dut_jtag.arm_debug.swj_dp.read_ap(0x010000FC)
|
7
7
|
$dut_jtag.arm_debug.swj_dp.write_read_ap(0x01000004, 0x10101010)
|
8
|
-
|
8
|
+
$dut_jtag.arm_debug.swj_dp.read_expect_ap(0x01000004, 0x10101010)
|
9
9
|
|
10
10
|
end
|
@@ -5,6 +5,6 @@ Pattern.create do
|
|
5
5
|
$dut_swd.arm_debug.swj_dp.write_read_dp("CTRL/STAT", 0x50000000, edata: 0xf0000000)
|
6
6
|
$dut_swd.arm_debug.swj_dp.read_ap(0x010000FC)
|
7
7
|
$dut_swd.arm_debug.swj_dp.write_read_ap(0x01000004, 0x10101010)
|
8
|
-
|
8
|
+
$dut_swd.arm_debug.swj_dp.read_expect_ap(0x01000004, 0x10101010)
|
9
9
|
|
10
10
|
end
|