ipxact-tools 0.2.0
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- data/config/detector.yml +63 -0
- data/lib/ipxact_tools.rb +287 -0
- data/lib/ipxact_tools/graph_pathfinder.rb +191 -0
- data/lib/ipxact_tools/interrupt_line_detector.rb +98 -0
- data/spec/integration/integration_spec.rb +254 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/PV/pv_initiator_port.h +135 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/PV/pv_initiator_port.tpp +247 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/PV/pv_initiator_port_base.h +189 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/PV/pv_router.h +205 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/PV/pv_router.tpp +278 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/PV/pv_slave_base.h +115 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/PV/pv_slave_base.tpp +126 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/PV/pv_target_port.h +168 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/PV/pv_target_port_base.h +133 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/PV/pv_tlm_if.h +280 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/PV/user_types.h +38 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/SystemTLM1/Leon2Platform/Leon2Platform.xml +77 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/SystemTLM1/Leon2Platform/design_Leon2Platform.xml +156 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/SystemTLM1/Leon2Platform/tlmsrc/Leon2Platform.h +149 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/SystemTLM1/apbSubSystem/apbSubSystem.xml +406 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/SystemTLM1/apbSubSystem/design_apbSubSystem.xml +135 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/SystemTLM1/apbSubSystem/tlmsrc/apbSubSystem.h +133 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/SystemTLM2/Leon2Platform/Leon2Platform.xml +77 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/SystemTLM2/Leon2Platform/design_Leon2Platform.xml +157 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/SystemTLM2/Leon2Platform/tlmsrc/Leon2Platform.h +150 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/SystemTLM2/apbSubSystem/apbSubSystem.xml +422 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/SystemTLM2/apbSubSystem/designConfig_apbSubSystem.xml +79 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/SystemTLM2/apbSubSystem/design_apbSubSystem.xml +184 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/SystemTLM2/apbSubSystem/tlmsrc/apbSubSystem.h +164 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/SystemTLM3/Leon2Platform/Leon2Platform.xml +105 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/SystemTLM3/Leon2Platform/design_Leon2Platform.xml +157 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/SystemTLM3/Leon2Platform/tlmsrc/Leon2Platform.h +152 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/SystemTLM3/apbSubSystem/apbSubSystem.xml +429 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/SystemTLM3/apbSubSystem/designConfig_apbSubSystem.xml +64 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/SystemTLM3/apbSubSystem/design_apbSubSystem.xml +150 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/SystemTLM3/apbSubSystem/tlmsrc/apbSubSystem.h +167 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/ahbbus/1.4/ahbbus22.xml +236 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/ahbbus/1.4/tlmsrc/ahbbus.h +52 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/ahbram/1.4/ahbram.xml +184 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/ahbram/1.4/tlmsrc/ahbram.cc +93 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/ahbram/1.4/tlmsrc/ahbram.h +77 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/apbbus/1.4/apbbus8.xml +544 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/apbbus/1.4/tlmsrc/apbbus.h +55 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/apbmst/1.4/apbmst.xml +209 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/apbmst/1.4/tlmsrc/apbmst.h +53 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/apbram/1.0/apbram.xml +395 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/apbram/1.0/hdlsrc/apbram.cc +89 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/apbram/1.0/hdlsrc/apbram.h +69 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/apbram/1.0/hdlsrc/apbram.v +82 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/apbram/1.0/hdlsrc/apbram.vhd +132 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/cgu/1.4/cgu.xml +686 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/cgu/1.4/tlmsrc/cgu.cc +121 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/cgu/1.4/tlmsrc/cgu.h +81 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/cgu/1.5/cgu.xml +707 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/cgu/1.5/tlmsrc/cgu.cc +121 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/cgu/1.5/tlmsrc/cgu.h +81 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/dma/1.4/dma.xml +272 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/dma/1.4/tlmsrc/dma.cc +230 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/dma/1.4/tlmsrc/dma.h +116 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/irqctrl/1.4/irqctrl.xml +530 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/irqctrl/1.4/tlmsrc/irqctrl.cc +211 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/irqctrl/1.4/tlmsrc/irqctrl.h +108 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/processor/1.4/processor.xml +423 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/processor/1.4/tlmsrc/processor.cc +331 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/processor/1.4/tlmsrc/processor.h +121 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/pv2apb/1.0/pv2apb.xml +240 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/pv2apb/1.0/tlmsrc/pv2apb.cc +153 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/pv2apb/1.0/tlmsrc/pv2apb.h +77 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/pv2tac/1.0/pv2tac.xml +154 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/pv2tac/1.0/tlmsrc/pv2tac.cc +114 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/pv2tac/1.0/tlmsrc/pv2tac.h +67 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/rgu/1.4/rgu.xml +766 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/rgu/1.4/tlmsrc/rgu.cc +126 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/rgu/1.4/tlmsrc/rgu.h +105 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/scmlAdaptor/1.0/scmlAdaptor.xml +154 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/scmlAdaptor/1.0/tlmsrc/scmladaptor.cc +100 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/scmlAdaptor/1.0/tlmsrc/scmladaptor.h +62 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/serial_device/1.0/serial_device.xml +151 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/serial_device/1.0/tlmsrc/serial_device.h +85 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/timers/1.4/timers.xml +460 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/timers/1.4/tlmsrc/timers.cc +201 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/timers/1.4/tlmsrc/timers.h +102 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_scml/1.0/tlmsrc/inc/uart.h +152 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_scml/1.0/tlmsrc/inc/uart_fifo.h +113 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_scml/1.0/tlmsrc/inc/uart_memory_map.h +96 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_scml/1.0/tlmsrc/inc/uart_types.h +60 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_scml/1.0/tlmsrc/src/uart.cc +125 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_scml/1.0/tlmsrc/src/uart_interrupt_handler.cc +136 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_scml/1.0/tlmsrc/src/uart_register_bank.cc +129 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_scml/1.0/tlmsrc/src/uart_serial_tx_rx.cc +145 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_scml/1.0/uart_scml.xml +372 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_tac/1.0/tlmsrc/include/Leon2_uart.h +216 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_tac/1.0/tlmsrc/include/def_Leon2_uart.h +34 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_tac/1.0/tlmsrc/include/tlm_field.h +72 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_tac/1.0/tlmsrc/include/tlm_register.h +129 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_tac/1.0/tlmsrc/include/tlmreg_Leon2_uart.h +133 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_tac/1.0/tlmsrc/src/Leon2_uart.cc +316 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_tac/1.0/tlmsrc/src/tlmreg_Leon2_uart.cc +197 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_tac/1.0/tlmsrc/src/user_specific_Leon2_uart.cc +146 -0
- data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_tac/1.0/uart_tac.xml +222 -0
- data/spec/unit/graph_pathfinder_spec.rb +128 -0
- metadata +272 -0
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//
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// Revision: $Revision: 1506 $
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// Date: $Date: 2009-04-26 01:51:56 -0500 (Sun, 26 Apr 2009) $
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//
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// Copyright (c) 2005, 2006, 2007, 2008, 2009 The SPIRIT Consortium.
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//
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// This work forms part of a deliverable of The SPIRIT Consortium.
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//
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// Use of these materials are governed by the legal terms and conditions
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// outlined in the disclaimer available from www.spiritconsortium.org.
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//
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// This source file is provided on an AS IS basis. The SPIRIT
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// Consortium disclaims any warranty express or implied including
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// any warranty of merchantability and fitness for use for a
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// particular purpose.
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//
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// The user of the source file shall indemnify and hold The SPIRIT
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// Consortium and its members harmless from any damages or liability.
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// Users are requested to provide feedback to The SPIRIT Consortium
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// using either mailto:feedback@lists.spiritconsortium.org or the forms at
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// http://www.spiritconsortium.org/about/contact_us/
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//
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// This file may be copied, and distributed, with or without
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// modifications; but this notice must be included on any copy.
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// uart_fifo.h
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#ifndef H_UART_FIFO
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#define H_UART_FIFO
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//***************************
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//* Includes *
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//***************************
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#include "systemc.h" // For 'sc_module'
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//***********************************
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//* UART FIFO Module Class *
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//***********************************
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template <class DT> // Template for the Data Type of the fifo
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class UART_FIFO : public sc_module {
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public:
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//**** Constructor ****//
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UART_FIFO<DT>(sc_module_name N, int pSize) : sc_module(N) {
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fifo = new std::queue<DT>; // Create a new queue object
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Size = pSize;
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TriggerLevel = 1;
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CurrentLevel = 0;
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};
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//**** Destructor ****//
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~UART_FIFO() { delete fifo; };
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// Function for writing data to the fifo
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void write(DT WriteData) {
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if (CurrentLevel < Size) {
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cout << sc_time_stamp() << ": " << name() << ": Writing to FIFO: " << WriteData;
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fifo->push(WriteData);
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CurrentLevel++;
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cout << " (New FIFO Level = " << CurrentLevel << ")" << endl;
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}
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};
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// Function for reading data from the fifo
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DT read() {
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if (CurrentLevel > 0) {
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DT ReturnData;
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ReturnData = fifo->front();
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fifo->pop();
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CurrentLevel--;
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cout << sc_time_stamp() << ": " << name() << ": Reading from FIFO: " << ReturnData << " (New FIFO Level = " << CurrentLevel << ")" << endl;
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return ReturnData;
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}
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return 0;
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};
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// Function for setting a new trigger level
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void SetTriggerLevel(int level) {
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if (level == 0)
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TriggerLevel = 1; // Minimum Trigger level = 1
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if (level > Size-2)
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TriggerLevel = Size-2; // Maximum Trigger level = Size - 2
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else
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TriggerLevel = level;
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cout << sc_time_stamp() << ": " << name() << ": Trigger Level set to: " << TriggerLevel << endl;
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};
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// Function that returns 1 if FIFO is empty
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bool IsEmpty() {
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return (CurrentLevel == 0);
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};
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// Function that returns 1 if FIFO is full
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bool IsFull() {
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return (CurrentLevel == Size);
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};
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// Function that returns 1 if FIFO is above (or at) the trigger level
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bool IsAboveTriggerLevel() {
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if (CurrentLevel >= TriggerLevel)
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return true;
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else
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return false;
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};
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// Function that returns 1 if FIFO is below the trigger level
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bool IsBelowTriggerLevel() {
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if (CurrentLevel < TriggerLevel)
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return true;
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else
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return false;
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};
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private:
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int Size; // The size of the FIFO
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int TriggerLevel; // Trigger Level of the FIFO
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int CurrentLevel; // This variable indicates how many elements are currently in the FIFO
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std::queue<DT> * fifo; // Pointer to the FIFO queue
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};
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#endif //H_UART_FIFO
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//
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// Revision: $Revision: 1506 $
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// Date: $Date: 2009-04-26 01:51:56 -0500 (Sun, 26 Apr 2009) $
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//
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// Copyright (c) 2005, 2006, 2007, 2008, 2009 The SPIRIT Consortium.
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//
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// This work forms part of a deliverable of The SPIRIT Consortium.
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//
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// Use of these materials are governed by the legal terms and conditions
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// outlined in the disclaimer available from www.spiritconsortium.org.
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//
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// This source file is provided on an AS IS basis. The SPIRIT
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// Consortium disclaims any warranty express or implied including
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// any warranty of merchantability and fitness for use for a
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// particular purpose.
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//
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// The user of the source file shall indemnify and hold The SPIRIT
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// Consortium and its members harmless from any damages or liability.
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// Users are requested to provide feedback to The SPIRIT Consortium
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// using either mailto:feedback@lists.spiritconsortium.org or the forms at
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// http://www.spiritconsortium.org/about/contact_us/
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//
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// This file may be copied, and distributed, with or without
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// modifications; but this notice must be included on any copy.
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#ifndef H_UART_MEMORY_MAP
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#define H_UART_MEMORY_MAP
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// Register Address Map:
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#define UART_MEM_SIZE 6 // Size of the UART address space
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#define UART_REG_WIDTH sizeof(DATA_TYPE) // Byte width of the registers
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// Index of UART registers
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#define UART_REG_RBR 0 // Receiver Buffer Register
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#define UART_REG_THR 0 // Transmitter Holding Register
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#define UART_REG_IER 1 // Interrupt Enable (Mask) Register
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#define UART_REG_IIR 2 // Interrupt Identification Register
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#define UART_REG_FCR 2 // FIFO Control Register
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#define UART_REG_LCR 3 // Line Control Register
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#define UART_REG_LSR 5 // Line Status Register
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// Individual Bit positions within registers
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#define UART_BIT_FCR_FIFOE 0 // Position of FIFO Enable bit in FCR register
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#define UART_BIT_LSR_THRE 5 // Position of THR Empty bit in LSR register
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#define UART_BIT_LSR_BI 4 // Position of Break Indicator bit in LSR register
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#define UART_BIT_LSR_FE 3 // Position of Frame Error bit in LSR register
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#define UART_BIT_LSR_PE 2 // Position of Parity Error bit in LSR register
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#define UART_BIT_LSR_OE 1 // Position of Overflow Error bit in LSR register
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#define UART_BIT_LSR_DR 0 // Position of Data Ready bit in LSR register
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#define UART_BIT_IER_ELSI 2 // Position of Enable Line Status Interrupt bit in IER register
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#define UART_BIT_IER_ETBEI 1 // Position of Enable Transmit Buffer Empty Interrupt bit in IER register
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#define UART_BIT_IER_ERBFI 0 // Position of Enable Receive Buffer Full Interrupt bit in IER register
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#define UART_BIT_LCR_SB 6 // Position of Set Break bit in LCR register
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#define UART_BIT_LCR_SP 5 // Position of Stick Parity bit in LCR register
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#define UART_BIT_LCR_EPS 4 // Position of Even Parity Select bit in LCR register
|
60
|
+
#define UART_BIT_LCR_PEN 3 // Position of Parity Enable bit in LCR register
|
61
|
+
#define UART_BIT_LCR_STB 2 // Position of Number of Stop Bits bit in LCR register
|
62
|
+
#define UART_BIT_LCR_WLS1 1 // Position of Word Length Select bit 1 in LCR register
|
63
|
+
#define UART_BIT_LCR_WLS0 0 // Position of Word Length Select bit 0 in LCR register
|
64
|
+
|
65
|
+
// Line Control Register Options
|
66
|
+
#define UART_LCR_SET_BREAK (1 << UART_BIT_LCR_SB)
|
67
|
+
|
68
|
+
#define UART_LCR_NO_PARITY ((0 << UART_BIT_LCR_PEN) | (0 << UART_BIT_LCR_EPS) | (0 << UART_BIT_LCR_SP))
|
69
|
+
#define UART_LCR_ODD_PARITY ((1 << UART_BIT_LCR_PEN) | (0 << UART_BIT_LCR_EPS) | (0 << UART_BIT_LCR_SP))
|
70
|
+
#define UART_LCR_EVEN_PARITY ((1 << UART_BIT_LCR_PEN) | (1 << UART_BIT_LCR_EPS) | (0 << UART_BIT_LCR_SP))
|
71
|
+
#define UART_LCR_STICK1_PARITY ((1 << UART_BIT_LCR_PEN) | (0 << UART_BIT_LCR_EPS) | (1 << UART_BIT_LCR_SP))
|
72
|
+
#define UART_LCR_STICK0_PARITY ((1 << UART_BIT_LCR_PEN) | (1 << UART_BIT_LCR_EPS) | (1 << UART_BIT_LCR_SP))
|
73
|
+
|
74
|
+
#define UART_LCR_TWO_STOPBITS (1 << UART_BIT_LCR_STB)
|
75
|
+
|
76
|
+
#define UART_LCR_WL5 ((0 << UART_BIT_LCR_WLS1) | (0 << UART_BIT_LCR_WLS0))
|
77
|
+
#define UART_LCR_WL6 ((0 << UART_BIT_LCR_WLS1) | (1 << UART_BIT_LCR_WLS0))
|
78
|
+
#define UART_LCR_WL7 ((1 << UART_BIT_LCR_WLS1) | (0 << UART_BIT_LCR_WLS0))
|
79
|
+
#define UART_LCR_WL8 ((1 << UART_BIT_LCR_WLS1) | (1 << UART_BIT_LCR_WLS0))
|
80
|
+
|
81
|
+
// Interrupt Identification
|
82
|
+
#define UART_IRQ_NONE 0x01 // No Interrupt
|
83
|
+
#define UART_IRQ_LS 0x06 // Line Status Interrupt
|
84
|
+
#define UART_IRQ_RX 0x04 // Data Received or RX FIFO trigger level reached
|
85
|
+
#define UART_IRQ_TX 0x02 // THR Empty or TX FIFO below trigger level
|
86
|
+
|
87
|
+
// Default Register values
|
88
|
+
#define UART_DEFAULT_RBR 0x00 //00000000b
|
89
|
+
#define UART_DEFAULT_THR 0x00 //00000000b
|
90
|
+
#define UART_DEFAULT_IER 0x00 //00000001b
|
91
|
+
#define UART_DEFAULT_IIR 0x01 //00000001b
|
92
|
+
#define UART_DEFAULT_FCR 0x01 //00000001b
|
93
|
+
#define UART_DEFAULT_LCR (UART_LCR_ODD_PARITY | UART_LCR_WL7)
|
94
|
+
#define UART_DEFAULT_LSR 0x60 //01100000b
|
95
|
+
|
96
|
+
#endif // H_UART_MEMORY_MAP
|
@@ -0,0 +1,60 @@
|
|
1
|
+
//
|
2
|
+
// Revision: $Revision: 1506 $
|
3
|
+
// Date: $Date: 2009-04-26 01:51:56 -0500 (Sun, 26 Apr 2009) $
|
4
|
+
//
|
5
|
+
// Copyright (c) 2005, 2006, 2007, 2008, 2009 The SPIRIT Consortium.
|
6
|
+
//
|
7
|
+
// This work forms part of a deliverable of The SPIRIT Consortium.
|
8
|
+
//
|
9
|
+
// Use of these materials are governed by the legal terms and conditions
|
10
|
+
// outlined in the disclaimer available from www.spiritconsortium.org.
|
11
|
+
//
|
12
|
+
// This source file is provided on an AS IS basis. The SPIRIT
|
13
|
+
// Consortium disclaims any warranty express or implied including
|
14
|
+
// any warranty of merchantability and fitness for use for a
|
15
|
+
// particular purpose.
|
16
|
+
//
|
17
|
+
// The user of the source file shall indemnify and hold The SPIRIT
|
18
|
+
// Consortium and its members harmless from any damages or liability.
|
19
|
+
// Users are requested to provide feedback to The SPIRIT Consortium
|
20
|
+
// using either mailto:feedback@lists.spiritconsortium.org or the forms at
|
21
|
+
// http://www.spiritconsortium.org/about/contact_us/
|
22
|
+
//
|
23
|
+
// This file may be copied, and distributed, with or without
|
24
|
+
// modifications; but this notice must be included on any copy.
|
25
|
+
|
26
|
+
|
27
|
+
// uart_types.h
|
28
|
+
|
29
|
+
#ifndef H_UART_TYPES
|
30
|
+
#define H_UART_TYPES
|
31
|
+
|
32
|
+
//*******************************
|
33
|
+
//* Type Definitions *
|
34
|
+
//*******************************
|
35
|
+
typedef unsigned int DATA_TYPE;
|
36
|
+
typedef unsigned int ADDRESS_TYPE;
|
37
|
+
|
38
|
+
typedef struct SerialDataStructure { // This structure is send and received through the serial UART interface
|
39
|
+
bool StartBit;
|
40
|
+
unsigned char Data;
|
41
|
+
bool Parity;
|
42
|
+
bool StopBit;
|
43
|
+
|
44
|
+
// Default Constructor
|
45
|
+
SerialDataStructure() {
|
46
|
+
StartBit = 1;
|
47
|
+
Data = '0';
|
48
|
+
Parity = 1;
|
49
|
+
StopBit = 1;
|
50
|
+
};
|
51
|
+
// Constructor with argument passing
|
52
|
+
SerialDataStructure(bool pStartBit, unsigned char pData, bool pParity, bool pStopBit) {
|
53
|
+
StartBit = pStartBit;
|
54
|
+
Data = pData;
|
55
|
+
Parity = pParity;
|
56
|
+
StopBit = pStopBit;
|
57
|
+
}
|
58
|
+
} SERIAL_DATA_STRUCTURE;
|
59
|
+
|
60
|
+
#endif // H_UART_TYPES
|
@@ -0,0 +1,125 @@
|
|
1
|
+
//
|
2
|
+
// Revision: $Revision: 1506 $
|
3
|
+
// Date: $Date: 2009-04-26 01:51:56 -0500 (Sun, 26 Apr 2009) $
|
4
|
+
//
|
5
|
+
// Copyright (c) 2005, 2006, 2007, 2008, 2009 The SPIRIT Consortium.
|
6
|
+
//
|
7
|
+
// This work forms part of a deliverable of The SPIRIT Consortium.
|
8
|
+
//
|
9
|
+
// Use of these materials are governed by the legal terms and conditions
|
10
|
+
// outlined in the disclaimer available from www.spiritconsortium.org.
|
11
|
+
//
|
12
|
+
// This source file is provided on an AS IS basis. The SPIRIT
|
13
|
+
// Consortium disclaims any warranty express or implied including
|
14
|
+
// any warranty of merchantability and fitness for use for a
|
15
|
+
// particular purpose.
|
16
|
+
//
|
17
|
+
// The user of the source file shall indemnify and hold The SPIRIT
|
18
|
+
// Consortium and its members harmless from any damages or liability.
|
19
|
+
// Users are requested to provide feedback to The SPIRIT Consortium
|
20
|
+
// using either mailto:feedback@lists.spiritconsortium.org or the forms at
|
21
|
+
// http://www.spiritconsortium.org/about/contact_us/
|
22
|
+
//
|
23
|
+
// This file may be copied, and distributed, with or without
|
24
|
+
// modifications; but this notice must be included on any copy.
|
25
|
+
|
26
|
+
|
27
|
+
// uart.cpp
|
28
|
+
|
29
|
+
//***************************
|
30
|
+
//* Includes *
|
31
|
+
//***************************
|
32
|
+
#include "uart.h"
|
33
|
+
|
34
|
+
//***************************************
|
35
|
+
//* UART Module: Constructor *
|
36
|
+
//***************************************
|
37
|
+
uart::uart(sc_module_name Name) :
|
38
|
+
sc_module(Name),
|
39
|
+
pPVTargetPort("pPVTargetPort"),
|
40
|
+
pReset("pReset"),
|
41
|
+
pInterrupt("pInterrupt"),
|
42
|
+
pSerialOut("pSerialOut"),
|
43
|
+
pSerialIn("pSerialIn"),
|
44
|
+
mRegisterBank("mRegisterBank", scml_memsize(UART_MEM_SIZE)),
|
45
|
+
rRBR_THR("rRBR_THR", mRegisterBank, UART_REG_RBR, 1),
|
46
|
+
rIIR_FCR("rIIR_FCR", mRegisterBank, UART_REG_IIR, 1),
|
47
|
+
rIER("rIER", mRegisterBank, UART_REG_IER, 1),
|
48
|
+
bIER_ELSI("bIER_ELSI", rIER, UART_BIT_IER_ELSI, 1),
|
49
|
+
bIER_ETBEI("bIER_ETBEI", rIER, UART_BIT_IER_ETBEI, 1),
|
50
|
+
bIER_ERBFI("bIER_ERBFI", rIER, UART_BIT_IER_ERBFI, 1),
|
51
|
+
rLCR("rLCR", mRegisterBank, UART_REG_LCR, 1),
|
52
|
+
bLCR_SB("bLCR_SB", rLCR, UART_BIT_LCR_SB, 1),
|
53
|
+
bLCR_SP("bLCR_SP", rLCR, UART_BIT_LCR_SP, 1),
|
54
|
+
bLCR_EPS("bLCR_EPS", rLCR, UART_BIT_LCR_EPS, 1),
|
55
|
+
bLCR_PEN("bLCR_PEN", rLCR, UART_BIT_LCR_PEN, 1),
|
56
|
+
bLCR_STB("bLCR_STB", rLCR, UART_BIT_LCR_STB, 1),
|
57
|
+
bLCR_WLS1("bLCR_WLS1", rLCR, UART_BIT_LCR_WLS1, 1),
|
58
|
+
bLCR_WLS0("bLCR_WLS0", rLCR, UART_BIT_LCR_WLS0, 1),
|
59
|
+
rLSR("rLSR", mRegisterBank, UART_REG_LSR, 1),
|
60
|
+
bLSR_THRE("bLSR_THRE", rLSR, UART_BIT_LSR_THRE, 1),
|
61
|
+
bLSR_BI("bLSR_BI", rLSR, UART_BIT_LSR_BI, 1),
|
62
|
+
bLSR_FE("bLSR_FE", rLSR, UART_BIT_LSR_FE, 1),
|
63
|
+
bLSR_PE("bLSR_PE", rLSR, UART_BIT_LSR_PE, 1),
|
64
|
+
bLSR_OE("bLSR_OE", rLSR, UART_BIT_LSR_OE, 1),
|
65
|
+
bLSR_DR("bLSR_DR", rLSR, UART_BIT_LSR_DR, 1),
|
66
|
+
rRBR("rRBR", scml_memsize(1)),
|
67
|
+
rTHR("rTHR", scml_memsize(1)),
|
68
|
+
rIIR("rIIR", scml_memsize(1)),
|
69
|
+
rFCR("rFCR", scml_memsize(1)),
|
70
|
+
bFCR_FIFOE("bFCR_FIFOE", rFCR, UART_BIT_FCR_FIFOE, 1),
|
71
|
+
TX_FIFO("TX_FIFO", TX_FIFO_SIZE),
|
72
|
+
RX_FIFO("RX_FIFO", RX_FIFO_SIZE)
|
73
|
+
{
|
74
|
+
|
75
|
+
mRegisterBank.set_addressing_mode(8); // Set memory to byte addressing
|
76
|
+
|
77
|
+
pPVTargetPort(mRegisterBank); // Bind the PV port to the register bank
|
78
|
+
|
79
|
+
// Initialize global class variables
|
80
|
+
Clear_LS_Interrupt = false;
|
81
|
+
Clear_RX_Interrupt = false;
|
82
|
+
Clear_TX_Interrupt = false;
|
83
|
+
CurrentInterruptPriority = 6;
|
84
|
+
|
85
|
+
pSerialIn.bind(*this); // bind the 'pSerialIn' export to this module
|
86
|
+
|
87
|
+
// Register the call-back functions of the register aliases
|
88
|
+
MEMORY_REGISTER_NB_WRITE(rRBR_THR, RegCB_RBR_THR_Write);
|
89
|
+
MEMORY_REGISTER_NB_READ(rRBR_THR, RegCB_RBR_THR_Read);
|
90
|
+
|
91
|
+
MEMORY_REGISTER_NB_WRITE(rIIR_FCR, RegCB_IIR_FCR_Write);
|
92
|
+
MEMORY_REGISTER_NB_READ(rIIR_FCR, RegCB_IIR_FCR_Read);
|
93
|
+
|
94
|
+
MEMORY_REGISTER_NB_READ(rLSR, RegCB_LSR_Read);
|
95
|
+
|
96
|
+
MEMORY_REGISTER_NB_WRITE(rIER, RegCB_IER_Write);
|
97
|
+
|
98
|
+
// Declare methods
|
99
|
+
SC_METHOD(Serial_Transmit);
|
100
|
+
sensitive << TransmitEvent;
|
101
|
+
dont_initialize();
|
102
|
+
|
103
|
+
SC_METHOD(Handle_Interrupts);
|
104
|
+
sensitive << InterruptEvent;
|
105
|
+
dont_initialize();
|
106
|
+
|
107
|
+
SC_METHOD(Reset);
|
108
|
+
sensitive << pReset.pos();
|
109
|
+
};
|
110
|
+
|
111
|
+
//*******************************************************************
|
112
|
+
//* UART Module: Reset() *
|
113
|
+
//* This Function resets all registers to their default value. *
|
114
|
+
//*******************************************************************
|
115
|
+
void uart::Reset() {
|
116
|
+
cout << name() << " resetting registers" << endl;
|
117
|
+
mRegisterBank.initialize(0);
|
118
|
+
rRBR = UART_DEFAULT_RBR;
|
119
|
+
rTHR = UART_DEFAULT_THR;
|
120
|
+
rIER = UART_DEFAULT_IER;
|
121
|
+
rIIR = UART_DEFAULT_IIR;
|
122
|
+
rFCR = UART_DEFAULT_FCR;
|
123
|
+
rLCR = UART_DEFAULT_LCR;
|
124
|
+
rLSR = UART_DEFAULT_LSR;
|
125
|
+
};
|
data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_scml/1.0/tlmsrc/src/uart_interrupt_handler.cc
ADDED
@@ -0,0 +1,136 @@
|
|
1
|
+
//
|
2
|
+
// Revision: $Revision: 1506 $
|
3
|
+
// Date: $Date: 2009-04-26 01:51:56 -0500 (Sun, 26 Apr 2009) $
|
4
|
+
//
|
5
|
+
// Copyright (c) 2005, 2006, 2007, 2008, 2009 The SPIRIT Consortium.
|
6
|
+
//
|
7
|
+
// This work forms part of a deliverable of The SPIRIT Consortium.
|
8
|
+
//
|
9
|
+
// Use of these materials are governed by the legal terms and conditions
|
10
|
+
// outlined in the disclaimer available from www.spiritconsortium.org.
|
11
|
+
//
|
12
|
+
// This source file is provided on an AS IS basis. The SPIRIT
|
13
|
+
// Consortium disclaims any warranty express or implied including
|
14
|
+
// any warranty of merchantability and fitness for use for a
|
15
|
+
// particular purpose.
|
16
|
+
//
|
17
|
+
// The user of the source file shall indemnify and hold The SPIRIT
|
18
|
+
// Consortium and its members harmless from any damages or liability.
|
19
|
+
// Users are requested to provide feedback to The SPIRIT Consortium
|
20
|
+
// using either mailto:feedback@lists.spiritconsortium.org or the forms at
|
21
|
+
// http://www.spiritconsortium.org/about/contact_us/
|
22
|
+
//
|
23
|
+
// This file may be copied, and distributed, with or without
|
24
|
+
// modifications; this notice must be included on any copy.
|
25
|
+
|
26
|
+
|
27
|
+
// uart_interrupt_handler.cpp
|
28
|
+
|
29
|
+
//***************************
|
30
|
+
//* Includes *
|
31
|
+
//***************************
|
32
|
+
#include "uart.h"
|
33
|
+
|
34
|
+
//***********************************************************************************
|
35
|
+
//* UART Module: Handle_Interrupts() *
|
36
|
+
//* This Method is triggered by the 'InterruptEvent' event. *
|
37
|
+
//* It checks the status of the UART and issues interrupts when necessary. *
|
38
|
+
//***********************************************************************************
|
39
|
+
void uart::Handle_Interrupts() {
|
40
|
+
|
41
|
+
rIIR = (bFCR_FIFOE << 7) | (bFCR_FIFOE << 6) | UART_IRQ_NONE; // Set the IIR register do default value (NO interrupt pending)
|
42
|
+
|
43
|
+
if (CurrentInterruptPriority == 1 && Clear_LS_Interrupt == true) { // If the Line Status Interrupt is to be cleared...
|
44
|
+
cout << sc_time_stamp() << ": " << name() << ": Line Status Interrupt Cleared." << endl;
|
45
|
+
Clear_LS_Interrupt = false;
|
46
|
+
bLSR_OE = 0; // Clear the Overflow Error bit
|
47
|
+
bLSR_PE = 0; // Clear the Parity Error bit
|
48
|
+
bLSR_FE = 0; // Clear the Framing Error bit
|
49
|
+
bLSR_BI = 0; // Clear the Break Indicator bit
|
50
|
+
CurrentInterruptPriority = 6; // Reset interrupt priority level
|
51
|
+
pInterrupt = 0; // Clear Interrupt line
|
52
|
+
InterruptEvent.notify(); // Check for additional interrupts
|
53
|
+
return;
|
54
|
+
}
|
55
|
+
if (CurrentInterruptPriority == 2 && Clear_RX_Interrupt == true) { // If the Receive Buffer full Interrupt is to be cleared...
|
56
|
+
cout << sc_time_stamp() << ": " << name() << ": Receiver Interrupt Cleared." << endl;
|
57
|
+
Clear_RX_Interrupt = false;
|
58
|
+
CurrentInterruptPriority = 6; // Reset interrupt priority level
|
59
|
+
pInterrupt = 0; // Clear Interrupt line
|
60
|
+
InterruptEvent.notify(); // Check for additional interrupts
|
61
|
+
return;
|
62
|
+
}
|
63
|
+
if (CurrentInterruptPriority == 3 && Clear_TX_Interrupt == true) { // If the Transmit Buffer empty Interrupt is to be cleared...
|
64
|
+
cout << sc_time_stamp() << ": " << name() << ": Transmitter Interrupt Cleared." << endl;
|
65
|
+
Clear_TX_Interrupt = false;
|
66
|
+
CurrentInterruptPriority = 6; // Reset interrupt priority level
|
67
|
+
pInterrupt = 0; // Clear Interrupt line
|
68
|
+
InterruptEvent.notify(); // Check for additional interrupts
|
69
|
+
return;
|
70
|
+
}
|
71
|
+
// Reset the Clear Interrupt variables
|
72
|
+
Clear_LS_Interrupt = false;
|
73
|
+
Clear_TX_Interrupt = false;
|
74
|
+
Clear_RX_Interrupt = false;
|
75
|
+
|
76
|
+
// Check for new Interrupts:
|
77
|
+
if (bIER_ELSI){ // If the Line Status Interrupt is Enabled...
|
78
|
+
if (bLSR_OE | bLSR_PE | bLSR_FE | bLSR_BI) { // If the Overflow Error, Parity Error, Framing Error or Break Indicator flag is set...
|
79
|
+
rIIR = (bFCR_FIFOE << 7) | (bFCR_FIFOE << 6) | UART_IRQ_LS; // Update IIR to indicate a Line Status Interrupt is set
|
80
|
+
CurrentInterruptPriority = 1; // Update Interrupt Priority level
|
81
|
+
if (pInterrupt == 1) { // If there already is an interrupt pending
|
82
|
+
pInterrupt = 0; // Clear the interrupt line
|
83
|
+
InterruptEvent.notify(SC_ZERO_TIME); // Call this function again, with a delta cycle delay. This should make the interrupt line low for one delta cycle.
|
84
|
+
return;
|
85
|
+
}
|
86
|
+
pInterrupt = 1; // Set the interrupt line
|
87
|
+
return;
|
88
|
+
}
|
89
|
+
}
|
90
|
+
if (bIER_ERBFI) { // If the Receive Buffer Full Interrupt is Enabled...
|
91
|
+
if (bLSR_DR) { // If the Data Ready flag is set...
|
92
|
+
if (bFCR_FIFOE) { // If the FIFOs are Enabled...
|
93
|
+
if (RX_FIFO.IsAboveTriggerLevel()) { // If the Receive FIFO is above its trigger level...
|
94
|
+
rIIR = (bFCR_FIFOE << 7) | (bFCR_FIFOE << 6) | UART_IRQ_RX; // Update IIR to indicate a Receive Buffer Full Interrupt is set
|
95
|
+
CurrentInterruptPriority = 2; // Update Interrupt Priority level
|
96
|
+
if (pInterrupt == 1) { // If there already is an interrupt pending...
|
97
|
+
pInterrupt = 0; // Clear the interrupt line
|
98
|
+
InterruptEvent.notify(SC_ZERO_TIME); // Call this function again, with a delta cycle delay. This should make the interrupt line low for one delta cycle.
|
99
|
+
return;
|
100
|
+
}
|
101
|
+
pInterrupt = 1; // Set the interrupt line
|
102
|
+
return;
|
103
|
+
}
|
104
|
+
} else {
|
105
|
+
rIIR = (bFCR_FIFOE << 7) | (bFCR_FIFOE << 6) | UART_IRQ_RX; // Update IIR to indicate a Receive Buffer Full Interrupt is set
|
106
|
+
CurrentInterruptPriority = 2; // Update Interrupt Priority level
|
107
|
+
if (pInterrupt == 1) { // If there already is an interrupt pending...
|
108
|
+
pInterrupt = 0; // Clear the interrupt line
|
109
|
+
InterruptEvent.notify(SC_ZERO_TIME); // Call this function again, with a delta cycle delay. This should make the interrupt line low for one delta cycle.
|
110
|
+
return;
|
111
|
+
}
|
112
|
+
pInterrupt = 1; // Set the interrupt line
|
113
|
+
return;
|
114
|
+
}
|
115
|
+
}
|
116
|
+
}
|
117
|
+
if (bIER_ETBEI) { // If the Transmit Buffer Empty Interrupt is Enabled...
|
118
|
+
if (bLSR_THRE) { // If the THR Empty bit is set...
|
119
|
+
rIIR = (bFCR_FIFOE << 7) | (bFCR_FIFOE << 6) | UART_IRQ_TX; // Update IIR to indicate a Transmit Buffer Empty Interrupt is set
|
120
|
+
CurrentInterruptPriority = 3; // Update Interrupt Priority level
|
121
|
+
if (pInterrupt == 1) { // If there already is an interrupt pending...
|
122
|
+
pInterrupt = 0; // Clear the interrupt line
|
123
|
+
InterruptEvent.notify(SC_ZERO_TIME); // Call this function again, with a delta cycle delay. This should make the interrupt line low for one delta cycle.
|
124
|
+
return;
|
125
|
+
}
|
126
|
+
pInterrupt = 1; // Set the interrupt line
|
127
|
+
return;
|
128
|
+
}
|
129
|
+
}
|
130
|
+
|
131
|
+
// No interrups
|
132
|
+
CurrentInterruptPriority = 6; // Reset interrupt priority level
|
133
|
+
pInterrupt = 0; // Clear the interrupt line
|
134
|
+
|
135
|
+
return;
|
136
|
+
};
|