indis-arm 0.3.0

data/lib/indis-arm/instruction.rb

@@ -0,0 +1,107 @@
+##############################################################################
+#   Indis framework                                                          #
+#   Copyright (C) 2012 Vladimir "Farcaller" Pouzanov <farcaller@gmail.com>   #
+#                                                                            #
+#   This program is free software: you can redistribute it and/or modify     #
+#   it under the terms of the GNU General Public License as published by     #
+#   the Free Software Foundation, either version 3 of the License, or        #
+#   (at your option) any later version.                                      #
+#                                                                            #
+#   This program is distributed in the hope that it will be useful,          #
+#   but WITHOUT ANY WARRANTY; without even the implied warranty of           #
+#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            #
+#   GNU General Public License for more details.                             #
+#                                                                            #
+#   You should have received a copy of the GNU General Public License        #
+#   along with this program.  If not, see <http://www.gnu.org/licenses/>.    #
+##############################################################################
+
+require 'ostruct'
+require 'indis-arm/instruction_helper'
+require 'indis-core/entity'
+
+module Indis
+  module ARM
+    
+    # ARM::Instruction is a code {Indis::Entity entity} that represens an ARM
+    # instruction
+    class Instruction < Indis::Entity
+      # Instructions can have different value formats. In such a case, +value_format+
+      # specifies the format to use
+      # @return [Symbol]
+      attr_accessor :value_format
+      
+      # @param [Fixnum] vmaddr virtual address
+      # @param [Fixnum] bytes bytes that represent an instruction
+      def initialize(vmaddr, bytes)
+        super vmaddr
+        @size = 4
+        m = self.class.kmap(bytes)
+        self.class.process_automap.each { |p| self.instance_exec(m, &p) } if self.class.process_automap
+        self.instance_exec(m, &self.class.process_block) if self.class.process_block
+      end
+      
+      # @return [Indis::ARM::InstructionHelper] helper that provides common methods for DSL
+      def h
+        InstructionHelper
+      end
+      
+      def to_s
+        s = self.instance_eval "\"#{self.class.formats[:operator]}\""
+        if @value_format
+          fmt = self.class.formats[@value_format]
+          v = self.instance_eval "\"#{fmt}\""
+        else
+          v = self.instance_eval "\"#{self.class.formats[:value]}\"" if self.class.formats[:value]
+        end
+        s = "#{s}\t#{v}" if v
+        s
+      end
+      
+      class << self
+        attr_reader :name # @return [String] instruction name
+        
+        attr_reader :encoding # @return [String] instruction encoding per ARMARM
+        
+        attr_reader :process_block # @return [Proc] data-processing proc
+        
+        attr_reader :formats # @return [Hash] output formats
+        
+        attr_reader :process_automap # @return [Array] a list of automapping procs
+        
+        # @return [String] instruction mask bits
+        def bits_mask
+          @bits.gsub('0', '1').gsub(/[^1]/, '0').to_i(2)
+        end
+        
+        # @return [String] instruction matching bits
+        def bits_match
+          @bits.gsub(/[^01]/, '0').to_i(2)
+        end
+        
+        # @return [OpenStruct] a map of known fields to instruction value
+        def kmap(v)
+          return OpenStruct.new unless @kmap
+          
+          map = @kmap.inject({}) do |map, (m, o, n)|
+            map[n] = (v & m) >> o
+            map
+          end
+          OpenStruct.new(map)
+        end
+      end
+    end
+    
+    # UnknownInstruction represents an unknown (not yet mapped in DSL) instruction
+    class UnknownInstruction < Instruction
+      def initialize(vmaddr, bytes)
+        super
+        @val = bytes
+      end
+      
+      def to_s
+        "UNK\t#{@val.to_s(16).upcase}"
+      end
+    end
+  end
+end

data/lib/indis-arm/instruction_helper.rb

@@ -0,0 +1,156 @@
+##############################################################################
+#   Indis framework                                                          #
+#   Copyright (C) 2012 Vladimir "Farcaller" Pouzanov <farcaller@gmail.com>   #
+#                                                                            #
+#   This program is free software: you can redistribute it and/or modify     #
+#   it under the terms of the GNU General Public License as published by     #
+#   the Free Software Foundation, either version 3 of the License, or        #
+#   (at your option) any later version.                                      #
+#                                                                            #
+#   This program is distributed in the hope that it will be useful,          #
+#   but WITHOUT ANY WARRANTY; without even the implied warranty of           #
+#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            #
+#   GNU General Public License for more details.                             #
+#                                                                            #
+#   You should have received a copy of the GNU General Public License        #
+#   along with this program.  If not, see <http://www.gnu.org/licenses/>.    #
+##############################################################################
+
+require 'indis-core/binaryops_string'
+
+module Indis
+  module ARM
+    module PseudoCodeInstructionHelper
+      def ARMExpandImm(bits_imm12) # A5.2.4
+        ARMExpandImm_C(bits_imm12, 0)[0] # FIXME APSR.C ???
+      end
+      
+      def ARMExpandImm_C(bits_imm12, carry_in) # A5.2.4
+        unrotated_value = bits_imm12.bits(7, 0).zero_extend(32)
+        Shift_C(unrotated_value, :SRType_ROR, 2*(bits_imm12.bits(11, 8).to_i), carry_in)
+      end
+      
+      def DecodeImmShift(bits2_type, bits5_imm5)
+        imm = bits5_imm5.to_i
+        case bits2_type.to_i
+        when 0b00
+          [:SRType_LSL, imm]
+        when 0b01
+          [:SRType_LSR, imm == 0 ? 32 : imm]
+        when 0b10
+          [:SRType_ASR, imm == 0 ? 32 : imm]
+        when 0b11
+          imm == 0 ? [:SRType_RRX, 1] : [:SRType_ROR, imm]
+        end    
+      end
+      
+      def ZeroExtend(bits_x, i) # P5.3
+        bits_x.zero_extend(i)
+      end
+      
+      def SignExtend(bits_x, i) # P5.3
+        bits_x.sign_extend(i)
+      end
+      
+      def Shift_C(bits_value, type, amount, carry_in) # A8.4.3
+        raise ArgumentError unless !(type == :SRType_RRX && amount != 1)
+        
+        return [bits_value, carry_in] if amount == 0
+        
+        case type
+        when :SRType_LSL
+          LSL_C(bits_value, amount)
+        when :SRType_LSR
+          LSR_C(bits_value, amount)
+        when :SRType_ASR
+          ASR_C(bits_value, amount)
+        when :SRType_ROR
+          ROR_C(bits_value, amount)
+        when :SRType_RRX
+          RRX_C(bits_value, carry_in)
+        end   
+      end
+      
+      def ROR_C(bits_x, shift) # A2.2.1
+        raise ArgumentError unless shift != 0
+        
+        [bits_x.ror(shift), bits_x.rbit(0)]
+      end
+      
+      def LSR(bits_x, shift) # A2.2.1
+        raise ArgumentError unless shift >= 0
+        bits_x >> shift
+      end
+      
+      def LSR_C(bits_x, shift) # A2.2.1
+        raise ArgumentError unless shift > 0
+        [bits_x >> shift, bits_x.bit(shift-1)]
+      end
+      
+      def LSL(bits_x, shift) # A2.2.1
+        raise ArgumentError unless shift >= 0
+        bits_x << shift
+      end
+      
+      def LSL_C(bits_x, shift) # A2.2.1
+        raise ArgumentError unless shift > 0
+        [bits_x << shift, bits_x.bit(shift)]
+      end
+    end
+    
+    module InstructionHelper
+      class << self
+        COND = [".EQ", ".NE", ".CS", ".CC", ".MI", ".PL", ".VS", ".VC", ".HI", ".LS", ".GE", ".LT", ".GT", ".LE", ""]
+        COND_SYM = [:eq, :ne, :cs, :cc, :mi, :pl, :vs, :vc, :hi, :ls, :ge, :lt, :gt, :le, :al]
+        NAMED_REG = { r13: :sp, r14: :lr, r15: :pc }
+        REG = [:r0, :r1, :r2, :r3, :r4, :r5, :r6, :r7, :r8, :r9, :r10, :r11, :r12, :r13, :r14, :r15]
+        SHIFT_TYPES = {
+          SRType_LSL: :lsl,
+          SRType_LSR: :lsr,
+          SRType_ASR: :asr,
+          SRType_ROR: :ror,
+          SRType_RRX: :rrx,
+        }
+        
+        def regs_from_bits(bits_list)
+          bl = bits_list.to_s(2)
+          bl = ('0'*(16-bl.length)) + bl
+          regs = []
+          bl.reverse! # XXX so that r0 is bit 0
+          bl.length.times do |i| 
+            regs << "r#{i}".to_sym if bl[i] == '1'
+          end
+          regs
+        end
+        
+        def shift_type_to_s(shift)
+          SHIFT_TYPES[shift]
+        end
+        
+        def cond_to_s(cond)
+          ('.' + cond.to_s.upcase).sub('.AL', '')
+        end
+        
+        def regs_to_s(regs)
+          regs = regs.map { |r| NAMED_REG[r] || r }
+          regs.join(', ')
+        end
+        
+        def flag(f, fn)
+          f ? fn : ''
+        end
+        
+        def reg(i)
+          r = REG[i]
+          NAMED_REG[r] || r
+        end
+        
+        def cond(i)
+          COND_SYM[i]
+        end
+        
+        include PseudoCodeInstructionHelper
+      end
+    end
+  end
+end

data/lib/indis-arm/instruction_loader.rb

@@ -0,0 +1,160 @@
+##############################################################################
+#   Indis framework                                                          #
+#   Copyright (C) 2012 Vladimir "Farcaller" Pouzanov <farcaller@gmail.com>   #
+#                                                                            #
+#   This program is free software: you can redistribute it and/or modify     #
+#   it under the terms of the GNU General Public License as published by     #
+#   the Free Software Foundation, either version 3 of the License, or        #
+#   (at your option) any later version.                                      #
+#                                                                            #
+#   This program is distributed in the hope that it will be useful,          #
+#   but WITHOUT ANY WARRANTY; without even the implied warranty of           #
+#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            #
+#   GNU General Public License for more details.                             #
+#                                                                            #
+#   You should have received a copy of the GNU General Public License        #
+#   along with this program.  If not, see <http://www.gnu.org/licenses/>.    #
+##############################################################################
+
+require 'singleton'
+require 'indis-arm/instruction'
+
+module Indis
+  module ARM
+    
+    class NotThisInstructionError < RuntimeError; end
+    class UnpredictableError < RuntimeError; end
+    
+    # InstructionLoader is a DSL parser for arm7.inst.rb DSL.
+    # The DSL is evaluated in the context of InstructionLoader singleton, the
+    # only top-level command is {Indis::ARM::InstructionLoader#instruction}
+    class InstructionLoader
+      include Singleton
+      
+      # Loads and processes the DSL
+      # @return [Array] all mapped classes from DSL
+      def load
+        return @classes if @classes
+        
+        @classes = []
+        instr_file = File.join(File.dirname(__FILE__), 'arm7.inst.rb')
+        self.instance_eval open(instr_file).read, instr_file, 1
+        
+        @classes
+      end
+      
+      # Loads a named instruction. The block is evaluated in a context of
+      # newly-created {Indis::ARM::EncodingLoader}.
+      # @param [Symbol] name instruction name
+      def instruction(name, &block)
+        el = EncodingLoader.new(name, @classes)
+        el.instance_eval(&block)
+      end
+    end
+    
+    class EncodingLoader
+      def initialize(name, arr)
+        @name = name
+        @classes = arr
+      end
+      
+      # Loads a specific instruction encoding. The block is evaluated in a
+      # context of newly-created {Indis::ARM::MnemonicLoader}.
+      # @param [Symbol] enc instruction encoding name
+      def encoding(enc, &block)
+        unless block_given?
+          #puts "Encoding #{enc} of #{@name} is undefined yet"
+          return
+        end
+        
+        name = @name
+        klass = Class.new(Indis::ARM::Instruction) { @name = name; @encoding = enc }
+        ARM.const_set("#{name}Instruction_#{enc}", klass)
+        
+        ml = MnemonicLoader.new(klass)
+        ml.instance_eval(&block)
+        
+        @classes << klass
+      end
+    end
+    
+    class MnemonicLoader
+      # A default map. Would set up the mapping only if the attribute name
+      # was passed in {Indis::ARM::MnemonicLoader#attrs}
+      AUTOMAPPED = {
+        'C' => :cond,
+        'n' => :Rn,
+        'm' => :Rm,
+        'd' => :Rd,
+        't' => :Rt,
+        'S' => :setflags,
+      }
+      
+      AUTOMAPPED_PROCS = {
+        cond: proc { |k| @cond = h.cond(k.cond) },
+        Rn: proc { |k| @Rn = h.reg(k.Rn) },
+        Rm: proc { |k| @Rm = h.reg(k.Rm) },
+        Rd: proc { |k| @Rd = h.reg(k.Rd) },
+        Rt: proc { |k| @Rt = h.reg(k.Rt) },
+        setflags: proc { |k| @setflags = k.setflags == 1 },
+      }
+      
+      def initialize(klass)
+        @klass = klass
+      end
+      
+      # Loads bit representation of instruction
+      # @overload bits(bitstring)
+      #   @param [String] bitstring a string with no special-mapped bits (either no specail bits at all, or all bits are automapped)
+      # @overload bits(bitstring, map)
+      #   @param [String] bitstring a string with bits map
+      #   @param [Hash{String => Symbol}] map a map from bit string to parsed symbol
+      def bits(*args)
+        raise "Malformed bits field" if args.length < 1 || args.length > 2
+        b = args.first
+        @klass.instance_eval { @bits = b }
+        
+        map = {}
+        AUTOMAPPED.each { |k,v| map[k] = v if @klass_attrs.include?(v) }
+        map.merge!(args[1]) if args.length == 2
+        
+        a = map.map do |v, name|
+          # TODO: chek on what happens if there is no cond 'C'
+          mask = b.gsub(Regexp.new("[^#{v}]"), '0').gsub(/[^0]/, "1")
+          ofs = mask.match(/0*$/)[0].length
+          mask = mask.to_i(2)
+          
+          [mask, ofs, name]
+        end
+        
+        @klass.instance_eval { @kmap = a }
+      end
+      
+      # Loads instruction attributes
+      def attrs(*attrs)
+        @klass_attrs = attrs
+        @klass.instance_eval { attr_reader *attrs }
+      end
+      
+      # Loads instruction format
+      def format(fmt)
+        if @klass_attrs.include?(:setflags)
+          formats = { operator: '#{self.class.name}#{h.flag @setflags, "S"}#{h.cond_to_s(@cond)}' }
+        else
+          formats = { operator: '#{self.class.name}#{h.cond_to_s(@cond)}' }
+        end
+        formats.merge!(fmt)
+        @klass.instance_eval { @formats = formats }
+      end
+      
+      # Loads instruction processing block
+      def process(&block)
+        automap_keys = @klass_attrs & AUTOMAPPED.values
+        automap_proc = AUTOMAPPED_PROCS.map { |k,p| automap_keys.include?(k) ? p : nil }.compact
+        @klass.instance_eval { @process_automap = automap_proc }
+        @klass.instance_eval { @process_block = block }
+      end
+    end
+    
+  end
+end

data/lib/indis-arm/version.rb

@@ -0,0 +1,23 @@
+##############################################################################
+#   Indis framework                                                          #
+#   Copyright (C) 2012 Vladimir "Farcaller" Pouzanov <farcaller@gmail.com>   #
+#                                                                            #
+#   This program is free software: you can redistribute it and/or modify     #
+#   it under the terms of the GNU General Public License as published by     #
+#   the Free Software Foundation, either version 3 of the License, or        #
+#   (at your option) any later version.                                      #
+#                                                                            #
+#   This program is distributed in the hope that it will be useful,          #
+#   but WITHOUT ANY WARRANTY; without even the implied warranty of           #
+#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            #
+#   GNU General Public License for more details.                             #
+#                                                                            #
+#   You should have received a copy of the GNU General Public License        #
+#   along with this program.  If not, see <http://www.gnu.org/licenses/>.    #
+##############################################################################
+
+module Indis
+  module ARM
+    VERSION = "0.3.0"
+  end
+end

data/lib/indis-arm.rb

@@ -0,0 +1,28 @@
+##############################################################################
+#   Indis framework                                                          #
+#   Copyright (C) 2012 Vladimir "Farcaller" Pouzanov <farcaller@gmail.com>   #
+#                                                                            #
+#   This program is free software: you can redistribute it and/or modify     #
+#   it under the terms of the GNU General Public License as published by     #
+#   the Free Software Foundation, either version 3 of the License, or        #
+#   (at your option) any later version.                                      #
+#                                                                            #
+#   This program is distributed in the hope that it will be useful,          #
+#   but WITHOUT ANY WARRANTY; without even the implied warranty of           #
+#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            #
+#   GNU General Public License for more details.                             #
+#                                                                            #
+#   You should have received a copy of the GNU General Public License        #
+#   along with this program.  If not, see <http://www.gnu.org/licenses/>.    #
+##############################################################################
+
+require 'indis-arm/version'
+require 'indis-arm/code_parser'
+require 'indis-arm/analyzer'
+
+module Indis
+  # Indis::ARM provides instruction parser for ARM and Thumb instruction sets.
+  module ARM
+
+  end
+end

data/spec/indis-arm/code_parser_spec.rb

@@ -0,0 +1,48 @@
+require 'indis-core/target'
+require 'indis-macho'
+require 'indis-arm/code_parser'
+
+describe Indis::ARM::CodeParser do
+  it "should decode arm instructions in given section" do
+    t = Indis::Target.new('spec/fixtures/single-object.o')
+    t.load
+    
+    section = t.segments.find { |seg| seg.name == '__TEXT' }.sections.find { |sect| sect.name == '__text' }
+    
+    code_parser = Indis::ARM::CodeParser.new(t)
+    
+    code_parser.reparse_section(section)
+    
+    sm = t.vmmap[section.to_vmrange]
+    
+    sm.each_with_index do |b, idx|
+      break if idx >= section.vmsize
+
+      if idx % 4 == 0
+        b.should be_a(Indis::Entity)
+        b.should be_a(Indis::ARM::Instruction)
+      else
+        b.should be_nil
+      end
+    end
+  end
+  
+  it "should parse known instructions" do
+    code_parser = Indis::ARM::CodeParser.new(double("Target", vmmap: double("VMMap")))
+    
+    i = code_parser.instance_eval { build_instruction(0, 0xe92d4080) }
+    i.should_not be_a(Indis::ARM::UnknownInstruction)
+  end
+  
+  it "should load instructions" do
+    Indis::ARM::CodeParser.load_instructions
+    expect { Indis::ARM.const_get('PUSHInstruction_A1') }.not_to raise_error
+  end
+  
+  it "should honor NotThisInstructionError" do
+    code_parser = Indis::ARM::CodeParser.new(double("Target", vmmap: double("VMMap")))
+    
+    i = code_parser.instance_eval { build_instruction(0, 0xe59f0024) }
+    i.class.should == Indis::ARM::LDRInstruction_A1_lit
+  end
+end

data/spec/indis-arm/instruction_helper_spec.rb

@@ -0,0 +1,29 @@
+require 'indis-arm/instruction_helper'
+
+describe Indis::ARM::InstructionHelper do
+  it "should decode registers" do
+    b = '0000111100000010'.reverse.to_i(2)
+    r = Indis::ARM::InstructionHelper.regs_from_bits(b)
+    r.should == [:r4, :r5, :r6, :r7, :r14]
+  end
+end
+
+describe Indis::ARM::PseudoCodeInstructionHelper do
+  it "should perform ZeroExtend" do
+    Indis::ARM::InstructionHelper.ZeroExtend('1101'.to_bo, 6).to_s.should == '001101'
+  end
+  
+  it "should perform LSR" do
+    a = Indis::ARM::InstructionHelper.LSR_C('101100'.to_bo, 3)
+    a[0].to_s.should == '000101'
+    a[1].should == 1
+  end
+  
+  it "should perform Shift_C" do
+    Indis::ARM::InstructionHelper.Shift_C('101100'.to_bo, :SRType_ROR, 2, 0).map{|v|v.to_s}.should == ['001011', '1']
+  end
+  
+  it "should perform ARMExpandImm_C" do
+    Indis::ARM::InstructionHelper.ARMExpandImm('000000001100'.to_bo).to_i.should == 12
+  end
+end

data/spec/indis-arm/instruction_loader_spec.rb

@@ -0,0 +1,76 @@
+require 'indis-arm/instruction_loader'
+
+describe Indis::ARM::InstructionLoader do
+  before(:all) { Indis::ARM::InstructionLoader.instance.load }
+  
+  it "should load instructions" do
+    expect { Indis::ARM.const_get('PUSHInstruction_A1') }.not_to raise_error
+  end
+  
+  it "should parse bitmap to mask and match" do
+    Indis::ARM::PUSHInstruction_A1.bits_mask.should == 0xfff0000
+    Indis::ARM::PUSHInstruction_A1.bits_match.should == 0x92d0000
+  end
+  
+  it "should create attr_readers for fields" do
+    i = Indis::ARM::PUSHInstruction_A1.new(0, 0xe92d4080)
+    expect { i.regs }.not_to raise_error(NoMethodError)
+  end
+  
+  it "should make a keymap for passed values" do
+    m = Indis::ARM::PUSHInstruction_A1.kmap(0xe92d4080)
+    m.cond.should == 0xe
+    m.regs_list.should == 0x4080
+  end
+  
+  it "should eval process block and set ivars" do
+    i = Indis::ARM::PUSHInstruction_A1.new(0, 0xe92d4080)
+    i.regs.should == [:r7, :r14]
+  end
+  
+  it "should set instruction name" do
+    Indis::ARM::PUSHInstruction_A1.name.should == :PUSH
+  end
+  
+  it "should set instruction encoding" do
+    Indis::ARM::PUSHInstruction_A1.encoding.should == :A1
+  end
+  
+  it "should raise NotThisInstructionError if the other mnemonic should be searched for" do
+    expect { Indis::ARM::LDRInstruction_A1_imm.new(0, 0xe59f0024) }.to raise_error(Indis::ARM::NotThisInstructionError)
+  end
+  
+  it "should provide full mnemonic when asked to_s" do
+    Indis::ARM::PUSHInstruction_A1.new(0, 0xe92d4080).to_s.should == "PUSH\t{r7, lr}"
+    Indis::ARM::MOVInstruction_A1_reg.new(0, 0xe1a0700d).to_s.should == "MOV\tr7, sp"
+    Indis::ARM::SUBInstruction_A1_spimm.new(0, 0xe24dd00c).to_s.should == "SUB\tsp, sp, #12"
+    Indis::ARM::STRInstruction_A1_imm.new(0, 0xe5070004).to_s.should == "STR\tr0, [r7, #-4]"
+    Indis::ARM::STRInstruction_A1_imm.new(0, 0xe58d1004).to_s.should == "STR\tr1, [sp, #4]"
+    Indis::ARM::LDRInstruction_A1_imm.new(0, 0xe5171004).to_s.should == "LDR\tr1, [r7, #-4]"
+    Indis::ARM::LDRInstruction_A1_imm.new(0, 0xe59d2004).to_s.should == "LDR\tr2, [sp, #4]"
+    Indis::ARM::LDRInstruction_A1_lit.new(0, 0xe59f0024).to_s.should == "LDR\tr0, [pc, #36]"
+    Indis::ARM::LDRInstruction_A1_reg.new(0, 0xe79f1001).to_s.should == "LDR\tr1, [pc, r1]"
+    Indis::ARM::ADDInstruction_A1_imm.new(0, 0xe2804001).to_s.should == "ADD\tr4, r0, #1"
+  end
+  
+  it "should provide cond when there is 'C' in bits" do
+    i = Indis::ARM::PUSHInstruction_A1.new(0, 0xe92d4080)
+    i.cond.should == :al
+  end
+  
+  it "should not provide cond when there is no 'C' in bits" do
+    i = Indis::ARM::DMBInstruction_A1.new(0, 0xf57ff05f)
+    expect { i.cond }.to raise_error(NoMethodError)
+  end
+  
+  it "should provide Rx when there are 'n', 'd', 'm' in bits" do
+    i = Indis::ARM::MOVInstruction_A1_reg.new(0, 0xe1a0700d)
+    i.Rd.should == :r7
+    i.Rm.should == :sp
+  end
+  
+  it "should not provide Rx when there are no 'n', 'd', 'm' in bits" do
+    i = Indis::ARM::MOVInstruction_A1_reg.new(0, 0xe1a0700d)
+    expect { i.Rn }.to raise_error(NoMethodError)
+  end
+end

data/spec/spec_helper.rb

@@ -0,0 +1,8 @@
+require 'rubygems'
+require 'bundler/setup'
+
+RSpec.configure do |config|
+  config.treat_symbols_as_metadata_keys_with_true_values = true
+  config.run_all_when_everything_filtered = true
+  config.filter_run :focus
+end