indis-arm 0.3.0

data/Rakefile

@@ -0,0 +1,9 @@
+#!/usr/bin/env rake
+
+require "bundler/gem_tasks"
+Bundler::GemHelper.install_tasks
+
+require 'rspec/core/rake_task'
+RSpec::Core::RakeTask.new('spec')
+
+task :default => :spec

data/indis-arm.gemspec

@@ -0,0 +1,22 @@
+# -*- encoding: utf-8 -*-
+require File.expand_path('../lib/indis-arm/version', __FILE__)
+
+Gem::Specification.new do |gem|
+  gem.authors       = ["Vladimir Pouzanov"]
+  gem.email         = ["farcaller@gmail.com"]
+  gem.description   = "ARM and Thumb instruction set code parser for indis"
+  gem.summary       = "ARM and Thumb instruction set code parser for indis"
+  gem.homepage      = "http://www.indis.org/"
+  gem.license       = "GPL-3"
+
+  gem.files         = `git ls-files`.split($\)
+  gem.executables   = gem.files.grep(%r{^bin/}).map{ |f| File.basename(f) }
+  gem.test_files    = gem.files.grep(%r{^(test|spec|features)/})
+  gem.name          = "indis-arm"
+  gem.require_paths = ["lib"]
+  gem.version       = Indis::ARM::VERSION
+
+  gem.add_development_dependency 'rspec'
+  gem.add_development_dependency 'indis-macho', '~> 0.3.0'
+  gem.add_runtime_dependency 'indis-core', '~> 0.1.2'
+end

data/lib/indis-arm/analyzer/bl_analyzer.rb

@@ -0,0 +1,20 @@
+module Indis
+  module ARM
+    module Analyzer
+      
+      class BLAnalyzer < Analyzer
+        
+        def initialize(target)
+          super target, :instruction_mapped
+        end
+        
+        def instruction_mapped(instr)
+          return unless instr.class.name == :BL
+          sym = @target.resolve_symbol_at_address(instr.branch_address)
+          instr.tags[:branch_to_sym] = sym if sym
+        end
+      end
+      
+    end
+  end
+end

data/lib/indis-arm/analyzer/ldr_lit_analyzer.rb

@@ -0,0 +1,25 @@
+require 'indis-core/data_entity'
+
+module Indis
+  module ARM
+    module Analyzer
+      
+      class LDRLitAnalyzer < Analyzer
+        
+        def initialize(target)
+          super target, :instruction_mapped
+        end
+        
+        def instruction_mapped(instr)
+          return unless instr.class.name == :LDR && instr.class.encoding == :A1_lit
+          
+          datab = Indis::DataEntity.new(instr.vmaddr+instr.imm+8, 4, @target.vmmap)
+          @target.vmmap.map!(datab)
+          instr.tags[:value] = datab
+          datab.tags[:loaded_by] = instr
+        end
+      end
+      
+    end
+  end
+end

data/lib/indis-arm/analyzer.rb

@@ -0,0 +1,17 @@
+module Indis
+  module ARM
+    module Analyzer
+      
+      class Analyzer
+        def initialize(target, evt)
+          @target = target
+          target.subscribe_for_event(evt, self)
+        end
+      end
+      
+    end
+  end
+end
+
+require 'indis-arm/analyzer/bl_analyzer'
+require 'indis-arm/analyzer/ldr_lit_analyzer'

data/lib/indis-arm/arm7.inst.rb

@@ -0,0 +1,415 @@
+##############################################################################
+#   Indis framework                                                          #
+#   Copyright (C) 2012 Vladimir "Farcaller" Pouzanov <farcaller@gmail.com>   #
+#                                                                            #
+#   This program is free software: you can redistribute it and/or modify     #
+#   it under the terms of the GNU General Public License as published by     #
+#   the Free Software Foundation, either version 3 of the License, or        #
+#   (at your option) any later version.                                      #
+#                                                                            #
+#   This program is distributed in the hope that it will be useful,          #
+#   but WITHOUT ANY WARRANTY; without even the implied warranty of           #
+#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            #
+#   GNU General Public License for more details.                             #
+#                                                                            #
+#   You should have received a copy of the GNU General Public License        #
+#   along with this program.  If not, see <http://www.gnu.org/licenses/>.    #
+##############################################################################
+
+instruction :ADD do # 8.8.4-11
+  encoding :T1_imm
+  encoding :T2_imm
+  encoding :T3_imm
+  encoding :T4_imm
+  encoding :A1_imm do
+    attrs :cond, :Rd, :Rn, :imm, :setflags
+    bits 'CCCC0010100Snnnnddddiiiiiiiiiiii', 'i' => :imm12
+    format value: '#{@Rd}, #{@Rn}, ##{@imm}'
+    process do |k|
+      raise Indis::ARM::NotThisInstructionError if k.Rn == 0b1111 && k.setflags == 0 # ADR
+      raise Indis::ARM::NotThisInstructionError if k.Rn == 0b1101 # ADD:spimm
+      raise Indis::ARM::NotThisInstructionError if k.Rd == 0b1111 && k.setflags == 1 # SUBS PC, LR
+      @imm = h.ARMExpandImm(k.imm12.to_boz(12)).to_i
+    end
+  end
+  encoding :T1_reg
+  encoding :T2_reg
+  encoding :A1_reg do
+    attrs :cond, :Rd, :Rn, :Rm, :imm, :setflags, :imm_shift
+    bits 'CCCC0000100SnnnnddddiiiiiTT0mmmm', 'i' => :imm5, 'T' => :type
+    format value: '#{@Rd}, #{@Rn}, #{@Rm}#{@imm > 0 ? ", #{h.shift_type_to_s(@imm_shift)} ##{@imm}" : "" }'
+    process do |k|
+      # FIXME: mnemonic is wrong?
+      raise Indis::ARM::NotThisInstructionError if k.Rd == 0b1111 && k.setflags == 1 # SUBS PC, LR
+      raise Indis::ARM::NotThisInstructionError if k.Rn == 0b1101 # ADD:spreg
+      (@imm_shift, @imm) = h.DecodeImmShift(k.type.to_bo, k.imm5.to_bo)
+      @imm = @imm.to_i
+    end
+  end
+  encoding :A1_rsr
+  encoding :T1_spimm
+  encoding :T2_spimm
+  encoding :T3_spimm
+  encoding :T4_spimm
+  encoding :A1_spimm do
+    attrs :cond, :Rd, :imm, :setflags
+    bits 'CCCC0010100S1101ddddiiiiiiiiiiii', 'i' => :imm12
+    format value: '#{@Rd}, sp, ##{@imm}'
+    process do |k|
+      raise Indis::ARM::NotThisInstructionError if k.Rd == 0b1111 && k.setflags == 1 # SUBS PC, LR
+      @imm = h.ARMExpandImm(k.imm12.to_boz(12)).to_i
+    end
+  end
+  encoding :T1_spreg
+  encoding :T2_spreg
+  encoding :T3_spreg
+  encoding :A1_spreg
+end
+
+instruction :B do # 8.8.18
+  encoding :T1
+  encoding :T2
+  encoding :T3
+  encoding :T4
+  encoding :A1 do
+    attrs :cond, :imm, :branch_address
+    bits 'CCCC1010iiiiiiiiiiiiiiiiiiiiiiii', 'i' => :imm24
+    format value:       '##{@imm}',
+           value_const: '#{sprintf("0x%x", @branch_address)}'
+    process do |k|
+      @imm = h.SignExtend(k.imm24.to_boz(24) << 2, 32).to_signed_i
+      @value_format = :value_const
+      @branch_address = @vmaddr+8+@imm
+    end
+  end
+end
+
+instruction :BIC do # 8.8.21
+  encoding :T1_imm
+  encoding :A1_imm do
+    attrs :cond, :setflags, :Rn, :Rd, :imm
+    bits 'CCCC0011110Snnnnddddiiiiiiiiiiii', 'i' => :imm12
+    format value: '#{@Rd}, #{@Rn}, ##{@imm}'
+    process do |k|
+      (@imm, @carry) = h.ARMExpandImm_C(k.imm12.to_boz(12), 0) # TODO: APSR.C ?
+      @imm = @imm.to_i
+    end
+  end
+  encoding :T1_reg
+  encoding :T2_reg
+  encoding :A1_reg do
+    attrs :cond, :setflags, :Rn, :Rd, :Rm, :imm, :imm_shift
+    bits 'CCCC0001110SnnnnddddiiiiiTT0mmmm', 'i' => :imm5, 'T' => :type
+    format value: '#{@Rd}, #{@Rn}, #{@Rm}#{@imm > 0 ? ", #{h.shift_type_to_s(@imm_shift)} ##{@imm}" : "" }'
+    process do |k|
+      raise Indis::ARM::NotThisInstructionError if k.Rd = 0b1111 && k.setflags == 1 # SUBS PC, LR
+      (@imm_shift, @imm) = h.DecodeImmShift(k.type.to_bo, k.imm5.to_bo)
+      @imm = @imm.to_i
+    end
+  end
+  encoding :A1_rsr
+end
+
+instruction :BL do # 8.8.25
+  encoding :T1
+  encoding :T2
+  encoding :A1 do
+    attrs :cond, :imm, :target_instr_set, :branch_address
+    bits 'CCCC1011iiiiiiiiiiiiiiiiiiiiiiii', 'i' => :imm24
+    format value:       '##{@imm}',
+           value_const: '#{sprintf("0x%x", @branch_address)}'
+    process do |k|
+      @imm = h.SignExtend(k.imm24.to_boz(24) << 2, 32).to_signed_i
+      @target_instr_set = :arm
+      @value_format = :value_const
+      @branch_address = @vmaddr+8+@imm
+    end
+  end
+  encoding :A2 do
+    attrs :imm, :target_instr_set, :branch_address
+    bits '1111101Hiiiiiiiiiiiiiiiiiiiiiiii', 'i' => :imm24, 'H' => :h
+    format operator:    'BLX',
+           value:       '##{@imm}',
+           value_const: '#{sprintf("0x%x", @branch_address)}'
+    process do |k|
+      # FIXME what is H used for?..
+      @imm = h.SignExtend(k.imm24.to_boz(24) << 2, 32).to_signed_i
+      @target_instr_set = :thumb
+      @value_format = :value_const
+      @branch_address = @vmaddr+8+@imm
+    end
+  end
+end
+
+instruction :CMP do # 8.8.37-39
+  encoding :T1_imm
+  encoding :T2_imm
+  encoding :A1_imm do
+    attrs :cond, :Rn, :imm
+    bits 'CCCC00110101nnnn0000iiiiiiiiiiii', 'i' => :imm12
+    format value: '#{@Rn}, ##{@imm}'
+    process do |k|
+      @imm = h.ARMExpandImm(k.imm12.to_boz(12)).to_i
+    end
+  end
+  encoding :T1_reg
+  encoding :T2_reg
+  encoding :T3_reg
+  encoding :A1_reg
+  encoding :A1_rsr
+end
+
+instruction :DMB do # 8.8.43
+  encoding :T1
+  encoding :A1 do
+    attrs :option
+    bits '1111010101111111111100000101oooo', 'o' => :option
+    format value: '#{@option == :sy ? "" : "#{@option}" }'
+    process do |k|
+      @option = {
+        0b1111 => :sy,  0b1110 => :st,    0b1011 => :ish, 0b1010 => :ishst,
+        0b0111 => :nsh, 0b0110 => :nshst, 0b0011 => :osh, 0b0010 => :oshst,
+      }[k.option]
+    end
+  end
+end
+
+instruction :MOV do # 8.8.102-105
+  encoding :T1_imm
+  encoding :T2_imm
+  encoding :T3_imm
+  encoding :A1_imm do
+    attrs :cond, :Rd, :imm, :setflags
+    bits 'CCCC0011101S0000ddddiiiiiiiiiiii', 'i' => :imm12
+    format value: '#{@Rd}, ##{@imm}'
+    process do |k|
+      raise NotThisInstructionError if k.Rd == 0b1111 && k.setflags == 1 # SUBS PC, LR
+      (@imm, @carry) = h.ARMExpandImm_C(k.imm12.to_boz(12), 0) # TODO: APSR.C ?
+      @imm = @imm.to_i
+    end
+  end
+  encoding :A2_imm do
+    attrs :cond, :Rd, :imm
+    bits 'CCCC00110000jjjjddddiiiiiiiiiiii', 'i' => :imm12, 'j' => :imm4
+    format operator: 'MOVW#{h.cond_to_s(@cond)}',
+           value:    '#{@Rd}, ##{@imm}'
+    process do |k|
+      @imm = h.ZeroExtend(k.imm4.to_boz(4).concat(k.imm12.to_boz(12)), 32).to_i
+      raise UnpredictableError if k.Rd == 15
+    end
+  end
+  encoding :T1_reg
+  encoding :T2_reg
+  encoding :T3_reg
+  encoding :A1_reg do
+    attrs :cond, :Rd, :Rm, :setflags
+    bits 'CCCC0001101S0000dddd00000000mmmm'
+    format value: '#{@Rd}, #{@Rm}'
+    process do |k|
+      raise Indis::ARM::NotThisInstructionError if k.Rd == 0b1111 && k.setflags == 1
+    end
+  end
+end
+
+instruction :MOVT do # 8.8.106
+  encoding :T1
+  encoding :A1 do
+    attrs :cond, :Rd, :imm
+    bits 'CCCC00110100jjjjddddiiiiiiiiiiii', 'i' => :imm12, 'j' => :imm4
+    format value: '#{@Rd}, ##{@imm}'
+    process do |k|
+      @imm = k.imm4.to_boz(4).concat(k.imm12.to_boz(12)).to_i
+      raise UnpredictableError if k.Rd == 15
+    end
+  end
+end
+
+instruction :POP do # 8.8.131-132
+  encoding :T1
+  encoding :T2
+  encoding :T3
+  encoding :A1 do
+    attrs :cond, :regs
+    bits 'CCCC100010111101rrrrrrrrrrrrrrrr', 'r' => :regs_list
+    format value: '{#{h.regs_to_s(@regs)}}'
+    process do |k|
+      @regs = h.regs_from_bits(k.regs_list)
+      raise Indis::ARM::NotThisInstructionError if @regs.length < 2
+      # XXX: UnalignedAllowed = FALSE;
+      raise UnpredictableError if @regs.include?(:sp)
+    end
+  end
+  encoding :A2
+end
+
+instruction :PUSH do # 8.8.133
+  encoding :T1
+  encoding :T2
+  encoding :T3
+  encoding :A1 do
+    attrs :cond, :regs
+    bits 'CCCC100100101101rrrrrrrrrrrrrrrr', 'r' => :regs_list
+    format value: '{#{h.regs_to_s(@regs)}}'
+    process do |k|
+      @regs = h.regs_from_bits(k.regs_list)
+      raise Indis::ARM::NotThisInstructionError if @regs.length < 2
+    end
+  end
+  encoding :A2
+end
+
+instruction :SUB do # 8.8.221-226
+  encoding :T1_imm
+  encoding :T2_imm
+  encoding :T3_imm
+  encoding :T4_imm
+  encoding :A1_imm
+  encoding :T1_reg
+  encoding :T2_reg
+  encoding :A1_reg
+  encoding :A1_rsr
+  encoding :T1_spimm
+  encoding :T2_spimm
+  encoding :T3_spimm
+  encoding :A1_spimm do
+    attrs :cond, :Rd, :imm, :setflags
+    bits 'CCCC0010010S1101ddddiiiiiiiiiiii', 'i' => :imm12
+    format value: '#{@Rd}, sp, ##{@imm}'
+    process do |k|
+      raise Indis::ARM::NotThisInstructionError if k.Rd == 0b1111 && k.setflags == 1
+      @imm = h.ARMExpandImm(k.imm12.to_boz(12)).to_i
+    end
+  end
+  encoding :T1_spreg
+  encoding :A1_spreg
+end
+
+instruction :STR do # 8.8.203-205
+  encoding :T1_imm
+  encoding :T2_imm
+  encoding :T3_imm
+  encoding :T4_imm
+  encoding :A1_imm do
+    attrs :cond, :Rn, :Rt, :imm, :add, :index, :wback
+    bits 'CCCC010PU0W0nnnnttttiiiiiiiiiiii', 'P' => :p, 'U' => :u, 'W' => :w, 'i' => :imm12
+    format value_offset:      '#{@Rt}, [#{@Rn}#{@imm != 0 ? ", ##{@imm}" : ""}]',
+           value_preindexed:  '#{@Rt}, [#{@Rn}, ##{@imm}]!',
+           value_postindexed: '#{@Rt}, [#{@Rn}], ##{@imm}'
+    process do |k|
+      raise Indis::ARM::NotThisInstructionError if k.p == 0 && k.w == 1 # STRT
+      raise Indis::ARM::NotThisInstructionError if k.Rn == 0b1101 && k.p == 1 && k.u == 0 && k.w == 1 && k.imm12 == 0b100 # PUSH
+      @index = k.p == 1
+      @add = k.u == 1
+      if @add
+        @imm = k.imm12 # XXX: zero_expand(32)
+      else
+        @imm = -k.imm12 # XXX: zero_expand(32)
+      end
+      @wback = (k.p == 0 || k.w == 1)
+      raise Indis::ARM::UnpredictableError if @wback && (k.Rn == 15 || k.Rn == k.Rt)
+      
+      if @index && !@wback
+        @value_format = :value_offset
+      elsif @index && @wback
+        @value_format = :value_preindexed
+      elsif !@index && @wback
+        @value_format = :value_postindexed
+      else
+        raise "Unknown format combo"
+      end
+    end
+  end
+  encoding :T1_reg
+  encoding :T2_reg
+  encoding :A1_reg
+end
+
+instruction :LDR do # 8.8.62-66
+  encoding :T1_imm
+  encoding :T2_imm
+  encoding :T3_imm
+  encoding :T4_imm
+  encoding :A1_imm do
+    attrs :cond, :Rn, :Rt, :imm, :add, :index, :wback
+    bits 'CCCC010PU0W1nnnnttttiiiiiiiiiiii', 'P' => :p, 'U' => :u, 'W' => :w, 'i' => :imm12
+    format value_offset:      '#{@Rt}, [#{@Rn}#{@imm != 0 ? ", ##{@imm}" : ""}]',
+           value_preindexed:  '#{@Rt}, [#{@Rn}, ##{@imm}]!',
+           value_postindexed: '#{@Rt}, [#{@Rn}], ##{@imm}'
+    process do |k|
+      raise Indis::ARM::NotThisInstructionError if k.Rn == 0b1111 # LDR :A1_lit
+      raise Indis::ARM::NotThisInstructionError if k.p == 0 && k.w == 1 # LDRT
+      raise Indis::ARM::NotThisInstructionError if k.Rn == 0b1101 && k.p == 0 && k.u == 1 && k.w == 0 && k.imm12 == 0b100 # POP
+      @index = k.p == 1
+      @add = k.u == 1
+      if @add
+        @imm = k.imm12 # XXX: zero_expand(32)
+      else
+        @imm = -k.imm12 # XXX: zero_expand(32)
+      end
+      @wback = (k.p == 0 || k.w == 1)
+      raise Indis::ARM::UnpredictableError if @wback && (k.Rn == k.Rt)
+      
+      if @index && !@wback
+        @value_format = :value_offset
+      elsif @index && @wback
+        @value_format = :value_preindexed
+      elsif !@index && @wback
+        @value_format = :value_postindexed
+      else
+        raise "Unknown format combo"
+      end
+    end
+  end
+  encoding :T1_lit
+  encoding :T2_lit
+  encoding :A1_lit do
+    attrs :cond, :Rn, :Rt, :imm, :add
+    bits 'CCCC0101U0011111ttttiiiiiiiiiiii', 'U' => :u, 'i' => :imm12
+    format value:       '#{@Rt}, [#{@Rn}, ##{@imm}]',
+           value_const: '#{@Rt}, [#{@va+8+@imm}]',
+           value_xref:  '#{@Rt}, =0x#{@xrefs[:value].value.to_s(16)}'
+    process do |k|
+      @Rn = :pc
+      @add = k.u == 1
+      if @add
+        @imm = k.imm12 # XXX: zero_expand(32)
+      else
+        @imm = -k.imm12 # XXX: zero_expand(32)
+      end
+    end
+  end
+  encoding :T1_reg
+  encoding :T2_reg
+  encoding :A1_reg do
+    attrs :cond, :Rn, :Rt, :Rm, :imm, :add, :index, :wback, :imm_shift
+    bits 'CCCC011PU0W1nnnnttttiiiiiTT0mmmm', 'P' => :p, 'U' => :u, 'W' => :w, 'i' => :imm5, 'T' => :type
+    format value_offset:      '#{@Rt}, [#{@Rn}, #{@Rm}#{@imm != 0 ? ", ##{@imm}" : ""}]',
+           value_preindexed:  '#{@Rt}, [#{@Rn}, #{@Rm}#{@imm != 0 ? ", ##{@imm}" : ""}]!',
+           value_postindexed: '#{@Rt}, [#{@Rn}], #{@Rm}#{@imm != 0 ? ", ##{@imm}" : ""}'
+    process do |k|
+      raise Indis::ARM::NotThisInstructionError if k.p == 0 && k.w == 1 # LDRT
+      @index = k.p == 1
+      @add = k.u == 1
+      (@imm_shift, @imm) = h.DecodeImmShift(k.type.to_bo, k.imm5.to_bo)
+      if @add
+        @imm = @imm.to_i
+      else
+        @imm = -(@imm.to_i)
+      end
+      @wback = (k.p == 0 || k.w == 1)
+      raise Indis::ARM::UnpredictableError if k.Rm == 15
+      raise Indis::ARM::UnpredictableError if @wback && (k.Rn == k.Rt)
+      # TODO: also raise on: if ArchVersion() < 6 && wback && m == n then UNPREDICTABLE
+      
+      if @index && !@wback
+        @value_format = :value_offset
+      elsif @index && @wback
+        @value_format = :value_preindexed
+      elsif !@index && @wback
+        @value_format = :value_postindexed
+      else
+        raise "Unknown format combo"
+      end
+    end
+  end
+end

data/lib/indis-arm/code_parser.rb

@@ -0,0 +1,109 @@
+##############################################################################
+#   Indis framework                                                          #
+#   Copyright (C) 2012 Vladimir "Farcaller" Pouzanov <farcaller@gmail.com>   #
+#                                                                            #
+#   This program is free software: you can redistribute it and/or modify     #
+#   it under the terms of the GNU General Public License as published by     #
+#   the Free Software Foundation, either version 3 of the License, or        #
+#   (at your option) any later version.                                      #
+#                                                                            #
+#   This program is distributed in the hope that it will be useful,          #
+#   but WITHOUT ANY WARRANTY; without even the implied warranty of           #
+#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            #
+#   GNU General Public License for more details.                             #
+#                                                                            #
+#   You should have received a copy of the GNU General Public License        #
+#   along with this program.  If not, see <http://www.gnu.org/licenses/>.    #
+##############################################################################
+
+require 'indis-arm/cpu_state'
+require 'indis-arm/instruction'
+require 'indis-arm/instruction_loader'
+
+module Indis
+  module ARM
+  
+    class CodeParser
+      attr_accessor :endianness
+      
+      def initialize(target)
+        @target = target
+        @map = target.vmmap
+        
+        @endianness = :little
+        @state = CpuState.new
+      end
+      
+      def reparse_section(sect)
+        virt_addr = sect.vmaddr
+        io = StringIO.new(sect.bytes)
+        
+        while virt_addr < sect.vmaddr + sect.vmsize
+          @state.pc = virt_addr + 8 # XXX: 4 for thumb
+          
+          bytes = io.read(4)
+
+          unless @map.has_unmapped(virt_addr, 4)
+            virt_addr += 4 # TODO: skip 2 for thumb
+            next
+          end
+          
+          i = build_instruction(virt_addr, bytes.unpack('V')[0])
+          @map.map(i)
+          @target.publish_event(:instruction_mapped, i)
+          
+          if i.size == 2
+            io.ungetbyte(bytes[2..-1])
+            virt_addr += 2
+          else
+            virt_addr += 4
+          end
+        end
+      end
+      
+      def endianness=(en)
+        raise "Unknown endianness set" unless en == :big || en == :little
+        @endianness = en
+      end
+      
+      private
+      def build_instruction(va, bytes)
+        CodeParser.instruction_masks.each do |m, arr|
+          instr = arr.find { |i| (bytes & m) == i.bits_match}
+          begin
+            return instr.new(va, bytes) if instr
+          rescue NotThisInstructionError
+            next
+          end
+        end
+        UnknownInstruction.new(va, bytes)
+      end
+      
+      class << self
+        def instruction_masks
+          @instruction_masks = load_instructions unless @instruction_masks
+
+          @instruction_masks
+        end
+        
+        def load_instructions
+          masks = {}
+          
+          InstructionLoader.instance.load.each do |klass|
+            m = klass.bits_mask
+            a = masks[m]
+            unless a
+              a = []
+              masks[m] = a
+            end
+            
+            a << klass
+          end
+          
+          masks
+        end
+      end
+    end
+    
+  end
+end

data/lib/indis-arm/cpu_state.rb

@@ -0,0 +1,34 @@
+##############################################################################
+#   Indis framework                                                          #
+#   Copyright (C) 2012 Vladimir "Farcaller" Pouzanov <farcaller@gmail.com>   #
+#                                                                            #
+#   This program is free software: you can redistribute it and/or modify     #
+#   it under the terms of the GNU General Public License as published by     #
+#   the Free Software Foundation, either version 3 of the License, or        #
+#   (at your option) any later version.                                      #
+#                                                                            #
+#   This program is distributed in the hope that it will be useful,          #
+#   but WITHOUT ANY WARRANTY; without even the implied warranty of           #
+#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            #
+#   GNU General Public License for more details.                             #
+#                                                                            #
+#   You should have received a copy of the GNU General Public License        #
+#   along with this program.  If not, see <http://www.gnu.org/licenses/>.    #
+##############################################################################
+
+module Indis
+  module ARM
+    class CpuState
+      16.times { |i| attr_accessor "r#{i}" }
+      
+      alias :sp :r13
+      alias :sp= :r13=
+      
+      alias :lr :r14
+      alias :lr= :r14=
+      
+      alias :pc :r15
+      alias :pc= :r15=
+    end
+  end
+end