gupl 0.0.1

data/example/command_parser_tb.vhd

@@ -0,0 +1,172 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity command_parser_tb is
+end entity command_parser_tb;
+
+architecture BEHAV of command_parser_tb is
+  
+  component command_parser
+    port(
+      -- input
+      UPL_input_data : in std_logic_vector(128-1 downto 0);
+      UPL_input_en : in std_logic;
+      UPL_input_req : in std_logic;
+      UPL_input_ack : out std_logic;
+      
+      -- forward_input
+      UPL_forward_input_data : in std_logic_vector(128-1 downto 0);
+      UPL_forward_input_en : in std_logic;
+      UPL_forward_input_req : in std_logic;
+      UPL_forward_input_ack : out std_logic;
+      
+      -- output
+      UPL_output_data : out std_logic_vector(128-1 downto 0);
+      UPL_output_en : out std_logic;
+      UPL_output_req : out std_logic;
+      UPL_output_ack : in std_logic;
+      
+      -- forward_output
+      UPL_forward_output_data : out std_logic_vector(128-1 downto 0);
+      UPL_forward_output_en : out std_logic;
+      UPL_forward_output_req : out std_logic;
+      UPL_forward_output_ack : in std_logic;
+      
+      -- user-defiend ports
+      synch_sender_kick : out std_logic;
+      synch_sender_busy : in std_logic;
+      synch_target_addr : out std_logic_vector(32-1 downto 0);
+      global_clock : in std_logic_vector(64-1 downto 0);
+      global_clock_clear : out std_logic;
+      
+      -- system clock and reset
+      clk : in std_logic;
+      reset : in std_logic
+      );
+  end component command_parser;
+
+  signal UPL_input_data          : std_logic_vector(128-1 downto 0) := (others => '0');
+  signal UPL_input_en            : std_logic := '0';
+  signal UPL_input_req           : std_logic := '0';
+  signal UPL_input_ack           : std_logic := '0';
+  signal UPL_forward_input_data  : std_logic_vector(128-1 downto 0) := (others => '0');
+  signal UPL_forward_input_en    : std_logic := '0';
+  signal UPL_forward_input_req   : std_logic := '0';
+  signal UPL_forward_input_ack   : std_logic := '0';
+  signal UPL_output_data         : std_logic_vector(128-1 downto 0) := (others => '0');
+  signal UPL_output_en           : std_logic := '0';
+  signal UPL_output_req          : std_logic := '0';
+  signal UPL_output_ack          : std_logic := '0';
+  signal UPL_forward_output_data : std_logic_vector(128-1 downto 0) := (others => '0');
+  signal UPL_forward_output_en   : std_logic := '0';
+  signal UPL_forward_output_req  : std_logic := '0';
+  signal UPL_forward_output_ack  : std_logic := '0';
+  signal synch_sender_kick       : std_logic;
+  signal synch_sender_busy       : std_logic := '0';
+  signal synch_target_addr       : std_logic_vector(32-1 downto 0) := (others => '0');
+  signal global_clock            : std_logic_vector(64-1 downto 0) := (others => '0');
+  signal global_clock_clear      : std_logic;
+  signal clk                     : std_logic := '0';
+  signal reset                   : std_logic := '0';
+
+  signal counter : unsigned(31 downto 0) := (others => '0');
+  
+begin
+
+  process
+  begin
+    clk <= not clk;
+    wait for 5ns;
+  end process;
+
+  process(clk)
+  begin
+    if rising_edge(clk) then
+      counter <= counter + 1;
+      
+      if global_clock_clear = '1' then
+        global_clock <= (others => '0');
+      else
+        global_clock <= std_logic_vector(unsigned(global_clock) + 1);
+      end if;
+    
+      case to_integer(counter) is
+        when 1 =>
+          reset <= '1';
+        when 10 =>
+          reset <= '0';
+          UPL_output_ack <= '1';
+          UPL_forward_output_ack <= '1';
+
+        when 100 =>
+          UPL_input_en <= '1';
+          UPL_input_data <= X"0a000001" & X"0a000003" & X"40004001" & X"00000008";
+        when 101 =>
+          UPL_input_en <= '1';
+          UPL_input_data <= X"34000000" & X"00000000" & X"00000000" & X"00000000";
+        when 102 =>
+          UPL_input_en <= '0';
+
+        when 200 =>
+          UPL_input_en <= '1';
+          UPL_input_data <= X"0a000001" & X"0a000003" & X"40004001" & std_logic_vector(to_unsigned(64, 32));
+        when 201 =>
+          UPL_input_en <= '1';
+          UPL_input_data <= X"32000000" & X"00000000" & X"0a020001" & X"00004000";
+        when 202 =>
+          UPL_input_en <= '1';
+          UPL_input_data <= X"0a020002" & X"00004001" & X"0a020003" & X"00004002";
+        when 203 =>
+          UPL_input_en <= '1';
+          UPL_input_data <= X"0a020004" & X"00004003" & X"0a020005" & X"00004004";
+        when 204 =>
+          UPL_input_en <= '1';
+          UPL_input_data <= X"0a020006" & X"00004005" & X"0a020007" & X"00004006";
+        when 205 =>
+          UPL_input_en <= '0';
+
+        when others => null;
+      end case;
+    end if;
+  end process;
+      
+  DUT : command_parser
+    port map(
+      -- input
+      UPL_input_data => UPL_input_data,
+      UPL_input_en   => UPL_input_en,
+      UPL_input_req  => UPL_input_req,
+      UPL_input_ack  => UPL_input_ack,
+
+      -- forward_input
+      UPL_forward_input_data => UPL_forward_input_data,
+      UPL_forward_input_en   => UPL_forward_input_en,
+      UPL_forward_input_req  => UPL_forward_input_req,
+      UPL_forward_input_ack  => UPL_forward_input_ack,
+
+      -- output
+      UPL_output_data => UPL_output_data,
+      UPL_output_en   => UPL_output_en,
+      UPL_output_req  => UPL_output_req,
+      UPL_output_ack  => UPL_output_ack,
+
+      -- forward_output
+      UPL_forward_output_data => UPL_forward_output_data,
+      UPL_forward_output_en   => UPL_forward_output_en,
+      UPL_forward_output_req  => UPL_forward_output_req,
+      UPL_forward_output_ack  => UPL_forward_output_ack,
+
+      -- user-defiend ports
+      synch_sender_kick  => synch_sender_kick,
+      synch_sender_busy  => synch_sender_busy,
+      synch_target_addr  => synch_target_addr,
+      global_clock       => global_clock,
+      global_clock_clear => global_clock_clear,
+
+      -- system clock and reset
+      clk   => clk,
+      reset => reset
+      );
+  
+end BEHAV;

data/example/sendrecv.gupl

@@ -0,0 +1,15 @@
+@GUPL_VERSION 0.0.1
+
+@ENTITY sendrecv
+
+@RECV 0 input 128
+  data        ,<12288
+@END
+
+@SEND 0 output 128
+  data        ,<12288
+@END
+
+@STAGE sendrecv
+  @SEND output
+@END

data/example/sendrecv_tb.vhd

@@ -0,0 +1,114 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity sendrecv_tb is
+end entity sendrecv_tb;
+
+architecture BEHAV of sendrecv_tb is
+  
+  component sendrecv
+    port(
+      -- input
+      UPL_input_data : in std_logic_vector(128-1 downto 0);
+      UPL_input_en : in std_logic;
+      UPL_input_req : in std_logic;
+      UPL_input_ack : out std_logic;
+      
+      -- output
+      UPL_output_data : out std_logic_vector(128-1 downto 0);
+      UPL_output_en : out std_logic;
+      UPL_output_req : out std_logic;
+      UPL_output_ack : in std_logic;
+      
+      -- system clock and reset
+      clk : in std_logic;
+      reset : in std_logic
+      );
+  end component sendrecv;
+
+  signal UPL_input_data          : std_logic_vector(128-1 downto 0) := (others => '0');
+  signal UPL_input_en            : std_logic := '0';
+  signal UPL_input_req           : std_logic := '0';
+  signal UPL_input_ack           : std_logic := '0';
+  signal UPL_output_data         : std_logic_vector(128-1 downto 0) := (others => '0');
+  signal UPL_output_en           : std_logic := '0';
+  signal UPL_output_req          : std_logic := '0';
+  signal UPL_output_ack          : std_logic := '0';
+  signal clk                     : std_logic := '0';
+  signal reset                   : std_logic := '0';
+
+  signal counter : unsigned(31 downto 0) := (others => '0');
+  
+begin
+
+  process
+  begin
+    clk <= not clk;
+    wait for 5ns;
+  end process;
+
+  process(clk)
+  begin
+    if rising_edge(clk) then
+      counter <= counter + 1;
+    
+      case to_integer(counter) is
+        when 1 =>
+          reset <= '1';
+        when 10 =>
+          reset <= '0';
+          UPL_output_ack <= '1';
+
+        when 100 =>
+          UPL_input_en <= '1';
+          UPL_input_data <= X"0a000001" & X"0a000003" & X"40004001" & X"00000008";
+        when 101 =>
+          UPL_input_en <= '1';
+          UPL_input_data <= X"34000000" & X"00000000" & X"00000000" & X"00000000";
+        when 102 =>
+          UPL_input_en <= '0';
+
+        when 200 =>
+          UPL_input_en <= '1';
+          UPL_input_data <= X"0a000001" & X"0a000003" & X"40004001" & std_logic_vector(to_unsigned(64, 32));
+        when 201 =>
+          UPL_input_en <= '1';
+          UPL_input_data <= X"32000000" & X"00000000" & X"0a020001" & X"00004000";
+        when 202 =>
+          UPL_input_en <= '1';
+          UPL_input_data <= X"0a020002" & X"00004001" & X"0a020003" & X"00004002";
+        when 203 =>
+          UPL_input_en <= '1';
+          UPL_input_data <= X"0a020004" & X"00004003" & X"0a020005" & X"00004004";
+        when 204 =>
+          UPL_input_en <= '1';
+          UPL_input_data <= X"0a020006" & X"00004005" & X"0a020007" & X"00004006";
+        when 205 =>
+          UPL_input_en <= '0';
+
+        when others => null;
+      end case;
+    end if;
+  end process;
+      
+  DUT : sendrecv
+    port map(
+      -- input
+      UPL_input_data => UPL_input_data,
+      UPL_input_en   => UPL_input_en,
+      UPL_input_req  => UPL_input_req,
+      UPL_input_ack  => UPL_input_ack,
+
+      -- output
+      UPL_output_data => UPL_output_data,
+      UPL_output_en   => UPL_output_en,
+      UPL_output_req  => UPL_output_req,
+      UPL_output_ack  => UPL_output_ack,
+
+      -- system clock and reset
+      clk   => clk,
+      reset => reset
+      );
+  
+end BEHAV;

data/example/udpled.gupl

@@ -0,0 +1,30 @@
+@GUPL_VERSION 0.0.1
+
+@ENTITY udpled
+
+@RECV 0 input 32
+  myIpAddr    , 32
+  dstIpAddr   , 32
+  myPort      , 16
+  dstPort     , 16
+  payloadBytes, 32
+  led_value   , 32
+@END
+
+@SEND 0 output 32
+  myIpAddr    , 32
+  dstIpAddr   , 32
+  myPort      , 16
+  dstPort     , 16
+  payloadBytes, 32
+  led_value   , 32
+@END
+
+@PORT
+  led, 8, out
+@END
+
+@STAGE udpled
+  led <= led_value(7 downto 0);
+  @SEND output
+@END

data/exe/gupl

@@ -0,0 +1,22 @@
+#!/usr/bin/env ruby
+
+require 'gupl'
+
+# main
+ARGV.each{|argv|
+  entity = nil
+  version = nil
+  open(argv){|f|
+    str = f.read()
+    version, entity = Gupl.main(str)
+  }
+  exit(0) if entity == nil
+  exit(0) if version == nil
+
+  dirname = File.dirname(argv)
+  open("#{dirname}/#{entity.name}.vhd", "w"){|dst|
+    buf = StringIO.new("", "w")
+    entity.generate(buf)
+    dst.puts(buf.string())
+  }
+}

data/gupl.gemspec

@@ -0,0 +1,38 @@
+# frozen_string_literal: true
+
+require_relative "lib/gupl/version"
+
+Gem::Specification.new do |spec|
+  spec.name = "gupl"
+  spec.version = Gupl::VERSION
+  spec.authors = ["Takefumi MIYOSHI"]
+  spec.email = ["miyo@wasamon.net"]
+
+  spec.summary = "gupl makes UPL module."
+  spec.description = "gupl makes UPL modules, which is a VHDL generator."
+  spec.homepage = "https://github.com/e-trees/gupl"
+  spec.required_ruby_version = ">= 2.6.0"
+
+  spec.metadata["allowed_push_host"] = "https://rubygems.org"
+
+  spec.metadata["homepage_uri"] = spec.homepage
+  spec.metadata["source_code_uri"] = "https://github.com/e-trees/gupl"
+  spec.metadata["changelog_uri"] = "https://github.com/e-trees/gupl/CHANGELOG.md"
+
+  # Specify which files should be added to the gem when it is released.
+  # The `git ls-files -z` loads the files in the RubyGem that have been added into git.
+  spec.files = Dir.chdir(__dir__) do
+    `git ls-files -z`.split("\x0").reject do |f|
+      (f == __FILE__) || f.match(%r{\A(?:(?:bin|test|spec|features)/|\.(?:git|travis|circleci)|appveyor)})
+    end
+  end
+  spec.bindir = "exe"
+  spec.executables = spec.files.grep(%r{\Aexe/}) { |f| File.basename(f) }
+  spec.require_paths = ["lib"]
+
+  # Uncomment to register a new dependency of your gem
+  # spec.add_dependency "example-gem", "~> 1.0"
+
+  # For more information and examples about making a new gem, check out our
+  # guide at: https://bundler.io/guides/creating_gem.html
+end

data/lib/gupl/version.rb

@@ -0,0 +1,5 @@
+# frozen_string_literal: true
+
+module Gupl
+  VERSION = "0.0.1"
+end