gupl 0.0.1
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +7 -0
- data/CHANGELOG.md +2 -0
- data/CODE_OF_CONDUCT.md +84 -0
- data/Gemfile +10 -0
- data/LICENSE +201 -0
- data/README.md +39 -0
- data/Rakefile +12 -0
- data/example/command_parser.gupl +177 -0
- data/example/command_parser_tb.vhd +172 -0
- data/example/sendrecv.gupl +15 -0
- data/example/sendrecv_tb.vhd +114 -0
- data/example/udpled.gupl +30 -0
- data/exe/gupl +22 -0
- data/gupl.gemspec +38 -0
- data/lib/gupl/version.rb +5 -0
- data/lib/gupl.rb +794 -0
- data/sig/gupl.rbs +4 -0
- data/vhdl_lib/simple_dualportram.vhd +57 -0
- metadata +64 -0
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity command_parser_tb is
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end entity command_parser_tb;
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architecture BEHAV of command_parser_tb is
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component command_parser
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port(
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-- input
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UPL_input_data : in std_logic_vector(128-1 downto 0);
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UPL_input_en : in std_logic;
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UPL_input_req : in std_logic;
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UPL_input_ack : out std_logic;
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-- forward_input
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UPL_forward_input_data : in std_logic_vector(128-1 downto 0);
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UPL_forward_input_en : in std_logic;
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UPL_forward_input_req : in std_logic;
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UPL_forward_input_ack : out std_logic;
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-- output
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UPL_output_data : out std_logic_vector(128-1 downto 0);
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UPL_output_en : out std_logic;
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UPL_output_req : out std_logic;
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UPL_output_ack : in std_logic;
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-- forward_output
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UPL_forward_output_data : out std_logic_vector(128-1 downto 0);
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UPL_forward_output_en : out std_logic;
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UPL_forward_output_req : out std_logic;
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UPL_forward_output_ack : in std_logic;
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-- user-defiend ports
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synch_sender_kick : out std_logic;
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synch_sender_busy : in std_logic;
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synch_target_addr : out std_logic_vector(32-1 downto 0);
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global_clock : in std_logic_vector(64-1 downto 0);
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global_clock_clear : out std_logic;
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-- system clock and reset
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clk : in std_logic;
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reset : in std_logic
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);
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end component command_parser;
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signal UPL_input_data : std_logic_vector(128-1 downto 0) := (others => '0');
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signal UPL_input_en : std_logic := '0';
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signal UPL_input_req : std_logic := '0';
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signal UPL_input_ack : std_logic := '0';
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signal UPL_forward_input_data : std_logic_vector(128-1 downto 0) := (others => '0');
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signal UPL_forward_input_en : std_logic := '0';
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signal UPL_forward_input_req : std_logic := '0';
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signal UPL_forward_input_ack : std_logic := '0';
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signal UPL_output_data : std_logic_vector(128-1 downto 0) := (others => '0');
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signal UPL_output_en : std_logic := '0';
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signal UPL_output_req : std_logic := '0';
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signal UPL_output_ack : std_logic := '0';
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signal UPL_forward_output_data : std_logic_vector(128-1 downto 0) := (others => '0');
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signal UPL_forward_output_en : std_logic := '0';
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signal UPL_forward_output_req : std_logic := '0';
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signal UPL_forward_output_ack : std_logic := '0';
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signal synch_sender_kick : std_logic;
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signal synch_sender_busy : std_logic := '0';
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signal synch_target_addr : std_logic_vector(32-1 downto 0) := (others => '0');
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signal global_clock : std_logic_vector(64-1 downto 0) := (others => '0');
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signal global_clock_clear : std_logic;
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signal clk : std_logic := '0';
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signal reset : std_logic := '0';
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signal counter : unsigned(31 downto 0) := (others => '0');
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begin
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process
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begin
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clk <= not clk;
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wait for 5ns;
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end process;
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process(clk)
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begin
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if rising_edge(clk) then
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counter <= counter + 1;
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if global_clock_clear = '1' then
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global_clock <= (others => '0');
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else
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global_clock <= std_logic_vector(unsigned(global_clock) + 1);
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end if;
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case to_integer(counter) is
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when 1 =>
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reset <= '1';
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when 10 =>
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reset <= '0';
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UPL_output_ack <= '1';
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UPL_forward_output_ack <= '1';
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when 100 =>
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UPL_input_en <= '1';
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UPL_input_data <= X"0a000001" & X"0a000003" & X"40004001" & X"00000008";
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when 101 =>
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UPL_input_en <= '1';
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UPL_input_data <= X"34000000" & X"00000000" & X"00000000" & X"00000000";
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when 102 =>
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UPL_input_en <= '0';
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when 200 =>
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UPL_input_en <= '1';
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UPL_input_data <= X"0a000001" & X"0a000003" & X"40004001" & std_logic_vector(to_unsigned(64, 32));
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when 201 =>
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UPL_input_en <= '1';
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UPL_input_data <= X"32000000" & X"00000000" & X"0a020001" & X"00004000";
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when 202 =>
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UPL_input_en <= '1';
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UPL_input_data <= X"0a020002" & X"00004001" & X"0a020003" & X"00004002";
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when 203 =>
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UPL_input_en <= '1';
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UPL_input_data <= X"0a020004" & X"00004003" & X"0a020005" & X"00004004";
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when 204 =>
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UPL_input_en <= '1';
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UPL_input_data <= X"0a020006" & X"00004005" & X"0a020007" & X"00004006";
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when 205 =>
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UPL_input_en <= '0';
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when others => null;
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end case;
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end if;
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end process;
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DUT : command_parser
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port map(
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-- input
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UPL_input_data => UPL_input_data,
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UPL_input_en => UPL_input_en,
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UPL_input_req => UPL_input_req,
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UPL_input_ack => UPL_input_ack,
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-- forward_input
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UPL_forward_input_data => UPL_forward_input_data,
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UPL_forward_input_en => UPL_forward_input_en,
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UPL_forward_input_req => UPL_forward_input_req,
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UPL_forward_input_ack => UPL_forward_input_ack,
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-- output
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UPL_output_data => UPL_output_data,
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UPL_output_en => UPL_output_en,
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UPL_output_req => UPL_output_req,
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UPL_output_ack => UPL_output_ack,
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-- forward_output
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UPL_forward_output_data => UPL_forward_output_data,
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UPL_forward_output_en => UPL_forward_output_en,
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UPL_forward_output_req => UPL_forward_output_req,
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UPL_forward_output_ack => UPL_forward_output_ack,
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-- user-defiend ports
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synch_sender_kick => synch_sender_kick,
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synch_sender_busy => synch_sender_busy,
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synch_target_addr => synch_target_addr,
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global_clock => global_clock,
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global_clock_clear => global_clock_clear,
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-- system clock and reset
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clk => clk,
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reset => reset
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);
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end BEHAV;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity sendrecv_tb is
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end entity sendrecv_tb;
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architecture BEHAV of sendrecv_tb is
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component sendrecv
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port(
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-- input
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UPL_input_data : in std_logic_vector(128-1 downto 0);
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UPL_input_en : in std_logic;
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UPL_input_req : in std_logic;
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UPL_input_ack : out std_logic;
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-- output
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UPL_output_data : out std_logic_vector(128-1 downto 0);
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UPL_output_en : out std_logic;
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UPL_output_req : out std_logic;
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UPL_output_ack : in std_logic;
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-- system clock and reset
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clk : in std_logic;
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reset : in std_logic
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);
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end component sendrecv;
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signal UPL_input_data : std_logic_vector(128-1 downto 0) := (others => '0');
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signal UPL_input_en : std_logic := '0';
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signal UPL_input_req : std_logic := '0';
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signal UPL_input_ack : std_logic := '0';
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signal UPL_output_data : std_logic_vector(128-1 downto 0) := (others => '0');
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signal UPL_output_en : std_logic := '0';
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signal UPL_output_req : std_logic := '0';
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signal UPL_output_ack : std_logic := '0';
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signal clk : std_logic := '0';
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signal reset : std_logic := '0';
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signal counter : unsigned(31 downto 0) := (others => '0');
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begin
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process
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begin
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clk <= not clk;
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wait for 5ns;
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end process;
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process(clk)
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begin
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if rising_edge(clk) then
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counter <= counter + 1;
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case to_integer(counter) is
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when 1 =>
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reset <= '1';
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when 10 =>
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reset <= '0';
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UPL_output_ack <= '1';
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when 100 =>
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UPL_input_en <= '1';
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UPL_input_data <= X"0a000001" & X"0a000003" & X"40004001" & X"00000008";
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when 101 =>
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UPL_input_en <= '1';
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UPL_input_data <= X"34000000" & X"00000000" & X"00000000" & X"00000000";
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when 102 =>
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UPL_input_en <= '0';
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when 200 =>
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UPL_input_en <= '1';
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UPL_input_data <= X"0a000001" & X"0a000003" & X"40004001" & std_logic_vector(to_unsigned(64, 32));
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when 201 =>
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UPL_input_en <= '1';
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UPL_input_data <= X"32000000" & X"00000000" & X"0a020001" & X"00004000";
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when 202 =>
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UPL_input_en <= '1';
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UPL_input_data <= X"0a020002" & X"00004001" & X"0a020003" & X"00004002";
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when 203 =>
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UPL_input_en <= '1';
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UPL_input_data <= X"0a020004" & X"00004003" & X"0a020005" & X"00004004";
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when 204 =>
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UPL_input_en <= '1';
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UPL_input_data <= X"0a020006" & X"00004005" & X"0a020007" & X"00004006";
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when 205 =>
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UPL_input_en <= '0';
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when others => null;
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end case;
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end if;
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end process;
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DUT : sendrecv
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port map(
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-- input
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UPL_input_data => UPL_input_data,
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UPL_input_en => UPL_input_en,
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UPL_input_req => UPL_input_req,
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UPL_input_ack => UPL_input_ack,
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-- output
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UPL_output_data => UPL_output_data,
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UPL_output_en => UPL_output_en,
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UPL_output_req => UPL_output_req,
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UPL_output_ack => UPL_output_ack,
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-- system clock and reset
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clk => clk,
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reset => reset
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);
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end BEHAV;
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data/example/udpled.gupl
ADDED
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@GUPL_VERSION 0.0.1
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@ENTITY udpled
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@RECV 0 input 32
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myIpAddr , 32
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dstIpAddr , 32
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myPort , 16
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dstPort , 16
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payloadBytes, 32
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led_value , 32
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@END
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@SEND 0 output 32
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myIpAddr , 32
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dstIpAddr , 32
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myPort , 16
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dstPort , 16
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payloadBytes, 32
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led_value , 32
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@END
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@PORT
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led, 8, out
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@END
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@STAGE udpled
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led <= led_value(7 downto 0);
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@SEND output
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@END
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data/exe/gupl
ADDED
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#!/usr/bin/env ruby
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require 'gupl'
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# main
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ARGV.each{|argv|
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entity = nil
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version = nil
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open(argv){|f|
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str = f.read()
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version, entity = Gupl.main(str)
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}
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exit(0) if entity == nil
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exit(0) if version == nil
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dirname = File.dirname(argv)
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open("#{dirname}/#{entity.name}.vhd", "w"){|dst|
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buf = StringIO.new("", "w")
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entity.generate(buf)
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dst.puts(buf.string())
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}
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}
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data/gupl.gemspec
ADDED
@@ -0,0 +1,38 @@
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# frozen_string_literal: true
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require_relative "lib/gupl/version"
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Gem::Specification.new do |spec|
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spec.name = "gupl"
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spec.version = Gupl::VERSION
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|
+
spec.authors = ["Takefumi MIYOSHI"]
|
9
|
+
spec.email = ["miyo@wasamon.net"]
|
10
|
+
|
11
|
+
spec.summary = "gupl makes UPL module."
|
12
|
+
spec.description = "gupl makes UPL modules, which is a VHDL generator."
|
13
|
+
spec.homepage = "https://github.com/e-trees/gupl"
|
14
|
+
spec.required_ruby_version = ">= 2.6.0"
|
15
|
+
|
16
|
+
spec.metadata["allowed_push_host"] = "https://rubygems.org"
|
17
|
+
|
18
|
+
spec.metadata["homepage_uri"] = spec.homepage
|
19
|
+
spec.metadata["source_code_uri"] = "https://github.com/e-trees/gupl"
|
20
|
+
spec.metadata["changelog_uri"] = "https://github.com/e-trees/gupl/CHANGELOG.md"
|
21
|
+
|
22
|
+
# Specify which files should be added to the gem when it is released.
|
23
|
+
# The `git ls-files -z` loads the files in the RubyGem that have been added into git.
|
24
|
+
spec.files = Dir.chdir(__dir__) do
|
25
|
+
`git ls-files -z`.split("\x0").reject do |f|
|
26
|
+
(f == __FILE__) || f.match(%r{\A(?:(?:bin|test|spec|features)/|\.(?:git|travis|circleci)|appveyor)})
|
27
|
+
end
|
28
|
+
end
|
29
|
+
spec.bindir = "exe"
|
30
|
+
spec.executables = spec.files.grep(%r{\Aexe/}) { |f| File.basename(f) }
|
31
|
+
spec.require_paths = ["lib"]
|
32
|
+
|
33
|
+
# Uncomment to register a new dependency of your gem
|
34
|
+
# spec.add_dependency "example-gem", "~> 1.0"
|
35
|
+
|
36
|
+
# For more information and examples about making a new gem, check out our
|
37
|
+
# guide at: https://bundler.io/guides/creating_gem.html
|
38
|
+
end
|