faiss 0.6.2 → 0.6.4

data/vendor/faiss/faiss/svs/IndexSVSVamanaLeanVec.h

@@ -36,7 +36,8 @@ struct IndexSVSVamanaLeanVec : IndexSVSVamana {
             MetricType metric = METRIC_L2,
             size_t leanvec_dims = 0,
             SVSStorageKind storage = SVSStorageKind::SVS_LeanVec4x4,
-            bool is_static = false);
+            bool is_static = false,
+            bool store_vectors = true);
 
     ~IndexSVSVamanaLeanVec() override;
 

data/vendor/faiss/faiss/utils/approx_topk_hamming/approx_topk_hamming.h

@@ -118,7 +118,7 @@ struct HeapWithBucketsForHamming32<
                         }
                     }
 
-                    if (valid_counter == 8) {
+                    if (valid_counter == 0) {
                         continue; // Skip if all vectors are filtered out
                     }
 

data/vendor/faiss/faiss/utils/distances.cpp

@@ -291,6 +291,11 @@ void exhaustive_inner_product_seq(
         BlockResultHandler& res) {
     using SingleResultHandler =
             typename BlockResultHandler::SingleResultHandler;
+
+    if (nx == 0) {
+        return;
+    }
+
     [[maybe_unused]] int nt = std::min(int(nx), omp_get_max_threads());
 
 #pragma omp parallel num_threads(nt)
@@ -327,6 +332,11 @@ void exhaustive_L2sqr_seq(
         BlockResultHandler& res) {
     using SingleResultHandler =
             typename BlockResultHandler::SingleResultHandler;
+
+    if (nx == 0) {
+        return;
+    }
+
     [[maybe_unused]] int nt = std::min(int(nx), omp_get_max_threads());
 
 #pragma omp parallel num_threads(nt)
@@ -531,15 +541,19 @@ void exhaustive_L2sqr_blas<Top1BlockResultHandler<CMax<float, int64_t>>>(
         return;
     }
 
-    with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_A2>([&]<SIMDLevel SL>() {
-        if constexpr (SL == SIMDLevel::AVX2 || SL == SIMDLevel::ARM_SVE) {
-            exhaustive_L2sqr_blas_cmax<SL>(x, y, d, nx, ny, res, y_norms);
-        } else {
-            exhaustive_L2sqr_blas_default_impl<
-                    Top1BlockResultHandler<CMax<float, int64_t>>>(
-                    x, y, d, nx, ny, res, y_norms);
-        }
-    });
+    with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_BASE_WITH_SVE>(
+            [&]<SIMDLevel SL>() {
+                if constexpr (
+                        SL == SIMDLevel::AVX2 || SL == SIMDLevel::AVX512 ||
+                        SL == SIMDLevel::ARM_SVE) {
+                    exhaustive_L2sqr_blas_cmax<SL>(
+                            x, y, d, nx, ny, res, y_norms);
+                } else {
+                    exhaustive_L2sqr_blas_default_impl<
+                            Top1BlockResultHandler<CMax<float, int64_t>>>(
+                            x, y, d, nx, ny, res, y_norms);
+                }
+            });
 }
 
 struct Run_search_inner_product {
@@ -551,7 +565,11 @@ struct Run_search_inner_product {
            size_t d,
            size_t nx,
            size_t ny) {
-        if (res.sel ||
+        // ny == 0 goes to the sequential path: it guards only on nx, so its
+        // per-query begin()/end() still runs and each handler writes its own
+        // neutral distance and -1 label. The BLAS path instead returns early
+        // on ny == 0, before the handler is initialized.
+        if (res.sel || ny == 0 ||
             nx * d < static_cast<size_t>(distance_compute_blas_threshold)) {
             exhaustive_inner_product_seq(x, y, d, nx, ny, res);
         } else {
@@ -570,7 +588,8 @@ struct Run_search_L2sqr {
            size_t nx,
            size_t ny,
            const float* y_norm2) {
-        if (res.sel ||
+        // See the note on ny == 0 in Run_search_inner_product.
+        if (res.sel || ny == 0 ||
             nx * d < static_cast<size_t>(distance_compute_blas_threshold)) {
             exhaustive_L2sqr_seq(x, y, d, nx, ny, res);
         } else {

data/vendor/faiss/faiss/utils/distances_dispatch.h

@@ -29,22 +29,22 @@
 namespace faiss {
 
 inline float fvec_L1_dispatch(const float* x, const float* y, size_t d) {
-    return with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_A1>(
+    return with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_BASE_WITH_SVE>(
             [&]<SIMDLevel SL>() { return fvec_L1<SL>(x, y, d); });
 }
 
 inline float fvec_Linf_dispatch(const float* x, const float* y, size_t d) {
-    return with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_A1>(
+    return with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_BASE_WITH_SVE>(
             [&]<SIMDLevel SL>() { return fvec_Linf<SL>(x, y, d); });
 }
 
 inline float fvec_norm_L2sqr_dispatch(const float* x, size_t d) {
-    return with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_A1>(
+    return with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_BASE_WITH_SVE>(
             [&]<SIMDLevel SL>() { return fvec_norm_L2sqr<SL>(x, d); });
 }
 
 inline float fvec_L2sqr_dispatch(const float* x, const float* y, size_t d) {
-    return with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_A1>(
+    return with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_BASE_WITH_SVE>(
             [&]<SIMDLevel SL>() { return fvec_L2sqr<SL>(x, y, d); });
 }
 
@@ -52,7 +52,7 @@ inline float fvec_inner_product_dispatch(
         const float* x,
         const float* y,
         size_t d) {
-    return with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_A1>(
+    return with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_BASE_WITH_SVE>(
             [&]<SIMDLevel SL>() { return fvec_inner_product<SL>(x, y, d); });
 }
 
@@ -67,10 +67,11 @@ inline void fvec_inner_product_batch_4_dispatch(
         float& dis1,
         float& dis2,
         float& dis3) {
-    with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_A1>([&]<SIMDLevel SL>() {
-        fvec_inner_product_batch_4<SL>(
-                x, y0, y1, y2, y3, d, dis0, dis1, dis2, dis3);
-    });
+    with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_BASE_WITH_SVE>(
+            [&]<SIMDLevel SL>() {
+                fvec_inner_product_batch_4<SL>(
+                        x, y0, y1, y2, y3, d, dis0, dis1, dis2, dis3);
+            });
 }
 
 inline void fvec_L2sqr_batch_4_dispatch(
@@ -84,9 +85,11 @@ inline void fvec_L2sqr_batch_4_dispatch(
         float& dis1,
         float& dis2,
         float& dis3) {
-    with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_A1>([&]<SIMDLevel SL>() {
-        fvec_L2sqr_batch_4<SL>(x, y0, y1, y2, y3, d, dis0, dis1, dis2, dis3);
-    });
+    with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_BASE_WITH_SVE>(
+            [&]<SIMDLevel SL>() {
+                fvec_L2sqr_batch_4<SL>(
+                        x, y0, y1, y2, y3, d, dis0, dis1, dis2, dis3);
+            });
 }
 
 inline void fvec_L2sqr_ny_transposed_dispatch(
@@ -97,9 +100,11 @@ inline void fvec_L2sqr_ny_transposed_dispatch(
         size_t d,
         size_t d_offset,
         size_t ny) {
-    with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_A1>([&]<SIMDLevel SL>() {
-        fvec_L2sqr_ny_transposed<SL>(dis, x, y, y_sqlen, d, d_offset, ny);
-    });
+    with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_BASE_WITH_SVE>(
+            [&]<SIMDLevel SL>() {
+                fvec_L2sqr_ny_transposed<SL>(
+                        dis, x, y, y_sqlen, d, d_offset, ny);
+            });
 }
 
 inline void fvec_inner_products_ny_dispatch(
@@ -108,9 +113,10 @@ inline void fvec_inner_products_ny_dispatch(
         const float* y,
         size_t d,
         size_t ny) {
-    with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_A1>([&]<SIMDLevel SL>() {
-        fvec_inner_products_ny<SL>(ip, x, y, d, ny);
-    });
+    with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_BASE_WITH_SVE>(
+            [&]<SIMDLevel SL>() {
+                fvec_inner_products_ny<SL>(ip, x, y, d, ny);
+            });
 }
 
 inline void fvec_L2sqr_ny_dispatch(
@@ -119,7 +125,7 @@ inline void fvec_L2sqr_ny_dispatch(
         const float* y,
         size_t d,
         size_t ny) {
-    with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_A1>(
+    with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_BASE_WITH_SVE>(
             [&]<SIMDLevel SL>() { fvec_L2sqr_ny<SL>(dis, x, y, d, ny); });
 }
 
@@ -129,7 +135,7 @@ inline size_t fvec_L2sqr_ny_nearest_dispatch(
         const float* y,
         size_t d,
         size_t ny) {
-    return with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_A1>(
+    return with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_BASE_WITH_SVE>(
             [&]<SIMDLevel SL>() {
                 return fvec_L2sqr_ny_nearest<SL>(
                         distances_tmp_buffer, x, y, d, ny);
@@ -144,7 +150,7 @@ inline size_t fvec_L2sqr_ny_nearest_y_transposed_dispatch(
         size_t d,
         size_t d_offset,
         size_t ny) {
-    return with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_A1>(
+    return with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_BASE_WITH_SVE>(
             [&]<SIMDLevel SL>() {
                 return fvec_L2sqr_ny_nearest_y_transposed<SL>(
                         distances_tmp_buffer, x, y, y_sqlen, d, d_offset, ny);
@@ -157,7 +163,7 @@ inline void fvec_madd_dispatch(
         float bf,
         const float* b,
         float* c) {
-    with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_A1>(
+    with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_BASE_WITH_SVE>(
             [&]<SIMDLevel SL>() { fvec_madd<SL>(n, a, bf, b, c); });
 }
 
@@ -167,7 +173,7 @@ inline int fvec_madd_and_argmin_dispatch(
         float bf,
         const float* b,
         float* c) {
-    return with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_A1>(
+    return with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_BASE_WITH_SVE>(
             [&]<SIMDLevel SL>() {
                 return fvec_madd_and_argmin<SL>(n, a, bf, b, c);
             });
@@ -241,7 +247,7 @@ auto with_VectorDistance(
         if constexpr (!has_simd) {
             return call.template operator()<SIMDLevel::NONE>();
         } else {
-            return with_simd_level(call);
+            return with_simd_level_with_sve(call);
         }
     };
     return with_metric_type(metric, dispatch_metric);

data/vendor/faiss/faiss/utils/distances_fused/distances_fused.cpp

@@ -51,7 +51,7 @@ bool exhaustive_L2sqr_fused_cmax(
         return true;
     }
 
-    return with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_A0>(
+    return with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_BASE>(
             [&]<SIMDLevel SL>() {
                 return exhaustive_L2sqr_fused_cmax<SL>(
                         x, y, d, nx, ny, res, y_norms);

data/vendor/faiss/faiss/utils/distances_simd.cpp

@@ -10,18 +10,19 @@
 #include <faiss/utils/distances.h>
 
 #include <cmath>
-#include <cstdio>
 #include <cstring>
 
-#include <faiss/impl/FaissAssert.h>
 #include <faiss/impl/simdlib/simdlib_dispatch.h>
 
 #define THE_SIMD_LEVEL SIMDLevel::NONE
 // NOLINTNEXTLINE(facebook-hte-InlineHeader)
 #include <faiss/utils/simd_impl/distances_autovec-inl.h>
 
+// This TU is the SIMDLevel::NONE build of the specializations that
+// distances_simdlib256.h emits, so the include is required despite no symbol
+// being named directly here.
 // NOLINTNEXTLINE(facebook-hte-InlineHeader)
-#include <faiss/utils/simd_impl/distances_simdlib256.h>
+#include <faiss/utils/simd_impl/distances_simdlib256.h> // IWYU pragma: keep
 
 namespace faiss {
 

data/vendor/faiss/faiss/utils/extra_distances.cpp

@@ -29,11 +29,9 @@ namespace {
 template <class VD>
 struct ExtraDistanceComputer : FlatCodesDistanceComputer {
     VD vd;
-    idx_t nb;
-    const float* q;
-    const float* b;
 
     float symmetric_dis(idx_t i, idx_t j) final {
+        const float* b = (const float*)codes;
         return vd(b + j * vd.d, b + i * vd.d);
     }
 
@@ -41,16 +39,9 @@ struct ExtraDistanceComputer : FlatCodesDistanceComputer {
         return vd(q, (float*)code);
     }
 
-    ExtraDistanceComputer(
-            const VD& vd_in,
-            const float* xb,
-            size_t nb_in,
-            const float* q_in = nullptr)
+    ExtraDistanceComputer(const VD& vd_in, const float* xb)
             : FlatCodesDistanceComputer((uint8_t*)xb, vd_in.d * sizeof(float)),
-              vd(vd_in),
-              nb(nb_in),
-              q(q_in),
-              b(xb) {}
+              vd(vd_in) {}
 
     void set_query(const float* x) override {
         q = x;
@@ -149,11 +140,10 @@ FlatCodesDistanceComputer* get_extra_distance_computer(
         size_t d,
         MetricType mt,
         float metric_arg,
-        size_t nb,
         const float* xb) {
     return with_VectorDistance(
             d, mt, metric_arg, [&](auto vd) -> FlatCodesDistanceComputer* {
-                return new ExtraDistanceComputer<decltype(vd)>(vd, xb, nb);
+                return new ExtraDistanceComputer<decltype(vd)>(vd, xb);
             });
 }
 

data/vendor/faiss/faiss/utils/extra_distances.h

@@ -49,12 +49,11 @@ void knn_extra_metrics(
         const IDSelector* sel = nullptr);
 
 /** get a DistanceComputer that refers to this type of distance and
- *  indexes a flat array of size nb */
+ *  indexes a flat array */
 FlatCodesDistanceComputer* get_extra_distance_computer(
         size_t d,
         MetricType mt,
         float metric_arg,
-        size_t nb,
         const float* xb);
 
 /// Dispatch to a lambda with MetricType as a compile-time constant.

data/vendor/faiss/faiss/utils/hamming.cpp

@@ -33,7 +33,7 @@
 // Scalar (NONE) fallback — only needs the generic specializations.
 #define THE_SIMD_LEVEL SIMDLevel::NONE
 // NOLINTNEXTLINE(facebook-hte-InlineHeader)
-#include <faiss/utils/hamming_distance/hamming_computer-generic.h>
+#include <faiss/utils/hamming_distance/hamming_computer-generic.h> // IWYU pragma: keep
 #include <faiss/utils/hamming_distance/hamming_impl.h>
 #undef THE_SIMD_LEVEL
 
@@ -146,8 +146,14 @@ void hammings(
         size_t nb,
         size_t ncodes,
         hamdis_t* __restrict dis) {
-    with_simd_level_a0_spr([&]<SIMDLevel SL>() {
-        hammings_fixSL<SL>(a, b, na, nb, ncodes, dis);
+    with_simd_level_with_vpopcnt([&]<SIMDLevel SL>() {
+        // Ragged sizes have their own kernel; keeping it out of
+        // hammings_fixSL() leaves the word-level paths untouched.
+        if (ncodes % 8 != 0) {
+            hammings_ragged_fixSL<SL>(a, b, na, nb, ncodes, dis);
+        } else {
+            hammings_fixSL<SL>(a, b, na, nb, ncodes, dis);
+        }
     });
 }
 
@@ -170,7 +176,7 @@ void hammings_knn_hc(
         int order,
         ApproxTopK_mode_t approx_topk_mode,
         const faiss::IDSelector* sel) {
-    with_simd_level_a0_spr([&]<SIMDLevel SL>() {
+    with_simd_level_with_vpopcnt([&]<SIMDLevel SL>() {
         hammings_knn_hc_fixSL<SL>(
                 ha, a, b, nb, ncodes, order, approx_topk_mode, sel);
     });
@@ -186,7 +192,7 @@ void hammings_knn_mc(
         int32_t* __restrict distances,
         int64_t* __restrict labels,
         const faiss::IDSelector* sel) {
-    with_simd_level_a0_spr([&]<SIMDLevel SL>() {
+    with_simd_level_with_vpopcnt([&]<SIMDLevel SL>() {
         hammings_knn_mc_fixSL<SL>(
                 a, b, na, nb, k, ncodes, distances, labels, sel);
     });
@@ -201,7 +207,7 @@ void hamming_range_search(
         size_t code_size,
         RangeSearchResult* result,
         const faiss::IDSelector* sel) {
-    with_simd_level_a0_spr([&]<SIMDLevel SL>() {
+    with_simd_level_with_vpopcnt([&]<SIMDLevel SL>() {
         hamming_range_search_fixSL<SL>(
                 a, b, na, nb, radius, code_size, result, sel);
     });
@@ -215,7 +221,7 @@ void hamming_count_thres(
         hamdis_t ht,
         size_t ncodes,
         size_t* nptr) {
-    with_simd_level_a0_spr([&]<SIMDLevel SL>() {
+    with_simd_level_with_vpopcnt([&]<SIMDLevel SL>() {
         hamming_count_thres_fixSL<SL>(bs1, bs2, n1, n2, ht, ncodes, nptr);
     });
 }
@@ -226,7 +232,7 @@ void crosshamming_count_thres(
         hamdis_t ht,
         size_t ncodes,
         size_t* nptr) {
-    with_simd_level_a0_spr([&]<SIMDLevel SL>() {
+    with_simd_level_with_vpopcnt([&]<SIMDLevel SL>() {
         crosshamming_count_thres_fixSL<SL>(dbs, n, ht, ncodes, nptr);
     });
 }
@@ -240,7 +246,7 @@ size_t match_hamming_thres(
         size_t ncodes,
         int64_t* idx,
         hamdis_t* dis) {
-    return with_simd_level_a0_spr([&]<SIMDLevel SL>() -> size_t {
+    return with_simd_level_with_vpopcnt([&]<SIMDLevel SL>() -> size_t {
         return match_hamming_thres_fixSL<SL>(
                 bs1, bs2, n1, n2, ht, ncodes, idx, dis);
     });
@@ -253,7 +259,7 @@ void generalized_hammings_knn_hc(
         size_t nb,
         size_t code_size,
         int ordered) {
-    with_simd_level_a0_spr([&]<SIMDLevel SL>() {
+    with_simd_level_with_vpopcnt([&]<SIMDLevel SL>() {
         generalized_hammings_knn_hc_fixSL<SL>(ha, a, b, nb, code_size, ordered);
     });
 }

data/vendor/faiss/faiss/utils/hamming.h

@@ -111,7 +111,7 @@ FAISS_API extern size_t hamming_batch_size;
  *
  * @param  a             size na * nbytespercode
  * @param  b             size nb * nbytespercode
- * @param  nbytespercode should be multiple of 8
+ * @param  nbytespercode any size; multiples of 8 take a faster kernel
  * @param  dis           output distances, size na * nb
  */
 void hammings(
@@ -327,6 +327,15 @@ void hamming_range_search_fixSL(
         RangeSearchResult* result,
         const IDSelector* sel);
 
+template <SIMDLevel SL>
+void hammings_ragged_fixSL(
+        const uint8_t* a,
+        const uint8_t* b,
+        size_t na,
+        size_t nb,
+        size_t ncodes,
+        hamdis_t* dis);
+
 template <SIMDLevel SL>
 void hammings_fixSL(
         const uint8_t* a,

data/vendor/faiss/faiss/utils/hamming_distance/common.h

@@ -210,12 +210,23 @@ inline void hammings_impl(
         size_t n2,
         hamdis_t* __restrict dis) {
     size_t i, j;
-    const size_t nwords = nbits / 64;
+    constexpr size_t nwords = nbits / 64;
     for (i = 0; i < n1; i++) {
         const uint64_t* __restrict bs1_ = bs1 + i * nwords;
         hamdis_t* __restrict dis_ = dis + i * n2;
-        for (j = 0; j < n2; j++) {
-            dis_[j] = hamming<nbits>(bs1_, bs2 + j * nwords);
+        if constexpr (nwords >= 4) {
+            // Wide codes are quicker one candidate at a time; otherwise the
+            // compiler batches candidates and must gather scattered bytes.
+#if defined(__clang__)
+#pragma clang loop vectorize(disable)
+#endif
+            for (j = 0; j < n2; j++) {
+                dis_[j] = hamming<nbits>(bs1_, bs2 + j * nwords);
+            }
+        } else {
+            for (j = 0; j < n2; j++) {
+                dis_[j] = hamming<nbits>(bs1_, bs2 + j * nwords);
+            }
         }
     }
 }

data/vendor/faiss/faiss/utils/hamming_distance/hamming_avx512_vpopcnt.cpp

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ * This source code is licensed under the MIT license found in the
+ * LICENSE file in the root directory of this source tree.
+ */
+
+#ifdef COMPILE_SIMD_AVX512_VPOPCNT
+
+#define THE_SIMD_LEVEL SIMDLevel::AVX512_VPOPCNT
+#include <faiss/utils/hamming_distance/hamming_computer-avx512_vpopcnt.h>
+#include <faiss/utils/hamming_distance/hamming_impl.h>
+
+// Must follow the computer specializations above.
+// clang-format off
+// NOLINTNEXTLINE(facebook-hte-InlineHeader)
+#include <faiss/impl/binary_hamming/IndexBinaryIVF_impl.h>
+// clang-format on
+
+// Fails the build if the batch path stops being selected for this computer.
+static_assert(faiss::has_hamming_batch<
+              faiss::HammingComputer20_tpl<faiss::SIMDLevel::AVX512_VPOPCNT>>);
+
+#endif // COMPILE_SIMD_AVX512_VPOPCNT

data/vendor/faiss/faiss/utils/hamming_distance/hamming_computer-avx512.h

@@ -12,7 +12,7 @@
 // Types without custom AVX512 code inherit from the NONE specializations
 // in hamming_computer-generic.h. HammingComputer64 and
 // HammingComputerDefault use scalar popcount here; the VPOPCNTDQ fast
-// path lives in hamming_computer-avx512_spr.h (AVX512_SPR level).
+// path lives in hamming_computer-avx512_vpopcnt.h (AVX512_VPOPCNT level).
 // GenHammingComputer classes leverage SSE/AVX2 intrinsics.
 
 #include <cassert>

data/vendor/faiss/faiss/utils/hamming_distance/{hamming_computer-avx512_spr.h → hamming_computer-avx512_vpopcnt.h}

@@ -5,17 +5,19 @@
  * LICENSE file in the root directory of this source tree.
  */
 
-#ifndef HAMMING_COMPUTER_AVX512_SPR_H
-#define HAMMING_COMPUTER_AVX512_SPR_H
+#ifndef HAMMING_COMPUTER_AVX512_VPOPCNT_H
+#define HAMMING_COMPUTER_AVX512_VPOPCNT_H
 
-// AVX512_SPR HammingComputer specializations using VPOPCNTDQ.
-// On Sapphire Rapids+, _mm512_popcnt_epi64 (and _mm256_popcnt_epi64 with VL)
-// are unconditionally available. This gives a faster path than the scalar
-// popcount fallback used in the base AVX512 specializations when compiled
-// without -mavx512vpopcntdq.
+// AVX512_VPOPCNT HammingComputer specializations. The 32/64/Default kernels
+// use VPOPCNTDQ; the batched 20-byte kernel uses AVX512_BITALG. This gives
+// a faster path than the scalar popcount fallback used in the base AVX512
+// specializations when compiled without -mavx512vpopcntdq.
 
 #include <cassert>
 #include <cstdint>
+#include <cstring>
+
+#include <faiss/utils/popcount.h>
 
 #include <faiss/impl/platform_macros.h>
 #include <faiss/utils/hamming_distance/hamming_computer-avx512.h>
@@ -25,31 +27,90 @@
 namespace faiss {
 
 /***************************************************************************
- * AVX512_SPR inheriting specializations for types without custom SPR code.
+ * AVX512_VPOPCNT inheriting specializations without custom VPOPCNT code.
  ***************************************************************************/
 
-#define FAISS_INHERIT_HAMMING_SPR(Class)                                   \
-    template <>                                                            \
-    struct Class##                                                         \
-            _tpl<SIMDLevel::AVX512_SPR> : Class##_tpl<SIMDLevel::AVX512> { \
-        using Class##_tpl<SIMDLevel::AVX512>::Class##_tpl;                 \
+#define FAISS_INHERIT_HAMMING_VPOPCNT(Class)                                   \
+    template <>                                                                \
+    struct Class##                                                             \
+            _tpl<SIMDLevel::AVX512_VPOPCNT> : Class##_tpl<SIMDLevel::AVX512> { \
+        using Class##_tpl<SIMDLevel::AVX512>::Class##_tpl;                     \
     }
 
-FAISS_INHERIT_HAMMING_SPR(HammingComputer16);
-FAISS_INHERIT_HAMMING_SPR(HammingComputer20);
-FAISS_INHERIT_HAMMING_SPR(GenHammingComputer8);
-FAISS_INHERIT_HAMMING_SPR(GenHammingComputer16);
-FAISS_INHERIT_HAMMING_SPR(GenHammingComputer32);
-FAISS_INHERIT_HAMMING_SPR(GenHammingComputerM8);
+FAISS_INHERIT_HAMMING_VPOPCNT(HammingComputer16);
+FAISS_INHERIT_HAMMING_VPOPCNT(GenHammingComputer8);
+FAISS_INHERIT_HAMMING_VPOPCNT(GenHammingComputer16);
+FAISS_INHERIT_HAMMING_VPOPCNT(GenHammingComputer32);
+FAISS_INHERIT_HAMMING_VPOPCNT(GenHammingComputerM8);
 
-#undef FAISS_INHERIT_HAMMING_SPR
+#undef FAISS_INHERIT_HAMMING_VPOPCNT
 
 /***************************************************************************
- * Custom AVX512_SPR specializations using VPOPCNTDQ.
+ * Custom AVX512_VPOPCNT specializations using VPOPCNTDQ.
  ***************************************************************************/
 
 template <>
-struct HammingComputer32_tpl<SIMDLevel::AVX512_SPR> {
+struct HammingComputer20_tpl<SIMDLevel::AVX512_VPOPCNT>
+        : HammingComputer20_tpl<SIMDLevel::AVX512> {
+    using HammingComputer20_tpl<SIMDLevel::AVX512>::HammingComputer20_tpl;
+
+    static constexpr size_t batch_size = 8;
+    static constexpr size_t kStride = get_code_size();
+    // 160 bytes is what the three loads in hamming_batch() cover, and the
+    // 16+4 or 4+16 split it applies per lane is written out for 20 bytes:
+    // the literal offsets and the two group indices are not derived from
+    // kStride, so another width needs the body reworked, not just retuned.
+    static_assert(batch_size * kStride == 160);
+    static_assert(kStride == 20, "hamming_batch() hardcodes the 16+4 split");
+    static constexpr __mmask64 kTailMask = 0xFFFFFFFFull;
+
+    /// Writes the query repeated batch_size times. The caller owns the buffer,
+    /// so a computer used only through hamming() carries no batch state.
+    static void build_batch_query(const uint8_t* a8, uint8_t* tile) {
+        for (size_t k = 0; k < batch_size; k++) {
+            memcpy(tile + k * kStride, a8, kStride);
+        }
+    }
+
+    static void hamming_batch(
+            const uint8_t* tile,
+            const uint8_t* codes,
+            int32_t* dis) {
+        const __m512i zero = _mm512_setzero_si512();
+        const __m512i p0 = _mm512_popcnt_epi8(_mm512_xor_si512(
+                _mm512_loadu_si512(codes), _mm512_loadu_si512(tile)));
+        const __m512i p1 = _mm512_popcnt_epi8(_mm512_xor_si512(
+                _mm512_loadu_si512(codes + 64), _mm512_loadu_si512(tile + 64)));
+        const __m512i p2 = _mm512_popcnt_epi8(_mm512_xor_si512(
+                _mm512_maskz_loadu_epi8(kTailMask, codes + 128),
+                _mm512_maskz_loadu_epi8(kTailMask, tile + 128)));
+
+        alignas(64) uint64_t grp[24];
+        _mm512_store_si512(grp, _mm512_sad_epu8(p0, zero));
+        _mm512_store_si512(grp + 8, _mm512_sad_epu8(p1, zero));
+        _mm512_store_si512(grp + 16, _mm512_sad_epu8(p2, zero));
+
+        for (size_t k = 0; k < batch_size; k++) {
+            const size_t s = k * kStride;
+            const size_t g = s / 8;
+            uint32_t xh, qh;
+            if (s % 8 == 0) {
+                memcpy(&xh, codes + s + 16, 4);
+                memcpy(&qh, tile + s + 16, 4);
+                dis[k] = static_cast<int32_t>(
+                        grp[g] + grp[g + 1] + popcount32(xh ^ qh));
+            } else {
+                memcpy(&xh, codes + s, 4);
+                memcpy(&qh, tile + s, 4);
+                dis[k] = static_cast<int32_t>(
+                        popcount32(xh ^ qh) + grp[g + 1] + grp[g + 2]);
+            }
+        }
+    }
+};
+
+template <>
+struct HammingComputer32_tpl<SIMDLevel::AVX512_VPOPCNT> {
     const uint8_t* a8;
 
     HammingComputer32_tpl() {}
@@ -81,7 +142,7 @@ struct HammingComputer32_tpl<SIMDLevel::AVX512_SPR> {
 };
 
 template <>
-struct HammingComputer64_tpl<SIMDLevel::AVX512_SPR> {
+struct HammingComputer64_tpl<SIMDLevel::AVX512_VPOPCNT> {
     const uint8_t* a8;
 
     HammingComputer64_tpl() {}
@@ -108,7 +169,7 @@ struct HammingComputer64_tpl<SIMDLevel::AVX512_SPR> {
 };
 
 template <>
-struct HammingComputerDefault_tpl<SIMDLevel::AVX512_SPR> {
+struct HammingComputerDefault_tpl<SIMDLevel::AVX512_VPOPCNT> {
     const uint8_t* a8;
     int quotient8;
     int remainder8;