contrast-agent 3.8.4

data/funchook/distorm/src/insts.h

@@ -0,0 +1,64 @@
+/*
+insts.h
+
+diStorm3 - Powerful disassembler for X86/AMD64
+http://ragestorm.net/distorm/
+distorm at gmail dot com
+Copyright (C) 2003-2016 Gil Dabah
+This library is licensed under the BSD license. See the file COPYING.
+*/
+
+
+#ifndef INSTS_H
+#define INSTS_H
+
+#include "instructions.h"
+
+
+/* Flags Table */
+extern _iflags FlagsTable[];
+
+/* Root Trie DB */
+extern _InstSharedInfo InstSharedInfoTable[];
+extern _InstInfo InstInfos[];
+extern _InstInfoEx InstInfosEx[];
+extern _InstNode InstructionsTree[];
+
+/* 3DNow! Trie DB */
+extern _InstNode Table_0F_0F;
+/* AVX related: */
+extern _InstNode Table_0F, Table_0F_38, Table_0F_3A;
+
+/*
+ * The inst_lookup will return on of these two instructions according to the specified decoding mode.
+ * ARPL or MOVSXD on 64 bits is one byte instruction at index 0x63.
+ */
+extern _InstInfo II_MOVSXD;
+
+/*
+ * The NOP instruction can be prefixed by REX in 64bits, therefore we have to decide in runtime whether it's an XCHG or NOP instruction.
+ * If 0x90 is prefixed by a usable REX it will become XCHG, otherwise it will become a NOP.
+ * Also note that if it's prefixed by 0xf3, it becomes a Pause.
+ */
+extern _InstInfo II_NOP;
+extern _InstInfo II_PAUSE;
+
+/*
+ * RDRAND and VMPTRLD share same 2.3 bytes opcode, and then alternates on the MOD bits,
+ * RDRAND is OT_FULL_REG while VMPTRLD is OT_MEM, and there's no such mixed type.
+ * So a hack into the inst_lookup was added for this decision, the DB isn't flexible enough. :(
+ */
+extern _InstInfo II_RDRAND;
+
+/*
+ * Used for letting the extract operand know the type of operands without knowing the
+ * instruction itself yet, because of the way those instructions work.
+ * See function instructions.c!inst_lookup_3dnow.
+ */
+extern _InstInfo II_3DNOW;
+
+/* Helper tables for pseudo compare mnemonics. */
+extern uint16_t CmpMnemonicOffsets[8]; /* SSE */
+extern uint16_t VCmpMnemonicOffsets[32]; /* AVX */
+
+#endif /* INSTS_H */

data/funchook/distorm/src/mnemonics.c

@@ -0,0 +1,284 @@
+/*
+mnemonics.c
+
+diStorm3 - Powerful disassembler for X86/AMD64
+http://ragestorm.net/distorm/
+distorm at gmail dot com
+Copyright (C) 2003-2016 Gil Dabah
+This library is licensed under the BSD license. See the file COPYING.
+*/
+
+
+#include "../include/mnemonics.h"
+
+#ifndef DISTORM_LIGHT
+
+const unsigned char _MNEMONICS[] =
+"\x09" "UNDEFINED\0" "\x03" "ADD\0" "\x04" "PUSH\0" "\x03" "POP\0" "\x02" "OR\0" \
+"\x03" "ADC\0" "\x03" "SBB\0" "\x03" "AND\0" "\x03" "DAA\0" "\x03" "SUB\0" \
+"\x03" "DAS\0" "\x03" "XOR\0" "\x03" "AAA\0" "\x03" "CMP\0" "\x03" "AAS\0" \
+"\x03" "INC\0" "\x03" "DEC\0" "\x05" "PUSHA\0" "\x04" "POPA\0" "\x05" "BOUND\0" \
+"\x04" "ARPL\0" "\x04" "IMUL\0" "\x03" "INS\0" "\x04" "OUTS\0" "\x02" "JO\0" \
+"\x03" "JNO\0" "\x02" "JB\0" "\x03" "JAE\0" "\x02" "JZ\0" "\x03" "JNZ\0" "\x03" "JBE\0" \
+"\x02" "JA\0" "\x02" "JS\0" "\x03" "JNS\0" "\x02" "JP\0" "\x03" "JNP\0" "\x02" "JL\0" \
+"\x03" "JGE\0" "\x03" "JLE\0" "\x02" "JG\0" "\x04" "TEST\0" "\x04" "XCHG\0" \
+"\x03" "MOV\0" "\x03" "LEA\0" "\x03" "CBW\0" "\x04" "CWDE\0" "\x04" "CDQE\0" \
+"\x03" "CWD\0" "\x03" "CDQ\0" "\x03" "CQO\0" "\x08" "CALL FAR\0" "\x05" "PUSHF\0" \
+"\x04" "POPF\0" "\x04" "SAHF\0" "\x04" "LAHF\0" "\x04" "MOVS\0" "\x04" "CMPS\0" \
+"\x04" "STOS\0" "\x04" "LODS\0" "\x04" "SCAS\0" "\x03" "RET\0" "\x03" "LES\0" \
+"\x03" "LDS\0" "\x05" "ENTER\0" "\x05" "LEAVE\0" "\x04" "RETF\0" "\x05" "INT 3\0" \
+"\x03" "INT\0" "\x04" "INTO\0" "\x04" "IRET\0" "\x03" "AAM\0" "\x03" "AAD\0" \
+"\x04" "SALC\0" "\x04" "XLAT\0" "\x06" "LOOPNZ\0" "\x05" "LOOPZ\0" "\x04" "LOOP\0" \
+"\x04" "JCXZ\0" "\x05" "JECXZ\0" "\x05" "JRCXZ\0" "\x02" "IN\0" "\x03" "OUT\0" \
+"\x04" "CALL\0" "\x03" "JMP\0" "\x07" "JMP FAR\0" "\x04" "INT1\0" "\x03" "HLT\0" \
+"\x03" "CMC\0" "\x03" "CLC\0" "\x03" "STC\0" "\x03" "CLI\0" "\x03" "STI\0" \
+"\x03" "CLD\0" "\x03" "STD\0" "\x03" "LAR\0" "\x03" "LSL\0" "\x07" "SYSCALL\0" \
+"\x04" "CLTS\0" "\x06" "SYSRET\0" "\x04" "INVD\0" "\x06" "WBINVD\0" "\x03" "UD2\0" \
+"\x05" "FEMMS\0" "\x03" "NOP\0" "\x05" "WRMSR\0" "\x05" "RDTSC\0" "\x05" "RDMSR\0" \
+"\x05" "RDPMC\0" "\x08" "SYSENTER\0" "\x07" "SYSEXIT\0" "\x06" "GETSEC\0" "\x05" "CMOVO\0" \
+"\x06" "CMOVNO\0" "\x05" "CMOVB\0" "\x06" "CMOVAE\0" "\x05" "CMOVZ\0" "\x06" "CMOVNZ\0" \
+"\x06" "CMOVBE\0" "\x05" "CMOVA\0" "\x05" "CMOVS\0" "\x06" "CMOVNS\0" "\x05" "CMOVP\0" \
+"\x06" "CMOVNP\0" "\x05" "CMOVL\0" "\x06" "CMOVGE\0" "\x06" "CMOVLE\0" "\x05" "CMOVG\0" \
+"\x04" "SETO\0" "\x05" "SETNO\0" "\x04" "SETB\0" "\x05" "SETAE\0" "\x04" "SETZ\0" \
+"\x05" "SETNZ\0" "\x05" "SETBE\0" "\x04" "SETA\0" "\x04" "SETS\0" "\x05" "SETNS\0" \
+"\x04" "SETP\0" "\x05" "SETNP\0" "\x04" "SETL\0" "\x05" "SETGE\0" "\x05" "SETLE\0" \
+"\x04" "SETG\0" "\x05" "CPUID\0" "\x02" "BT\0" "\x04" "SHLD\0" "\x03" "RSM\0" \
+"\x03" "BTS\0" "\x04" "SHRD\0" "\x07" "CMPXCHG\0" "\x03" "LSS\0" "\x03" "BTR\0" \
+"\x03" "LFS\0" "\x03" "LGS\0" "\x05" "MOVZX\0" "\x03" "BTC\0" "\x05" "MOVSX\0" \
+"\x04" "XADD\0" "\x06" "MOVNTI\0" "\x05" "BSWAP\0" "\x03" "ROL\0" "\x03" "ROR\0" \
+"\x03" "RCL\0" "\x03" "RCR\0" "\x03" "SHL\0" "\x03" "SHR\0" "\x03" "SAL\0" \
+"\x03" "SAR\0" "\x06" "XABORT\0" "\x06" "XBEGIN\0" "\x04" "FADD\0" "\x04" "FMUL\0" \
+"\x04" "FCOM\0" "\x05" "FCOMP\0" "\x04" "FSUB\0" "\x05" "FSUBR\0" "\x04" "FDIV\0" \
+"\x05" "FDIVR\0" "\x03" "FLD\0" "\x03" "FST\0" "\x04" "FSTP\0" "\x06" "FLDENV\0" \
+"\x05" "FLDCW\0" "\x04" "FXCH\0" "\x04" "FNOP\0" "\x04" "FCHS\0" "\x04" "FABS\0" \
+"\x04" "FTST\0" "\x04" "FXAM\0" "\x04" "FLD1\0" "\x06" "FLDL2T\0" "\x06" "FLDL2E\0" \
+"\x05" "FLDPI\0" "\x06" "FLDLG2\0" "\x06" "FLDLN2\0" "\x04" "FLDZ\0" "\x05" "F2XM1\0" \
+"\x05" "FYL2X\0" "\x05" "FPTAN\0" "\x06" "FPATAN\0" "\x07" "FXTRACT\0" "\x06" "FPREM1\0" \
+"\x07" "FDECSTP\0" "\x07" "FINCSTP\0" "\x05" "FPREM\0" "\x07" "FYL2XP1\0" "\x05" "FSQRT\0" \
+"\x07" "FSINCOS\0" "\x07" "FRNDINT\0" "\x06" "FSCALE\0" "\x04" "FSIN\0" "\x04" "FCOS\0" \
+"\x05" "FIADD\0" "\x05" "FIMUL\0" "\x05" "FICOM\0" "\x06" "FICOMP\0" "\x05" "FISUB\0" \
+"\x06" "FISUBR\0" "\x05" "FIDIV\0" "\x06" "FIDIVR\0" "\x06" "FCMOVB\0" "\x06" "FCMOVE\0" \
+"\x07" "FCMOVBE\0" "\x06" "FCMOVU\0" "\x07" "FUCOMPP\0" "\x04" "FILD\0" "\x06" "FISTTP\0" \
+"\x04" "FIST\0" "\x05" "FISTP\0" "\x07" "FCMOVNB\0" "\x07" "FCMOVNE\0" "\x08" "FCMOVNBE\0" \
+"\x07" "FCMOVNU\0" "\x04" "FENI\0" "\x06" "FEDISI\0" "\x06" "FSETPM\0" "\x06" "FUCOMI\0" \
+"\x05" "FCOMI\0" "\x06" "FRSTOR\0" "\x05" "FFREE\0" "\x05" "FUCOM\0" "\x06" "FUCOMP\0" \
+"\x05" "FADDP\0" "\x05" "FMULP\0" "\x06" "FCOMPP\0" "\x06" "FSUBRP\0" "\x05" "FSUBP\0" \
+"\x06" "FDIVRP\0" "\x05" "FDIVP\0" "\x04" "FBLD\0" "\x05" "FBSTP\0" "\x07" "FUCOMIP\0" \
+"\x06" "FCOMIP\0" "\x03" "NOT\0" "\x03" "NEG\0" "\x03" "MUL\0" "\x03" "DIV\0" \
+"\x04" "IDIV\0" "\x04" "SLDT\0" "\x03" "STR\0" "\x04" "LLDT\0" "\x03" "LTR\0" \
+"\x04" "VERR\0" "\x04" "VERW\0" "\x04" "SGDT\0" "\x04" "SIDT\0" "\x04" "LGDT\0" \
+"\x04" "LIDT\0" "\x04" "SMSW\0" "\x04" "LMSW\0" "\x06" "INVLPG\0" "\x06" "VMCALL\0" \
+"\x08" "VMLAUNCH\0" "\x08" "VMRESUME\0" "\x06" "VMXOFF\0" "\x07" "MONITOR\0" \
+"\x05" "MWAIT\0" "\x06" "XGETBV\0" "\x06" "XSETBV\0" "\x06" "VMFUNC\0" "\x04" "XEND\0" \
+"\x05" "VMRUN\0" "\x07" "VMMCALL\0" "\x06" "VMLOAD\0" "\x06" "VMSAVE\0" "\x04" "STGI\0" \
+"\x04" "CLGI\0" "\x06" "SKINIT\0" "\x07" "INVLPGA\0" "\x06" "SWAPGS\0" "\x06" "RDTSCP\0" \
+"\x08" "PREFETCH\0" "\x09" "PREFETCHW\0" "\x05" "PI2FW\0" "\x05" "PI2FD\0" \
+"\x05" "PF2IW\0" "\x05" "PF2ID\0" "\x06" "PFNACC\0" "\x07" "PFPNACC\0" "\x07" "PFCMPGE\0" \
+"\x05" "PFMIN\0" "\x05" "PFRCP\0" "\x07" "PFRSQRT\0" "\x05" "PFSUB\0" "\x05" "PFADD\0" \
+"\x07" "PFCMPGT\0" "\x05" "PFMAX\0" "\x08" "PFRCPIT1\0" "\x08" "PFRSQIT1\0" \
+"\x06" "PFSUBR\0" "\x05" "PFACC\0" "\x07" "PFCMPEQ\0" "\x05" "PFMUL\0" "\x08" "PFRCPIT2\0" \
+"\x07" "PMULHRW\0" "\x06" "PSWAPD\0" "\x07" "PAVGUSB\0" "\x06" "MOVUPS\0" "\x06" "MOVUPD\0" \
+"\x05" "MOVSS\0" "\x05" "MOVSD\0" "\x07" "VMOVUPS\0" "\x07" "VMOVUPD\0" "\x06" "VMOVSS\0" \
+"\x06" "VMOVSD\0" "\x07" "MOVHLPS\0" "\x06" "MOVLPS\0" "\x06" "MOVLPD\0" "\x08" "MOVSLDUP\0" \
+"\x07" "MOVDDUP\0" "\x08" "VMOVHLPS\0" "\x07" "VMOVLPS\0" "\x07" "VMOVLPD\0" \
+"\x09" "VMOVSLDUP\0" "\x08" "VMOVDDUP\0" "\x08" "UNPCKLPS\0" "\x08" "UNPCKLPD\0" \
+"\x09" "VUNPCKLPS\0" "\x09" "VUNPCKLPD\0" "\x08" "UNPCKHPS\0" "\x08" "UNPCKHPD\0" \
+"\x09" "VUNPCKHPS\0" "\x09" "VUNPCKHPD\0" "\x07" "MOVLHPS\0" "\x06" "MOVHPS\0" \
+"\x06" "MOVHPD\0" "\x08" "MOVSHDUP\0" "\x08" "VMOVLHPS\0" "\x07" "VMOVHPS\0" \
+"\x07" "VMOVHPD\0" "\x09" "VMOVSHDUP\0" "\x0b" "PREFETCHNTA\0" "\x0a" "PREFETCHT0\0" \
+"\x0a" "PREFETCHT1\0" "\x0a" "PREFETCHT2\0" "\x06" "MOVAPS\0" "\x06" "MOVAPD\0" \
+"\x07" "VMOVAPS\0" "\x07" "VMOVAPD\0" "\x08" "CVTPI2PS\0" "\x08" "CVTPI2PD\0" \
+"\x08" "CVTSI2SS\0" "\x08" "CVTSI2SD\0" "\x09" "VCVTSI2SS\0" "\x09" "VCVTSI2SD\0" \
+"\x07" "MOVNTPS\0" "\x07" "MOVNTPD\0" "\x07" "MOVNTSS\0" "\x07" "MOVNTSD\0" \
+"\x08" "VMOVNTPS\0" "\x08" "VMOVNTPD\0" "\x09" "CVTTPS2PI\0" "\x09" "CVTTPD2PI\0" \
+"\x09" "CVTTSS2SI\0" "\x09" "CVTTSD2SI\0" "\x0a" "VCVTTSS2SI\0" "\x0a" "VCVTTSD2SI\0" \
+"\x08" "CVTPS2PI\0" "\x08" "CVTPD2PI\0" "\x08" "CVTSS2SI\0" "\x08" "CVTSD2SI\0" \
+"\x09" "VCVTSS2SI\0" "\x09" "VCVTSD2SI\0" "\x07" "UCOMISS\0" "\x07" "UCOMISD\0" \
+"\x08" "VUCOMISS\0" "\x08" "VUCOMISD\0" "\x06" "COMISS\0" "\x06" "COMISD\0" \
+"\x07" "VCOMISS\0" "\x07" "VCOMISD\0" "\x08" "MOVMSKPS\0" "\x08" "MOVMSKPD\0" \
+"\x09" "VMOVMSKPS\0" "\x09" "VMOVMSKPD\0" "\x06" "SQRTPS\0" "\x06" "SQRTPD\0" \
+"\x06" "SQRTSS\0" "\x06" "SQRTSD\0" "\x07" "VSQRTPS\0" "\x07" "VSQRTPD\0" "\x07" "VSQRTSS\0" \
+"\x07" "VSQRTSD\0" "\x07" "RSQRTPS\0" "\x07" "RSQRTSS\0" "\x08" "VRSQRTPS\0" \
+"\x08" "VRSQRTSS\0" "\x05" "RCPPS\0" "\x05" "RCPSS\0" "\x06" "VRCPPS\0" "\x06" "VRCPSS\0" \
+"\x05" "ANDPS\0" "\x05" "ANDPD\0" "\x06" "VANDPS\0" "\x06" "VANDPD\0" "\x06" "ANDNPS\0" \
+"\x06" "ANDNPD\0" "\x07" "VANDNPS\0" "\x07" "VANDNPD\0" "\x04" "ORPS\0" "\x04" "ORPD\0" \
+"\x05" "VORPS\0" "\x05" "VORPD\0" "\x05" "XORPS\0" "\x05" "XORPD\0" "\x06" "VXORPS\0" \
+"\x06" "VXORPD\0" "\x05" "ADDPS\0" "\x05" "ADDPD\0" "\x05" "ADDSS\0" "\x05" "ADDSD\0" \
+"\x06" "VADDPS\0" "\x06" "VADDPD\0" "\x06" "VADDSS\0" "\x06" "VADDSD\0" "\x05" "MULPS\0" \
+"\x05" "MULPD\0" "\x05" "MULSS\0" "\x05" "MULSD\0" "\x06" "VMULPS\0" "\x06" "VMULPD\0" \
+"\x06" "VMULSS\0" "\x06" "VMULSD\0" "\x08" "CVTPS2PD\0" "\x08" "CVTPD2PS\0" \
+"\x08" "CVTSS2SD\0" "\x08" "CVTSD2SS\0" "\x09" "VCVTPS2PD\0" "\x09" "VCVTPD2PS\0" \
+"\x09" "VCVTSS2SD\0" "\x09" "VCVTSD2SS\0" "\x08" "CVTDQ2PS\0" "\x08" "CVTPS2DQ\0" \
+"\x09" "CVTTPS2DQ\0" "\x09" "VCVTDQ2PS\0" "\x09" "VCVTPS2DQ\0" "\x0a" "VCVTTPS2DQ\0" \
+"\x05" "SUBPS\0" "\x05" "SUBPD\0" "\x05" "SUBSS\0" "\x05" "SUBSD\0" "\x06" "VSUBPS\0" \
+"\x06" "VSUBPD\0" "\x06" "VSUBSS\0" "\x06" "VSUBSD\0" "\x05" "MINPS\0" "\x05" "MINPD\0" \
+"\x05" "MINSS\0" "\x05" "MINSD\0" "\x06" "VMINPS\0" "\x06" "VMINPD\0" "\x06" "VMINSS\0" \
+"\x06" "VMINSD\0" "\x05" "DIVPS\0" "\x05" "DIVPD\0" "\x05" "DIVSS\0" "\x05" "DIVSD\0" \
+"\x06" "VDIVPS\0" "\x06" "VDIVPD\0" "\x06" "VDIVSS\0" "\x06" "VDIVSD\0" "\x05" "MAXPS\0" \
+"\x05" "MAXPD\0" "\x05" "MAXSS\0" "\x05" "MAXSD\0" "\x06" "VMAXPS\0" "\x06" "VMAXPD\0" \
+"\x06" "VMAXSS\0" "\x06" "VMAXSD\0" "\x09" "PUNPCKLBW\0" "\x0a" "VPUNPCKLBW\0" \
+"\x09" "PUNPCKLWD\0" "\x0a" "VPUNPCKLWD\0" "\x09" "PUNPCKLDQ\0" "\x0a" "VPUNPCKLDQ\0" \
+"\x08" "PACKSSWB\0" "\x09" "VPACKSSWB\0" "\x07" "PCMPGTB\0" "\x08" "VPCMPGTB\0" \
+"\x07" "PCMPGTW\0" "\x08" "VPCMPGTW\0" "\x07" "PCMPGTD\0" "\x08" "VPCMPGTD\0" \
+"\x08" "PACKUSWB\0" "\x09" "VPACKUSWB\0" "\x09" "PUNPCKHBW\0" "\x0a" "VPUNPCKHBW\0" \
+"\x09" "PUNPCKHWD\0" "\x0a" "VPUNPCKHWD\0" "\x09" "PUNPCKHDQ\0" "\x0a" "VPUNPCKHDQ\0" \
+"\x08" "PACKSSDW\0" "\x09" "VPACKSSDW\0" "\x0a" "PUNPCKLQDQ\0" "\x0b" "VPUNPCKLQDQ\0" \
+"\x0a" "PUNPCKHQDQ\0" "\x0b" "VPUNPCKHQDQ\0" "\x04" "MOVD\0" "\x04" "MOVQ\0" \
+"\x05" "VMOVD\0" "\x05" "VMOVQ\0" "\x06" "MOVDQA\0" "\x06" "MOVDQU\0" "\x07" "VMOVDQA\0" \
+"\x07" "VMOVDQU\0" "\x06" "PSHUFW\0" "\x06" "PSHUFD\0" "\x07" "PSHUFHW\0" "\x07" "PSHUFLW\0" \
+"\x07" "VPSHUFD\0" "\x08" "VPSHUFHW\0" "\x08" "VPSHUFLW\0" "\x07" "PCMPEQB\0" \
+"\x08" "VPCMPEQB\0" "\x07" "PCMPEQW\0" "\x08" "VPCMPEQW\0" "\x07" "PCMPEQD\0" \
+"\x08" "VPCMPEQD\0" "\x04" "EMMS\0" "\x0a" "VZEROUPPER\0" "\x08" "VZEROALL\0" \
+"\x06" "VMREAD\0" "\x05" "EXTRQ\0" "\x07" "INSERTQ\0" "\x07" "VMWRITE\0" "\x08" "CVTPH2PS\0" \
+"\x08" "CVTPS2PH\0" "\x06" "HADDPD\0" "\x06" "HADDPS\0" "\x07" "VHADDPD\0" \
+"\x07" "VHADDPS\0" "\x06" "HSUBPD\0" "\x06" "HSUBPS\0" "\x07" "VHSUBPD\0" "\x07" "VHSUBPS\0" \
+"\x05" "XSAVE\0" "\x07" "XSAVE64\0" "\x06" "LFENCE\0" "\x06" "XRSTOR\0" "\x08" "XRSTOR64\0" \
+"\x06" "MFENCE\0" "\x08" "XSAVEOPT\0" "\x0a" "XSAVEOPT64\0" "\x06" "SFENCE\0" \
+"\x07" "CLFLUSH\0" "\x06" "POPCNT\0" "\x03" "BSF\0" "\x05" "TZCNT\0" "\x03" "BSR\0" \
+"\x05" "LZCNT\0" "\x07" "CMPEQPS\0" "\x07" "CMPLTPS\0" "\x07" "CMPLEPS\0" "\x0a" "CMPUNORDPS\0" \
+"\x08" "CMPNEQPS\0" "\x08" "CMPNLTPS\0" "\x08" "CMPNLEPS\0" "\x08" "CMPORDPS\0" \
+"\x07" "CMPEQPD\0" "\x07" "CMPLTPD\0" "\x07" "CMPLEPD\0" "\x0a" "CMPUNORDPD\0" \
+"\x08" "CMPNEQPD\0" "\x08" "CMPNLTPD\0" "\x08" "CMPNLEPD\0" "\x08" "CMPORDPD\0" \
+"\x07" "CMPEQSS\0" "\x07" "CMPLTSS\0" "\x07" "CMPLESS\0" "\x0a" "CMPUNORDSS\0" \
+"\x08" "CMPNEQSS\0" "\x08" "CMPNLTSS\0" "\x08" "CMPNLESS\0" "\x08" "CMPORDSS\0" \
+"\x07" "CMPEQSD\0" "\x07" "CMPLTSD\0" "\x07" "CMPLESD\0" "\x0a" "CMPUNORDSD\0" \
+"\x08" "CMPNEQSD\0" "\x08" "CMPNLTSD\0" "\x08" "CMPNLESD\0" "\x08" "CMPORDSD\0" \
+"\x08" "VCMPEQPS\0" "\x08" "VCMPLTPS\0" "\x08" "VCMPLEPS\0" "\x0b" "VCMPUNORDPS\0" \
+"\x09" "VCMPNEQPS\0" "\x09" "VCMPNLTPS\0" "\x09" "VCMPNLEPS\0" "\x09" "VCMPORDPS\0" \
+"\x0b" "VCMPEQ_UQPS\0" "\x09" "VCMPNGEPS\0" "\x09" "VCMPNGTPS\0" "\x0b" "VCMPFALSEPS\0" \
+"\x0c" "VCMPNEQ_OQPS\0" "\x08" "VCMPGEPS\0" "\x08" "VCMPGTPS\0" "\x0a" "VCMPTRUEPS\0" \
+"\x0b" "VCMPEQ_OSPS\0" "\x0b" "VCMPLT_OQPS\0" "\x0b" "VCMPLE_OQPS\0" "\x0d" "VCMPUNORD_SPS\0" \
+"\x0c" "VCMPNEQ_USPS\0" "\x0c" "VCMPNLT_UQPS\0" "\x0c" "VCMPNLE_UQPS\0" "\x0b" "VCMPORD_SPS\0" \
+"\x0b" "VCMPEQ_USPS\0" "\x0c" "VCMPNGE_UQPS\0" "\x0c" "VCMPNGT_UQPS\0" "\x0e" "VCMPFALSE_OSPS\0" \
+"\x0c" "VCMPNEQ_OSPS\0" "\x0b" "VCMPGE_OQPS\0" "\x0b" "VCMPGT_OQPS\0" "\x0d" "VCMPTRUE_USPS\0" \
+"\x08" "VCMPEQPD\0" "\x08" "VCMPLTPD\0" "\x08" "VCMPLEPD\0" "\x0b" "VCMPUNORDPD\0" \
+"\x09" "VCMPNEQPD\0" "\x09" "VCMPNLTPD\0" "\x09" "VCMPNLEPD\0" "\x09" "VCMPORDPD\0" \
+"\x0b" "VCMPEQ_UQPD\0" "\x09" "VCMPNGEPD\0" "\x09" "VCMPNGTPD\0" "\x0b" "VCMPFALSEPD\0" \
+"\x0c" "VCMPNEQ_OQPD\0" "\x08" "VCMPGEPD\0" "\x08" "VCMPGTPD\0" "\x0a" "VCMPTRUEPD\0" \
+"\x0b" "VCMPEQ_OSPD\0" "\x0b" "VCMPLT_OQPD\0" "\x0b" "VCMPLE_OQPD\0" "\x0d" "VCMPUNORD_SPD\0" \
+"\x0c" "VCMPNEQ_USPD\0" "\x0c" "VCMPNLT_UQPD\0" "\x0c" "VCMPNLE_UQPD\0" "\x0b" "VCMPORD_SPD\0" \
+"\x0b" "VCMPEQ_USPD\0" "\x0c" "VCMPNGE_UQPD\0" "\x0c" "VCMPNGT_UQPD\0" "\x0e" "VCMPFALSE_OSPD\0" \
+"\x0c" "VCMPNEQ_OSPD\0" "\x0b" "VCMPGE_OQPD\0" "\x0b" "VCMPGT_OQPD\0" "\x0d" "VCMPTRUE_USPD\0" \
+"\x08" "VCMPEQSS\0" "\x08" "VCMPLTSS\0" "\x08" "VCMPLESS\0" "\x0b" "VCMPUNORDSS\0" \
+"\x09" "VCMPNEQSS\0" "\x09" "VCMPNLTSS\0" "\x09" "VCMPNLESS\0" "\x09" "VCMPORDSS\0" \
+"\x0b" "VCMPEQ_UQSS\0" "\x09" "VCMPNGESS\0" "\x09" "VCMPNGTSS\0" "\x0b" "VCMPFALSESS\0" \
+"\x0c" "VCMPNEQ_OQSS\0" "\x08" "VCMPGESS\0" "\x08" "VCMPGTSS\0" "\x0a" "VCMPTRUESS\0" \
+"\x0b" "VCMPEQ_OSSS\0" "\x0b" "VCMPLT_OQSS\0" "\x0b" "VCMPLE_OQSS\0" "\x0d" "VCMPUNORD_SSS\0" \
+"\x0c" "VCMPNEQ_USSS\0" "\x0c" "VCMPNLT_UQSS\0" "\x0c" "VCMPNLE_UQSS\0" "\x0b" "VCMPORD_SSS\0" \
+"\x0b" "VCMPEQ_USSS\0" "\x0c" "VCMPNGE_UQSS\0" "\x0c" "VCMPNGT_UQSS\0" "\x0e" "VCMPFALSE_OSSS\0" \
+"\x0c" "VCMPNEQ_OSSS\0" "\x0b" "VCMPGE_OQSS\0" "\x0b" "VCMPGT_OQSS\0" "\x0d" "VCMPTRUE_USSS\0" \
+"\x08" "VCMPEQSD\0" "\x08" "VCMPLTSD\0" "\x08" "VCMPLESD\0" "\x0b" "VCMPUNORDSD\0" \
+"\x09" "VCMPNEQSD\0" "\x09" "VCMPNLTSD\0" "\x09" "VCMPNLESD\0" "\x09" "VCMPORDSD\0" \
+"\x0b" "VCMPEQ_UQSD\0" "\x09" "VCMPNGESD\0" "\x09" "VCMPNGTSD\0" "\x0b" "VCMPFALSESD\0" \
+"\x0c" "VCMPNEQ_OQSD\0" "\x08" "VCMPGESD\0" "\x08" "VCMPGTSD\0" "\x0a" "VCMPTRUESD\0" \
+"\x0b" "VCMPEQ_OSSD\0" "\x0b" "VCMPLT_OQSD\0" "\x0b" "VCMPLE_OQSD\0" "\x0d" "VCMPUNORD_SSD\0" \
+"\x0c" "VCMPNEQ_USSD\0" "\x0c" "VCMPNLT_UQSD\0" "\x0c" "VCMPNLE_UQSD\0" "\x0b" "VCMPORD_SSD\0" \
+"\x0b" "VCMPEQ_USSD\0" "\x0c" "VCMPNGE_UQSD\0" "\x0c" "VCMPNGT_UQSD\0" "\x0e" "VCMPFALSE_OSSD\0" \
+"\x0c" "VCMPNEQ_OSSD\0" "\x0b" "VCMPGE_OQSD\0" "\x0b" "VCMPGT_OQSD\0" "\x0d" "VCMPTRUE_USSD\0" \
+"\x06" "PINSRW\0" "\x07" "VPINSRW\0" "\x06" "PEXTRW\0" "\x07" "VPEXTRW\0" "\x06" "SHUFPS\0" \
+"\x06" "SHUFPD\0" "\x07" "VSHUFPS\0" "\x07" "VSHUFPD\0" "\x09" "CMPXCHG8B\0" \
+"\x0a" "CMPXCHG16B\0" "\x07" "VMPTRST\0" "\x08" "ADDSUBPD\0" "\x08" "ADDSUBPS\0" \
+"\x09" "VADDSUBPD\0" "\x09" "VADDSUBPS\0" "\x05" "PSRLW\0" "\x06" "VPSRLW\0" \
+"\x05" "PSRLD\0" "\x06" "VPSRLD\0" "\x05" "PSRLQ\0" "\x06" "VPSRLQ\0" "\x05" "PADDQ\0" \
+"\x06" "VPADDQ\0" "\x06" "PMULLW\0" "\x07" "VPMULLW\0" "\x07" "MOVQ2DQ\0" "\x07" "MOVDQ2Q\0" \
+"\x08" "PMOVMSKB\0" "\x09" "VPMOVMSKB\0" "\x07" "PSUBUSB\0" "\x08" "VPSUBUSB\0" \
+"\x07" "PSUBUSW\0" "\x08" "VPSUBUSW\0" "\x06" "PMINUB\0" "\x07" "VPMINUB\0" \
+"\x04" "PAND\0" "\x05" "VPAND\0" "\x07" "PADDUSB\0" "\x08" "VPADDUSW\0" "\x07" "PADDUSW\0" \
+"\x06" "PMAXUB\0" "\x07" "VPMAXUB\0" "\x05" "PANDN\0" "\x06" "VPANDN\0" "\x05" "PAVGB\0" \
+"\x06" "VPAVGB\0" "\x05" "PSRAW\0" "\x06" "VPSRAW\0" "\x05" "PSRAD\0" "\x06" "VPSRAD\0" \
+"\x05" "PAVGW\0" "\x06" "VPAVGW\0" "\x07" "PMULHUW\0" "\x08" "VPMULHUW\0" "\x06" "PMULHW\0" \
+"\x07" "VPMULHW\0" "\x09" "CVTTPD2DQ\0" "\x08" "CVTDQ2PD\0" "\x08" "CVTPD2DQ\0" \
+"\x0a" "VCVTTPD2DQ\0" "\x09" "VCVTDQ2PD\0" "\x09" "VCVTPD2DQ\0" "\x06" "MOVNTQ\0" \
+"\x07" "MOVNTDQ\0" "\x08" "VMOVNTDQ\0" "\x06" "PSUBSB\0" "\x07" "VPSUBSB\0" \
+"\x06" "PSUBSW\0" "\x07" "VPSUBSW\0" "\x06" "PMINSW\0" "\x07" "VPMINSW\0" "\x03" "POR\0" \
+"\x04" "VPOR\0" "\x06" "PADDSB\0" "\x07" "VPADDSB\0" "\x06" "PADDSW\0" "\x07" "VPADDSW\0" \
+"\x06" "PMAXSW\0" "\x07" "VPMAXSW\0" "\x04" "PXOR\0" "\x05" "VPXOR\0" "\x05" "LDDQU\0" \
+"\x06" "VLDDQU\0" "\x05" "PSLLW\0" "\x06" "VPSLLW\0" "\x05" "PSLLD\0" "\x06" "VPSLLD\0" \
+"\x05" "PSLLQ\0" "\x06" "VPSLLQ\0" "\x07" "PMULUDQ\0" "\x08" "VPMULUDQ\0" "\x07" "PMADDWD\0" \
+"\x08" "VPMADDWD\0" "\x06" "PSADBW\0" "\x07" "VPSADBW\0" "\x08" "MASKMOVQ\0" \
+"\x0a" "MASKMOVDQU\0" "\x0b" "VMASKMOVDQU\0" "\x05" "PSUBB\0" "\x06" "VPSUBB\0" \
+"\x05" "PSUBW\0" "\x06" "VPSUBW\0" "\x05" "PSUBD\0" "\x06" "VPSUBD\0" "\x05" "PSUBQ\0" \
+"\x06" "VPSUBQ\0" "\x05" "PADDB\0" "\x06" "VPADDB\0" "\x05" "PADDW\0" "\x06" "VPADDW\0" \
+"\x05" "PADDD\0" "\x06" "VPADDD\0" "\x07" "FNSTENV\0" "\x06" "FSTENV\0" "\x06" "FNSTCW\0" \
+"\x05" "FSTCW\0" "\x06" "FNCLEX\0" "\x05" "FCLEX\0" "\x06" "FNINIT\0" "\x05" "FINIT\0" \
+"\x06" "FNSAVE\0" "\x05" "FSAVE\0" "\x06" "FNSTSW\0" "\x05" "FSTSW\0" "\x06" "PSHUFB\0" \
+"\x07" "VPSHUFB\0" "\x06" "PHADDW\0" "\x07" "VPHADDW\0" "\x06" "PHADDD\0" "\x07" "VPHADDD\0" \
+"\x07" "PHADDSW\0" "\x08" "VPHADDSW\0" "\x09" "PMADDUBSW\0" "\x0a" "VPMADDUBSW\0" \
+"\x06" "PHSUBW\0" "\x07" "VPHSUBW\0" "\x06" "PHSUBD\0" "\x07" "VPHSUBD\0" "\x07" "PHSUBSW\0" \
+"\x08" "VPHSUBSW\0" "\x06" "PSIGNB\0" "\x07" "VPSIGNB\0" "\x06" "PSIGNW\0" \
+"\x07" "VPSIGNW\0" "\x06" "PSIGND\0" "\x07" "VPSIGND\0" "\x08" "PMULHRSW\0" \
+"\x09" "VPMULHRSW\0" "\x09" "VPERMILPS\0" "\x09" "VPERMILPD\0" "\x07" "VTESTPS\0" \
+"\x07" "VTESTPD\0" "\x08" "PBLENDVB\0" "\x08" "BLENDVPS\0" "\x08" "BLENDVPD\0" \
+"\x05" "PTEST\0" "\x06" "VPTEST\0" "\x0c" "VBROADCASTSS\0" "\x0c" "VBROADCASTSD\0" \
+"\x0e" "VBROADCASTF128\0" "\x05" "PABSB\0" "\x06" "VPABSB\0" "\x05" "PABSW\0" \
+"\x06" "VPABSW\0" "\x05" "PABSD\0" "\x06" "VPABSD\0" "\x08" "PMOVSXBW\0" "\x09" "VPMOVSXBW\0" \
+"\x08" "PMOVSXBD\0" "\x09" "VPMOVSXBD\0" "\x08" "PMOVSXBQ\0" "\x09" "VPMOVSXBQ\0" \
+"\x08" "PMOVSXWD\0" "\x09" "VPMOVSXWD\0" "\x08" "PMOVSXWQ\0" "\x09" "VPMOVSXWQ\0" \
+"\x08" "PMOVSXDQ\0" "\x09" "VPMOVSXDQ\0" "\x06" "PMULDQ\0" "\x07" "VPMULDQ\0" \
+"\x07" "PCMPEQQ\0" "\x08" "VPCMPEQQ\0" "\x08" "MOVNTDQA\0" "\x09" "VMOVNTDQA\0" \
+"\x08" "PACKUSDW\0" "\x09" "VPACKUSDW\0" "\x0a" "VMASKMOVPS\0" "\x0a" "VMASKMOVPD\0" \
+"\x08" "PMOVZXBW\0" "\x09" "VPMOVZXBW\0" "\x08" "PMOVZXBD\0" "\x09" "VPMOVZXBD\0" \
+"\x08" "PMOVZXBQ\0" "\x09" "VPMOVZXBQ\0" "\x08" "PMOVZXWD\0" "\x09" "VPMOVZXWD\0" \
+"\x08" "PMOVZXWQ\0" "\x09" "VPMOVZXWQ\0" "\x08" "PMOVZXDQ\0" "\x09" "VPMOVZXDQ\0" \
+"\x07" "PCMPGTQ\0" "\x08" "VPCMPGTQ\0" "\x06" "PMINSB\0" "\x07" "VPMINSB\0" \
+"\x06" "PMINSD\0" "\x07" "VPMINSD\0" "\x06" "PMINUW\0" "\x07" "VPMINUW\0" "\x06" "PMINUD\0" \
+"\x07" "VPMINUD\0" "\x06" "PMAXSB\0" "\x07" "VPMAXSB\0" "\x06" "PMAXSD\0" "\x07" "VPMAXSD\0" \
+"\x06" "PMAXUW\0" "\x07" "VPMAXUW\0" "\x06" "PMAXUD\0" "\x07" "VPMAXUD\0" "\x06" "PMULLD\0" \
+"\x07" "VPMULLD\0" "\x0a" "PHMINPOSUW\0" "\x0b" "VPHMINPOSUW\0" "\x06" "INVEPT\0" \
+"\x07" "INVVPID\0" "\x07" "INVPCID\0" "\x0e" "VFMADDSUB132PS\0" "\x0e" "VFMADDSUB132PD\0" \
+"\x0e" "VFMSUBADD132PS\0" "\x0e" "VFMSUBADD132PD\0" "\x0b" "VFMADD132PS\0" \
+"\x0b" "VFMADD132PD\0" "\x0b" "VFMADD132SS\0" "\x0b" "VFMADD132SD\0" "\x0b" "VFMSUB132PS\0" \
+"\x0b" "VFMSUB132PD\0" "\x0b" "VFMSUB132SS\0" "\x0b" "VFMSUB132SD\0" "\x0c" "VFNMADD132PS\0" \
+"\x0c" "VFNMADD132PD\0" "\x0c" "VFNMADD132SS\0" "\x0c" "VFNMADD132SD\0" "\x0c" "VFNMSUB132PS\0" \
+"\x0c" "VFNMSUB132PD\0" "\x0c" "VFNMSUB132SS\0" "\x0c" "VFNMSUB132SD\0" "\x0e" "VFMADDSUB213PS\0" \
+"\x0e" "VFMADDSUB213PD\0" "\x0e" "VFMSUBADD213PS\0" "\x0e" "VFMSUBADD213PD\0" \
+"\x0b" "VFMADD213PS\0" "\x0b" "VFMADD213PD\0" "\x0b" "VFMADD213SS\0" "\x0b" "VFMADD213SD\0" \
+"\x0b" "VFMSUB213PS\0" "\x0b" "VFMSUB213PD\0" "\x0b" "VFMSUB213SS\0" "\x0b" "VFMSUB213SD\0" \
+"\x0c" "VFNMADD213PS\0" "\x0c" "VFNMADD213PD\0" "\x0c" "VFNMADD213SS\0" "\x0c" "VFNMADD213SD\0" \
+"\x0c" "VFNMSUB213PS\0" "\x0c" "VFNMSUB213PD\0" "\x0c" "VFNMSUB213SS\0" "\x0c" "VFNMSUB213SD\0" \
+"\x0e" "VFMADDSUB231PS\0" "\x0e" "VFMADDSUB231PD\0" "\x0e" "VFMSUBADD231PS\0" \
+"\x0e" "VFMSUBADD231PD\0" "\x0b" "VFMADD231PS\0" "\x0b" "VFMADD231PD\0" "\x0b" "VFMADD231SS\0" \
+"\x0b" "VFMADD231SD\0" "\x0b" "VFMSUB231PS\0" "\x0b" "VFMSUB231PD\0" "\x0b" "VFMSUB231SS\0" \
+"\x0b" "VFMSUB231SD\0" "\x0c" "VFNMADD231PS\0" "\x0c" "VFNMADD231PD\0" "\x0c" "VFNMADD231SS\0" \
+"\x0c" "VFNMADD231SD\0" "\x0c" "VFNMSUB231PS\0" "\x0c" "VFNMSUB231PD\0" "\x0c" "VFNMSUB231SS\0" \
+"\x0c" "VFNMSUB231SD\0" "\x06" "AESIMC\0" "\x07" "VAESIMC\0" "\x06" "AESENC\0" \
+"\x07" "VAESENC\0" "\x0a" "AESENCLAST\0" "\x0b" "VAESENCLAST\0" "\x06" "AESDEC\0" \
+"\x07" "VAESDEC\0" "\x0a" "AESDECLAST\0" "\x0b" "VAESDECLAST\0" "\x05" "MOVBE\0" \
+"\x05" "CRC32\0" "\x0a" "VPERM2F128\0" "\x07" "ROUNDPS\0" "\x08" "VROUNDPS\0" \
+"\x07" "ROUNDPD\0" "\x08" "VROUNDPD\0" "\x07" "ROUNDSS\0" "\x08" "VROUNDSS\0" \
+"\x07" "ROUNDSD\0" "\x08" "VROUNDSD\0" "\x07" "BLENDPS\0" "\x08" "VBLENDPS\0" \
+"\x07" "BLENDPD\0" "\x08" "VBLENDPD\0" "\x07" "PBLENDW\0" "\x08" "VPBLENDW\0" \
+"\x07" "PALIGNR\0" "\x08" "VPALIGNR\0" "\x06" "PEXTRB\0" "\x07" "VPEXTRB\0" \
+"\x06" "PEXTRD\0" "\x06" "PEXTRQ\0" "\x07" "VPEXTRD\0" "\x07" "VPEXTRQ\0" "\x09" "EXTRACTPS\0" \
+"\x0a" "VEXTRACTPS\0" "\x0b" "VINSERTF128\0" "\x0c" "VEXTRACTF128\0" "\x06" "PINSRB\0" \
+"\x07" "VPINSRB\0" "\x08" "INSERTPS\0" "\x09" "VINSERTPS\0" "\x06" "PINSRD\0" \
+"\x06" "PINSRQ\0" "\x07" "VPINSRD\0" "\x07" "VPINSRQ\0" "\x04" "DPPS\0" "\x05" "VDPPS\0" \
+"\x04" "DPPD\0" "\x05" "VDPPD\0" "\x07" "MPSADBW\0" "\x08" "VMPSADBW\0" "\x09" "PCLMULQDQ\0" \
+"\x0a" "VPCLMULQDQ\0" "\x09" "VBLENDVPS\0" "\x09" "VBLENDVPD\0" "\x09" "VPBLENDVB\0" \
+"\x09" "PCMPESTRM\0" "\x0a" "VPCMPESTRM\0" "\x09" "PCMPESTRI\0" "\x0a" "VPCMPESTRI\0" \
+"\x09" "PCMPISTRM\0" "\x0a" "VPCMPISTRM\0" "\x09" "PCMPISTRI\0" "\x0a" "VPCMPISTRI\0" \
+"\x0f" "AESKEYGENASSIST\0" "\x10" "VAESKEYGENASSIST\0" "\x06" "PSRLDQ\0" "\x07" "VPSRLDQ\0" \
+"\x06" "PSLLDQ\0" "\x07" "VPSLLDQ\0" "\x06" "FXSAVE\0" "\x08" "FXSAVE64\0" \
+"\x08" "RDFSBASE\0" "\x07" "FXRSTOR\0" "\x09" "FXRSTOR64\0" "\x08" "RDGSBASE\0" \
+"\x07" "LDMXCSR\0" "\x08" "WRFSBASE\0" "\x08" "VLDMXCSR\0" "\x07" "STMXCSR\0" \
+"\x08" "WRGSBASE\0" "\x08" "VSTMXCSR\0" "\x07" "VMPTRLD\0" "\x07" "VMCLEAR\0" \
+"\x05" "VMXON\0" "\x06" "MOVSXD\0" "\x05" "PAUSE\0" "\x04" "WAIT\0" "\x06" "RDRAND\0" \
+"\x06" "_3DNOW\0";
+
+const _WRegister _REGISTERS[] = {
+	{ 3, "RAX" }, { 3, "RCX" }, { 3, "RDX" }, { 3, "RBX" }, { 3, "RSP" }, { 3, "RBP" }, { 3, "RSI" }, { 3, "RDI" }, { 2, "R8" }, { 2, "R9" }, { 3, "R10" }, { 3, "R11" }, { 3, "R12" }, { 3, "R13" }, { 3, "R14" }, { 3, "R15" },
+	{ 3, "EAX" }, { 3, "ECX" }, { 3, "EDX" }, { 3, "EBX" }, { 3, "ESP" }, { 3, "EBP" }, { 3, "ESI" }, { 3, "EDI" }, { 3, "R8D" }, { 3, "R9D" }, { 4, "R10D" }, { 4, "R11D" }, { 4, "R12D" }, { 4, "R13D" }, { 4, "R14D" }, { 4, "R15D" },
+	{ 2, "AX" }, { 2, "CX" }, { 2, "DX" }, { 2, "BX" }, { 2, "SP" }, { 2, "BP" }, { 2, "SI" }, { 2, "DI" }, { 3, "R8W" }, { 3, "R9W" }, { 4, "R10W" }, { 4, "R11W" }, { 4, "R12W" }, { 4, "R13W" }, { 4, "R14W" }, { 4, "R15W" },
+	{ 2, "AL" }, { 2, "CL" }, { 2, "DL" }, { 2, "BL" }, { 2, "AH" }, { 2, "CH" }, { 2, "DH" }, { 2, "BH" }, { 3, "R8B" }, { 3, "R9B" }, { 4, "R10B" }, { 4, "R11B" }, { 4, "R12B" }, { 4, "R13B" }, { 4, "R14B" }, { 4, "R15B" },
+	{ 3, "SPL" }, { 3, "BPL" }, { 3, "SIL" }, { 3, "DIL" },
+	{ 2, "ES" }, { 2, "CS" }, { 2, "SS" }, { 2, "DS" }, { 2, "FS" }, { 2, "GS" },
+	{ 3, "RIP" },
+	{ 3, "ST0" }, { 3, "ST1" }, { 3, "ST2" }, { 3, "ST3" }, { 3, "ST4" }, { 3, "ST5" }, { 3, "ST6" }, { 3, "ST7" },
+	{ 3, "MM0" }, { 3, "MM1" }, { 3, "MM2" }, { 3, "MM3" }, { 3, "MM4" }, { 3, "MM5" }, { 3, "MM6" }, { 3, "MM7" },
+	{ 4, "XMM0" }, { 4, "XMM1" }, { 4, "XMM2" }, { 4, "XMM3" }, { 4, "XMM4" }, { 4, "XMM5" }, { 4, "XMM6" }, { 4, "XMM7" }, { 4, "XMM8" }, { 4, "XMM9" }, { 5, "XMM10" }, { 5, "XMM11" }, { 5, "XMM12" }, { 5, "XMM13" }, { 5, "XMM14" }, { 5, "XMM15" },
+	{ 4, "YMM0" }, { 4, "YMM1" }, { 4, "YMM2" }, { 4, "YMM3" }, { 4, "YMM4" }, { 4, "YMM5" }, { 4, "YMM6" }, { 4, "YMM7" }, { 4, "YMM8" }, { 4, "YMM9" }, { 5, "YMM10" }, { 5, "YMM11" }, { 5, "YMM12" }, { 5, "YMM13" }, { 5, "YMM14" }, { 5, "YMM15" },
+	{ 3, "CR0" }, { 0, "" }, { 3, "CR2" }, { 3, "CR3" }, { 3, "CR4" }, { 0, "" }, { 0, "" }, { 0, "" }, { 3, "CR8" },
+	{ 3, "DR0" }, { 3, "DR1" }, { 3, "DR2" }, { 3, "DR3" }, { 0, "" }, { 0, "" }, { 3, "DR6" }, { 3, "DR7" }
+};
+
+#endif /* DISTORM_LIGHT */

data/funchook/distorm/src/operands.c

@@ -0,0 +1,1290 @@
+/*
+operands.c
+
+diStorm3 - Powerful disassembler for X86/AMD64
+http://ragestorm.net/distorm/
+distorm at gmail dot com
+Copyright (C) 2003-2016 Gil Dabah
+This library is licensed under the BSD license. See the file COPYING.
+*/
+
+
+#include "config.h"
+#include "operands.h"
+#include "x86defs.h"
+#include "insts.h"
+#include "../include/mnemonics.h"
+
+
+/* Maps a register to its register-class mask. */
+uint32_t _REGISTERTORCLASS[] = /* Based on _RegisterType enumeration! */
+{RM_AX, RM_CX, RM_DX, RM_BX, RM_SP, RM_BP, RM_SI, RM_DI, RM_R8, RM_R9, RM_R10, RM_R11, RM_R12, RM_R13, RM_R14, RM_R15,
+ RM_AX, RM_CX, RM_DX, RM_BX, RM_SP, RM_BP, RM_SI, RM_DI, RM_R8, RM_R9, RM_R10, RM_R11, RM_R12, RM_R13, RM_R14, RM_R15,
+ RM_AX, RM_CX, RM_DX, RM_BX, RM_SP, RM_BP, RM_SI, RM_DI, RM_R8, RM_R9, RM_R10, RM_R11, RM_R12, RM_R13, RM_R14, RM_R15,
+ RM_AX, RM_CX, RM_DX, RM_BX, RM_AX, RM_CX, RM_DX, RM_BX, RM_R8, RM_R9, RM_R10, RM_R11, RM_R12, RM_R13, RM_R14, RM_R15,
+ RM_SP, RM_BP, RM_SI, RM_DI,
+ 0, 0, 0, 0, 0, 0,
+ 0,
+ RM_FPU, RM_FPU, RM_FPU, RM_FPU, RM_FPU, RM_FPU, RM_FPU, RM_FPU,
+ RM_MMX, RM_MMX, RM_MMX, RM_MMX, RM_MMX, RM_MMX, RM_MMX, RM_MMX,
+ RM_SSE, RM_SSE, RM_SSE, RM_SSE, RM_SSE, RM_SSE, RM_SSE, RM_SSE, RM_SSE, RM_SSE, RM_SSE, RM_SSE, RM_SSE, RM_SSE, RM_SSE, RM_SSE,
+ RM_AVX, RM_AVX, RM_AVX, RM_AVX, RM_AVX, RM_AVX, RM_AVX, RM_AVX, RM_AVX, RM_AVX, RM_AVX, RM_AVX, RM_AVX, RM_AVX, RM_AVX, RM_AVX,
+ RM_CR, 0, RM_CR, RM_CR, RM_CR, 0, 0, 0, RM_CR,
+ RM_DR, RM_DR, RM_DR, RM_DR, 0, 0, RM_DR, RM_DR
+};
+
+typedef enum {OPERAND_SIZE_NONE = 0, OPERAND_SIZE8, OPERAND_SIZE16, OPERAND_SIZE32, OPERAND_SIZE64, OPERAND_SIZE80, OPERAND_SIZE128, OPERAND_SIZE256} _OperandSizeType;
+static uint16_t _OPSIZETOINT[] = {0, 8, 16, 32, 64, 80, 128, 256};
+
+/* A helper function to fix the 8 bits register if REX is used (to support SIL, DIL, etc). */
+static unsigned int _FASTCALL_ operands_fix_8bit_rex_base(unsigned int reg)
+{
+	if ((reg >= 4) && (reg < 8)) return reg + REGS8_REX_BASE - 4;
+	return reg + REGS8_BASE;
+}
+
+/* A helper function to set operand's type and size. */
+static void _FASTCALL_ operands_set_ts(_Operand* op, _OperandType type, uint16_t size)
+{
+	op->type = type;
+	op->size = size;
+}
+
+/* A helper function to set operand's type, size and index. */
+static void _FASTCALL_ operands_set_tsi(_Operand* op, _OperandType type, uint16_t size, unsigned int index)
+{
+	op->type = type;
+	op->index = (uint8_t)index;
+	op->size = size;
+}
+
+/* A helper function to read an unsigned integer from the stream safely. */
+static int _FASTCALL_ read_stream_safe_uint(_CodeInfo* ci, void* result, unsigned int size)
+{
+	ci->codeLen -= size;
+	if (ci->codeLen < 0) return FALSE;
+	switch (size)
+	{
+		case 1: *(uint8_t*)result = *(uint8_t*)ci->code; break;
+		case 2: *(uint16_t*)result = RUSHORT(ci->code); break;
+		case 4: *(uint32_t*)result = RULONG(ci->code); break;
+		case 8: *(uint64_t*)result = RULLONG(ci->code); break;
+	}
+	ci->code += size;
+	return TRUE;
+}
+
+/* A helper function to read a signed integer from the stream safely. */
+static int _FASTCALL_ read_stream_safe_sint(_CodeInfo* ci, int64_t* result, unsigned int size)
+{
+	ci->codeLen -= size;
+	if (ci->codeLen < 0) return FALSE;
+	switch (size)
+	{
+		case 1: *result = *(int8_t*)ci->code; break;
+		case 2: *result = RSHORT(ci->code); break;
+		case 4: *result = RLONG(ci->code); break;
+		case 8: *result = RLLONG(ci->code); break;
+	}
+	ci->code += size;
+	return TRUE;
+}
+
+/*
+ * SIB decoding is the most confusing part when decoding IA-32 instructions.
+ * This explanation should clear up some stuff.
+ *
+ * ! When base == 5, use EBP as the base register !
+ * if (rm == 4) {
+ *	if mod == 01, decode SIB byte and ALSO read a 8 bits displacement.
+ *	if mod == 10, decode SIB byte and ALSO read a 32 bits displacement.
+ *	if mod == 11 <-- EXCEPTION, this is a general-purpose register and mustn't lead to SIB decoding!
+ *	; So far so good, now the confusing part comes in with mod == 0 and base=5, but no worry.
+ *	if (mod == 00) {
+ *	 decode SIB byte WITHOUT any displacement.
+ *	 EXCEPTION!!! when base == 5, read a 32 bits displacement, but this time DO NOT use (EBP) BASE at all!
+ *	}
+ *
+ *	NOTE: base could specify None (no base register) if base==5 and mod==0, but then you also need DISP32.
+ * }
+ */
+static void operands_extract_sib(_DInst* di, _OperandNumberType opNum,
+                                 _PrefixState* ps, _DecodeType effAdrSz,
+                                 unsigned int sib, unsigned int mod)
+{
+	unsigned int scale = 0, index = 0, base = 0;
+	unsigned int vrex = ps->vrex;
+	uint8_t* pIndex = NULL;
+
+	_Operand* op = &di->ops[opNum];
+
+	/*
+	 * SIB bits:
+	 * |7---6-5----3-2---0|
+	 * |SCALE| INDEX| BASE|
+	 * |------------------|
+	 */
+	scale = (sib >> 6) & 3;
+	index = (sib >> 3) & 7;
+	base = sib & 7;
+
+	/*
+	 * The following fields: base/index/scale/disp8/32 are ALL optional by specific rules!
+	 * The idea here is to keep the indirection as a simple-memory type.
+	 * Because the base is optional, and we might be left with only one index.
+	 * So even if there's a base but no index, or vice versa, we end up with one index register.
+	 */
+
+	/* In 64 bits the REX prefix might affect the index of the SIB byte. */
+	if (vrex & PREFIX_EX_X) {
+		ps->usedPrefixes |= INST_PRE_REX;
+		index += EX_GPR_BASE;
+	}
+
+	if (index == 4) { /* No index is used. Use SMEM. */
+		op->type = O_SMEM;
+		pIndex = &op->index;
+	} else {
+		op->type = O_MEM;
+		pIndex = &di->base;
+		/* No base, unless it is updated below. E.G: [EAX*4] has no base reg. */
+	}
+
+	if (base != 5) {
+		if (vrex & PREFIX_EX_B) ps->usedPrefixes |= INST_PRE_REX;
+		*pIndex = effAdrSz == Decode64Bits ? REGS64_BASE : REGS32_BASE;
+		*pIndex += (uint8_t)(base + ((vrex & PREFIX_EX_B) ? EX_GPR_BASE : 0));
+	} else if (mod != 0) {
+		/*
+		 * if base == 5 then you have to decode according to MOD.
+		 * mod(00) - disp32.
+		 * mod(01) - disp8 + rBP
+		 * mod(10) - disp32 + rBP
+		 * mod(11) - not possible, it's a general-purpose register.
+		 */
+
+		if (vrex & PREFIX_EX_B) ps->usedPrefixes |= INST_PRE_REX;
+		if (effAdrSz == Decode64Bits) *pIndex = REGS64_BASE + 5 + ((vrex & PREFIX_EX_B) ? EX_GPR_BASE : 0);
+		else *pIndex = REGS32_BASE + 5 + ((vrex & PREFIX_EX_B) ? EX_GPR_BASE : 0);
+	} else if (index == 4) {
+		 /* 32bits displacement only. */
+		op->type = O_DISP;
+		return;
+	}
+
+	if (index != 4) { /* In 64 bits decoding mode, if index == R12, it's valid! */
+		if (effAdrSz == Decode64Bits) op->index = (uint8_t)(REGS64_BASE + index);
+		else op->index = (uint8_t)(REGS32_BASE + index);
+		di->scale = scale != 0 ? (1 << scale) : 0;
+	}
+}
+
+/*
+ * This seems to be the hardest part in decoding the operands.
+ * If you take a look carefully at Table 2-2. 32-Bit Addressing Forms with the ModR/M Byte,
+ * you will understand it's easy to decode the operands.
+
+ * First we check the DT, so we can decide according to which Table in the documentation we are supposed to decode.
+ * Then we follow the specific table whether it's 16 bits or 32/64 bits.
+
+ * Don't forget that Operand Size AND Address Size prefixes may change the decoding!
+
+ * Some instructions force the use of RM16 or other specific types, so take it into account.
+ */
+static int operands_extract_modrm(_CodeInfo* ci,
+                                  _DInst* di, _OpType type,
+                                  _OperandNumberType opNum, _PrefixState* ps,
+                                  _DecodeType effOpSz, _DecodeType effAdrSz,
+                                  int* lockableInstruction, unsigned int mod, unsigned int rm,
+                                  _iflags instFlags)
+{
+	unsigned int vrex = ps->vrex, sib = 0, base = 0;
+	_Operand* op = &di->ops[opNum];
+	uint16_t size = 0;
+
+	if (mod == 3) {
+		/*
+		 * General-purpose register is handled the same way in 16/32/64 bits decoding modes.
+		 * NOTE!! that we have to override the size of the register, since it was set earlier as Memory and not Register!
+		 */
+		op->type = O_REG;
+		/* Start with original size which was set earlier, some registers have same size of memory and depend on it. */
+		size = op->size;
+		switch(type)
+		{
+			case OT_RFULL_M16:
+			case OT_RM_FULL:
+				switch (effOpSz)
+				{
+					case Decode16Bits:
+						ps->usedPrefixes |= INST_PRE_OP_SIZE;
+						if (vrex & PREFIX_EX_B) {
+							ps->usedPrefixes |= INST_PRE_REX;
+							rm += EX_GPR_BASE;
+						}
+						size = 16;
+						rm += REGS16_BASE;
+					break;
+					case Decode32Bits:
+						ps->usedPrefixes |= INST_PRE_OP_SIZE;
+						if (vrex & PREFIX_EX_B) {
+							ps->usedPrefixes |= INST_PRE_REX;
+							rm += EX_GPR_BASE;
+						}
+						size = 32;
+						rm += REGS32_BASE;
+					break;
+					case Decode64Bits:
+						/* A fix for SMSW RAX which use the REX prefix. */
+						if (type == OT_RFULL_M16) ps->usedPrefixes |= INST_PRE_REX;
+						/* CALL NEAR/PUSH/POP defaults to 64 bits. --> INST_64BITS, REX isn't required, thus ignored anyways. */
+						if (instFlags & INST_PRE_REX) ps->usedPrefixes |= INST_PRE_REX;
+						/* Include REX if used for REX.B. */
+						if (vrex & PREFIX_EX_B) {
+							ps->usedPrefixes |= INST_PRE_REX;
+							rm += EX_GPR_BASE;
+						}
+						size = 64;
+						rm += REGS64_BASE;
+					break;
+				}
+			break;
+			case OT_R32_64_M8:
+			/* FALL THROUGH, decode 32 or 64 bits register. */
+			case OT_R32_64_M16:
+			/* FALL THROUGH, decode 32 or 64 bits register. */
+			case OT_RM32_64: /* Take care specifically in MOVNTI/MOVD/CVT's instructions, making it _REG64 with REX or if they are promoted. */
+				if (vrex & PREFIX_EX_B) {
+					ps->usedPrefixes |= INST_PRE_REX;
+					rm += EX_GPR_BASE;
+				}
+				/* Is it a promoted instruction? (only INST_64BITS is set and REX isn't required.) */
+				if ((ci->dt == Decode64Bits) && ((instFlags & (INST_64BITS | INST_PRE_REX)) == INST_64BITS)) {
+					size = 64;
+					rm += REGS64_BASE;
+					break;
+				}
+				/* Give a chance to REX.W. Because if it was a promoted instruction we don't care about REX.W anyways. */
+				if (vrex & PREFIX_EX_W) {
+					ps->usedPrefixes |= INST_PRE_REX;
+					size = 64;
+					rm += REGS64_BASE;
+				} else {
+					size = 32;
+					rm += REGS32_BASE;
+				}
+			break;
+			case OT_RM16_32: /* Used only with MOVZXD instruction to support 16 bits operand. */
+				if (vrex & PREFIX_EX_B) {
+					ps->usedPrefixes |= INST_PRE_REX;
+					rm += EX_GPR_BASE;
+				}
+				/* Is it 16 bits operand size? */
+				if (ps->decodedPrefixes & INST_PRE_OP_SIZE) {
+					ps->usedPrefixes |= INST_PRE_OP_SIZE;
+					size = 16;
+					rm += REGS16_BASE;
+				} else {
+					size = 32;
+					rm += REGS32_BASE;
+				}
+			break;
+			case OT_RM16:
+				if (vrex & PREFIX_EX_B) {
+					ps->usedPrefixes |= INST_PRE_REX;
+					rm += EX_GPR_BASE;
+				}
+				rm += REGS16_BASE;
+			break;
+			case OT_RM8:
+				if (ps->prefixExtType == PET_REX) {
+					ps->usedPrefixes |= INST_PRE_REX;
+					rm = operands_fix_8bit_rex_base(rm + ((vrex & PREFIX_EX_B) ? EX_GPR_BASE : 0));
+				} else rm += REGS8_BASE;
+			break;
+			case OT_MM32:
+			case OT_MM64:
+				/* MMX doesn't support extended registers. */
+				size = 64;
+				rm += MMXREGS_BASE;
+			break;
+
+			case OT_XMM16:
+			case OT_XMM32:
+			case OT_XMM64:
+			case OT_XMM128:
+				if (vrex & PREFIX_EX_B) {
+					ps->usedPrefixes |= INST_PRE_REX;
+					rm += EX_GPR_BASE;
+				}
+				size = 128;
+				rm += SSEREGS_BASE;
+			break;
+
+			case OT_RM32:
+			case OT_R32_M8:
+			case OT_R32_M16:
+				if (vrex & PREFIX_EX_B) {
+					ps->usedPrefixes |= INST_PRE_REX;
+					rm += EX_GPR_BASE;
+				}
+				size = 32;
+				rm += REGS32_BASE;
+			break;
+
+			case OT_YMM256:
+				if (vrex & PREFIX_EX_B) rm += EX_GPR_BASE;
+				rm += AVXREGS_BASE;
+			break;
+			case OT_YXMM64_256:
+			case OT_YXMM128_256:
+				if (vrex & PREFIX_EX_B) rm += EX_GPR_BASE;
+				if (vrex & PREFIX_EX_L) {
+					size = 256;
+					rm += AVXREGS_BASE;
+				} else {
+					size = 128;
+					rm += SSEREGS_BASE;
+				}
+			break;
+			case OT_WXMM32_64:
+			case OT_LXMM64_128:
+				if (vrex & PREFIX_EX_B) rm += EX_GPR_BASE;
+				size = 128;
+				rm += SSEREGS_BASE;
+			break;
+
+			case OT_WRM32_64:
+			case OT_REG32_64_M8:
+			case OT_REG32_64_M16:
+				if (vrex & PREFIX_EX_B) rm += EX_GPR_BASE;
+				if (vrex & PREFIX_EX_W) {
+					size = 64;
+					rm += REGS64_BASE;
+				} else {
+					size = 32;
+					rm += REGS32_BASE;
+				}
+			break;
+
+			default: return FALSE;
+		}
+		op->size = size;
+		op->index = (uint8_t)rm;
+		return TRUE;
+	}
+
+	/* Memory indirection decoding ahead:) */
+
+	ps->usedPrefixes |= INST_PRE_ADDR_SIZE;
+	if (lockableInstruction && (ps->decodedPrefixes & INST_PRE_LOCK)) *lockableInstruction = TRUE;
+
+	if (effAdrSz == Decode16Bits) {
+		/* Decoding according to Table 2-1. (16 bits) */
+		if ((mod == 0) && (rm == 6)) {
+			/* 6 is a special case - only 16 bits displacement. */
+			op->type = O_DISP;
+			di->dispSize = 16;
+			if (!read_stream_safe_sint(ci, (int64_t*)&di->disp, sizeof(int16_t))) return FALSE;
+		} else {
+			/*
+			 * Create the O_MEM for 16 bits indirection that requires 2 registers, E.G: [BS+SI].
+			 * or create O_SMEM for a single register indirection, E.G: [BP].
+			 */
+			static uint8_t MODS[] = {R_BX, R_BX, R_BP, R_BP, R_SI, R_DI, R_BP, R_BX};
+			static uint8_t MODS2[] = {R_SI, R_DI, R_SI, R_DI};
+			if (rm < 4) {
+				op->type = O_MEM;
+				di->base = MODS[rm];
+				op->index = MODS2[rm];
+			} else {
+				op->type = O_SMEM;
+				op->index = MODS[rm];
+			}
+
+			if (mod == 1) { /* 8 bits displacement + indirection */
+				di->dispSize = 8;
+				if (!read_stream_safe_sint(ci, (int64_t*)&di->disp, sizeof(int8_t))) return FALSE;
+			} else if (mod == 2) { /* 16 bits displacement + indirection */
+				di->dispSize = 16;
+				if (!read_stream_safe_sint(ci, (int64_t*)&di->disp, sizeof(int16_t))) return FALSE;
+			}
+		}
+
+		if ((rm == 2) || (rm == 3) || ((rm == 6) && (mod != 0))) {
+			/* BP's default segment is SS, so ignore it. */
+			prefixes_use_segment(INST_PRE_SS, ps, ci->dt, di);
+		} else {
+			/* Ignore default DS segment. */
+			prefixes_use_segment(INST_PRE_DS, ps, ci->dt, di);
+		}
+	} else { /* Decode32Bits or Decode64Bits! */
+		/* Remember that from a 32/64 bits ModR/M byte a SIB byte could follow! */
+		if ((mod == 0) && (rm == 5)) {
+
+			/* 5 is a special case - only 32 bits displacement, or RIP relative. */
+			di->dispSize = 32;
+			if (!read_stream_safe_sint(ci, (int64_t*)&di->disp, sizeof(int32_t))) return FALSE;
+
+			if (ci->dt == Decode64Bits) {
+				/* In 64 bits decoding mode depsite of the address size, a RIP-relative address it is. */
+				op->type = O_SMEM;
+				op->index = R_RIP;
+				di->flags |= FLAG_RIP_RELATIVE;
+			} else {
+				/* Absolute address: */
+				op->type = O_DISP;
+			}
+		} else {
+			if (rm == 4) {
+				/* 4 is a special case - SIB byte + disp8/32 follows! */
+				/* Read SIB byte. */
+				if (!read_stream_safe_uint(ci, &sib, sizeof(int8_t))) return FALSE;
+				operands_extract_sib(di, opNum, ps, effAdrSz, sib, mod);
+			} else {
+				op->type = O_SMEM;
+				if (vrex & PREFIX_EX_B) {
+					ps->usedPrefixes |= INST_PRE_REX;
+					rm += EX_GPR_BASE;
+				}
+
+				if (effAdrSz == Decode64Bits) op->index = (uint8_t)(REGS64_BASE + rm);
+				else op->index = (uint8_t)(REGS32_BASE + rm);
+			}
+
+			if (mod == 1) {
+				di->dispSize = 8;
+				if (!read_stream_safe_sint(ci, (int64_t*)&di->disp, sizeof(int8_t))) return FALSE;
+			} else if ((mod == 2) || ((sib & 7) == 5)) { /* If there is no BASE, read DISP32! */
+				di->dispSize = 32;
+				if (!read_stream_safe_sint(ci, (int64_t*)&di->disp, sizeof(int32_t))) return FALSE;
+			}
+		}
+
+		/* Get the base register. */
+		base = op->index;
+		if (di->base != R_NONE) base = di->base;
+		else if (di->scale >= 2) base = 0; /* If it's only an index but got scale, it's still DS. */
+		/* Default for EBP/ESP is SS segment. 64 bits mode ignores DS anyway. */
+		if ((base == R_EBP) || (base == R_ESP)) prefixes_use_segment(INST_PRE_SS, ps, ci->dt, di);
+		else prefixes_use_segment(INST_PRE_DS, ps, ci->dt, di);
+	}
+
+	return TRUE;
+}
+
+
+/*
+ * This function is reponsible to textually format a required operand according to its type.
+ * It is vital to understand that there are other operands than what the ModR/M byte specifies.
+
+ * Only by decoding the operands of an instruction which got a LOCK prefix, we could tell whether it may use the LOCK prefix.
+ * According to Intel, LOCK prefix must precede some specific instructions AND in their memory destination operand form (which means first operand).
+ * LOCK INC EAX, would generate an exception, but LOCK INC [EAX] is alright.
+ * Also LOCK ADD BX, [BP] would generate an exception.
+
+ * Return code:
+ * TRUE - continue parsing the instruction and its operands, everything went right 'till now.
+ * FALSE - not enough bytes, or invalid operands.
+ */
+
+int operands_extract(_CodeInfo* ci, _DInst* di, _InstInfo* ii,
+                     _iflags instFlags, _OpType type, _OperandNumberType opNum,
+                     unsigned int modrm, _PrefixState* ps, _DecodeType effOpSz,
+                     _DecodeType effAdrSz, int* lockableInstruction)
+{
+	int ret = 0;
+	unsigned int mod = 0, reg = 0, rm = 0, vexV = ps->vexV;
+	unsigned int vrex = ps->vrex, typeHandled = TRUE;
+	_Operand* op = &di->ops[opNum];
+
+	/* Used to indicate the size of the MEMORY INDIRECTION only. */
+	_OperandSizeType opSize = OPERAND_SIZE_NONE;
+
+	/*
+	 * ModRM bits:
+	 * |7-6-5--------3-2-0|
+	 * |MOD|REG/OPCODE|RM |
+	 * |------------------|
+	 */
+	mod = (modrm >> 6) & 3; /* Mode(register-indirection, disp8+reg+indirection, disp16+reg+indirection, general-purpose register) */
+	reg = (modrm >> 3) & 7; /* Register(could be part of the opcode itself or general-purpose register) */
+	rm = modrm & 7; /* Specifies which general-purpose register or disp+reg to use. */
+
+	/* -- Memory Indirection Operands (that cannot be a general purpose register) -- */
+	switch (type)
+	{
+		case OT_MEM64_128: /* Used only by CMPXCHG8/16B. */
+			/* Make a specific check when the type is OT_MEM64_128 since the lockable CMPXCHG8B uses this one... */
+			if (lockableInstruction && (ps->decodedPrefixes & INST_PRE_LOCK)) *lockableInstruction = TRUE;
+			if (effOpSz == Decode64Bits) {
+				ps->usedPrefixes |= INST_PRE_REX;
+				opSize = OPERAND_SIZE128;
+			} else opSize = OPERAND_SIZE64;
+		break;
+		case OT_MEM32: opSize = OPERAND_SIZE32; break;
+		case OT_MEM32_64:
+			/* Used by MOVNTI. Default size is 32bits, 64bits with REX. */
+			if (effOpSz == Decode64Bits) {
+				ps->usedPrefixes |= INST_PRE_REX;
+				opSize = OPERAND_SIZE64;
+			} else opSize = OPERAND_SIZE32;
+		break;
+		case OT_MEM64: opSize = OPERAND_SIZE64; break;
+		case OT_MEM128: opSize = OPERAND_SIZE128; break;
+		case OT_MEM16_FULL: /* The size indicates about the second item of the pair. */
+			switch (effOpSz)
+			{
+				case Decode16Bits:
+					ps->usedPrefixes |= INST_PRE_OP_SIZE;
+					opSize = OPERAND_SIZE16;
+				break;
+				case Decode32Bits:
+					ps->usedPrefixes |= INST_PRE_OP_SIZE;
+					opSize = OPERAND_SIZE32;
+				break;
+				case Decode64Bits:
+					/* Mark usage of REX only if it was required. */
+					if ((instFlags & (INST_64BITS | INST_PRE_REX)) == (INST_64BITS | INST_PRE_REX)) ps->usedPrefixes |= INST_PRE_REX;
+					opSize = OPERAND_SIZE64;
+				break;
+			}
+		break;
+		case OT_MEM16_3264: /* The size indicates about the second item of the pair. */
+			if (ci->dt == Decode64Bits) opSize = OPERAND_SIZE64;
+			else opSize = OPERAND_SIZE32;
+		break;
+		case OT_MEM_OPT:
+			/* Since the MEM is optional, only when mod != 3, then return true as if the operand was alright. */
+			if (mod == 0x3) return TRUE;
+		break;
+		case OT_FPUM16: opSize = OPERAND_SIZE16; break;
+		case OT_FPUM32: opSize = OPERAND_SIZE32; break;
+		case OT_FPUM64: opSize = OPERAND_SIZE64; break;
+		case OT_FPUM80: opSize = OPERAND_SIZE80; break;
+		case OT_LMEM128_256:
+			if (vrex & PREFIX_EX_L) opSize = OPERAND_SIZE256;
+			else opSize = OPERAND_SIZE128;
+		break;
+		case OT_MEM: /* Size is unknown, but still handled. */ break;
+		default: typeHandled = FALSE; break;
+	}
+	if (typeHandled) {
+		/* All of the above types can't use a general-purpose register (a MOD of 3)!. */
+		if (mod == 0x3) {
+			if (lockableInstruction) *lockableInstruction = FALSE;
+			return FALSE;
+		}
+		op->size = _OPSIZETOINT[opSize];
+		ret = operands_extract_modrm(ci, di, type, opNum, ps, effOpSz, effAdrSz, lockableInstruction, mod, rm, instFlags);
+		if ((op->type == O_REG) || (op->type == O_SMEM) || (op->type == O_MEM)) {
+			di->usedRegistersMask |= _REGISTERTORCLASS[op->index];
+		}
+		return ret;
+	}
+
+	/* -- Memory Indirection Operands (that can be a register) -- */
+	typeHandled = TRUE;
+	switch (type)
+	{
+		case OT_RM_FULL:
+			ps->usedPrefixes |= INST_PRE_OP_SIZE;
+			/* PUSH/JMP/CALL are automatically promoted to 64 bits! */
+			if (effOpSz == Decode32Bits) {
+				opSize = OPERAND_SIZE32;
+				break;
+			} else if (effOpSz == Decode64Bits) {
+				/* Mark usage of REX only if it was required. */
+				if ((instFlags & INST_64BITS) == 0) ps->usedPrefixes |= INST_PRE_REX;
+				opSize = OPERAND_SIZE64;
+				break;
+			}
+			/* FALL THROUGH BECAUSE dt==Decoded16Bits @-<----*/
+		case OT_RM16:
+			/* If we got here not from OT_RM16, then the prefix was used. */
+			if (type != OT_RM16) ps->usedPrefixes |= INST_PRE_OP_SIZE;
+			opSize = OPERAND_SIZE16;
+		break;
+		case OT_RM32_64:
+			/* The default size is 32, which can be 64 with a REX only. */
+			if (effOpSz == Decode64Bits) {
+				opSize = OPERAND_SIZE64;
+				/* Mark REX prefix as used if non-promoted instruction. */
+				if ((instFlags & (INST_64BITS | INST_PRE_REX)) == (INST_64BITS | INST_PRE_REX)) {
+					ps->usedPrefixes |= INST_PRE_REX;
+				}
+			} else opSize = OPERAND_SIZE32;
+		break;
+		case OT_RM16_32:
+			/* Ignore REX, it's either 32 or 16 bits RM. */
+			if (ps->decodedPrefixes & INST_PRE_OP_SIZE) {
+				ps->usedPrefixes |= INST_PRE_OP_SIZE;
+				/* Assume: We are in 64bits when we have this operand used. */
+				opSize = OPERAND_SIZE16;
+			} else opSize = OPERAND_SIZE32;
+		break;
+		case OT_WXMM32_64:
+		case OT_WRM32_64:
+			if (vrex & PREFIX_EX_W) opSize = OPERAND_SIZE64;
+			else opSize = OPERAND_SIZE32;
+		break;
+		case OT_YXMM64_256:
+			if (vrex & PREFIX_EX_L) opSize = OPERAND_SIZE256;
+			else opSize = OPERAND_SIZE64;
+		break;
+		case OT_YXMM128_256:
+			if (vrex & PREFIX_EX_L) opSize = OPERAND_SIZE256;
+			else opSize = OPERAND_SIZE128;
+		break;
+		case OT_LXMM64_128:
+			if (vrex & PREFIX_EX_L) opSize = OPERAND_SIZE128;
+			else opSize = OPERAND_SIZE64;
+		break;
+		case OT_RFULL_M16:
+			ps->usedPrefixes |= INST_PRE_OP_SIZE;
+			opSize = OPERAND_SIZE16;
+		break;
+
+		case OT_RM8:
+		case OT_R32_M8:
+		case OT_R32_64_M8:
+		case OT_REG32_64_M8:
+			opSize = OPERAND_SIZE8;
+		break;
+
+		case OT_XMM16:
+		case OT_R32_M16:
+		case OT_R32_64_M16:
+		case OT_REG32_64_M16:
+			opSize = OPERAND_SIZE16;
+		break;
+
+		case OT_RM32:
+		case OT_MM32:
+		case OT_XMM32:
+			opSize = OPERAND_SIZE32;
+		break;
+
+		case OT_MM64:
+		case OT_XMM64:
+			opSize = OPERAND_SIZE64;
+		break;
+
+		case OT_XMM128: opSize = OPERAND_SIZE128; break;
+		case OT_YMM256: opSize = OPERAND_SIZE256; break;
+		default: typeHandled = FALSE; break;
+	}
+	if (typeHandled) {
+		/* Fill size of memory dereference for operand. */
+		op->size = _OPSIZETOINT[opSize];
+		ret = operands_extract_modrm(ci, di, type, opNum, ps, effOpSz, effAdrSz, lockableInstruction, mod, rm, instFlags);
+		if ((op->type == O_REG) || (op->type == O_SMEM) || (op->type == O_MEM)) {
+			di->usedRegistersMask |= _REGISTERTORCLASS[op->index];
+		}
+		return ret;
+	}
+
+	/* Simple operand type (no ModRM byte). */
+	switch (type)
+	{
+		case OT_IMM8:
+			operands_set_ts(op, O_IMM, 8);
+			if (!read_stream_safe_uint(ci, &di->imm.byte, sizeof(int8_t))) return FALSE;
+		break;
+		case OT_IMM_FULL: /* 16, 32 or 64, depends on prefixes. */
+			if (effOpSz == Decode16Bits) {
+				ps->usedPrefixes |= INST_PRE_OP_SIZE;
+				/* FALL THROUGH */
+		case OT_IMM16: /* Force 16 bits imm. */
+			operands_set_ts(op, O_IMM, 16);
+			if (!read_stream_safe_uint(ci, &di->imm.word, sizeof(int16_t))) return FALSE;
+		break;
+			/*
+			 * Extension: MOV imm64, requires REX.
+			 * Make sure it needs the REX.
+			 * REX must be present because op size function takes it into consideration.
+			 */
+			} else if ((effOpSz == Decode64Bits) &&
+				        ((instFlags & (INST_64BITS | INST_PRE_REX)) == (INST_64BITS | INST_PRE_REX))) {
+				ps->usedPrefixes |= INST_PRE_REX;
+
+				operands_set_ts(op, O_IMM, 64);
+				if (!read_stream_safe_uint(ci, &di->imm.qword, sizeof(int64_t))) return FALSE;
+				break;
+			} else ps->usedPrefixes |= INST_PRE_OP_SIZE;
+			/* FALL THROUGH BECAUSE dt==Decoded32Bits @-<----*/
+		case OT_IMM32:
+			op->type = O_IMM;
+			if (ci->dt == Decode64Bits) {
+				/*
+				 * Imm32 is sign extended to 64 bits!
+				 * Originally the op size was 64, but later was changed to reflect real size of imm.
+				 */
+				op->size = 32;
+				/* Use this as an indicator that it should be signed extended. */
+				di->flags |= FLAG_IMM_SIGNED;
+				if (!read_stream_safe_sint(ci, &di->imm.sqword, sizeof(int32_t))) return FALSE;
+			} else {
+				op->size = 32;
+				if (!read_stream_safe_uint(ci, &di->imm.dword, sizeof(int32_t))) return FALSE;
+			}
+		break;
+		case OT_SEIMM8: /* Sign extended immediate. */
+			/*
+			 * PUSH SEIMM8 can be prefixed by operand size:
+			 * Input stream: 66, 6a, 55
+			 * 64bits DT: push small 55
+			 * 32bits DT: push small 55
+			 * 16bits DT: push large 55
+			 * small/large indicates the size of the eSP pointer advancement.
+			 * Check the instFlags (ii->flags) if it can be operand-size-prefixed and if the prefix exists.
+			 */
+			op->type = O_IMM;
+			if ((instFlags & INST_PRE_OP_SIZE) && (ps->decodedPrefixes & INST_PRE_OP_SIZE)) {
+				ps->usedPrefixes |= INST_PRE_OP_SIZE;
+				switch (ci->dt)
+				{
+					case Decode16Bits: op->size = 32; break;
+					case Decode32Bits:
+					case Decode64Bits:
+						op->size = 16;
+					break;
+				}
+			} else op->size = 8;
+			di->flags |= FLAG_IMM_SIGNED;
+			if (!read_stream_safe_sint(ci, &di->imm.sqword, sizeof(int8_t))) return FALSE;
+		break;
+		case OT_IMM16_1:
+			operands_set_ts(op, O_IMM1, 16);
+			if (!read_stream_safe_uint(ci, &di->imm.ex.i1, sizeof(int16_t))) return FALSE;
+		break;
+		case OT_IMM8_1:
+			operands_set_ts(op, O_IMM1, 8);
+			if (!read_stream_safe_uint(ci, &di->imm.ex.i1, sizeof(int8_t))) return FALSE;
+		break;
+		case OT_IMM8_2:
+			operands_set_ts(op, O_IMM2, 8);
+			if (!read_stream_safe_uint(ci, &di->imm.ex.i2, sizeof(int8_t))) return FALSE;
+		break;
+		case OT_REG8:
+			operands_set_ts(op, O_REG, 8);
+			if (ps->prefixExtType) {
+				/*
+				 * If REX prefix is valid then we will have to use low bytes.
+				 * This is a PASSIVE behavior changer of REX prefix, it affects operands even if its value is 0x40 !
+				 */
+				ps->usedPrefixes |= INST_PRE_REX;
+				op->index = (uint8_t)operands_fix_8bit_rex_base(reg + ((vrex & PREFIX_EX_R) ? EX_GPR_BASE : 0));
+			} else op->index = (uint8_t)(REGS8_BASE + reg);
+		break;
+		case OT_REG16:
+			operands_set_tsi(op, O_REG, 16, REGS16_BASE + reg);
+		break;
+		case OT_REG_FULL:
+			switch (effOpSz)
+			{
+				case Decode16Bits:
+					ps->usedPrefixes |= INST_PRE_OP_SIZE;
+					if (vrex & PREFIX_EX_R) {
+						ps->usedPrefixes |= INST_PRE_REX;
+						reg += EX_GPR_BASE;
+					}
+					operands_set_tsi(op, O_REG, 16, REGS16_BASE + reg);
+				break;
+				case Decode32Bits:
+					if (vrex & PREFIX_EX_R) {
+						ps->usedPrefixes |= INST_PRE_REX;
+						reg += EX_GPR_BASE;
+					} else ps->usedPrefixes |= INST_PRE_OP_SIZE;
+					operands_set_tsi(op, O_REG, 32, REGS32_BASE + reg);
+				break;
+				case Decode64Bits: /* rex must be presented. */
+					ps->usedPrefixes |= INST_PRE_REX;
+					operands_set_tsi(op, O_REG, 64, REGS64_BASE + reg + ((vrex & PREFIX_EX_R) ? EX_GPR_BASE : 0));
+				break;
+			}
+		break;
+		case OT_REG32:
+			if (vrex & PREFIX_EX_R) {
+				ps->usedPrefixes |= INST_PRE_REX;
+				reg += EX_GPR_BASE;
+			}
+			operands_set_tsi(op, O_REG, 32, REGS32_BASE + reg);
+		break;
+		case OT_REG32_64: /* Handle CVT's, MOVxX and MOVNTI instructions which could be extended to 64 bits registers with REX. */
+			if (vrex & PREFIX_EX_R) {
+				ps->usedPrefixes |= INST_PRE_REX;
+				reg += EX_GPR_BASE;
+			}
+
+			/* Is it a promoted instruction? (only INST_64BITS is set and REX isn't required.) */
+			if ((ci->dt == Decode64Bits) && ((instFlags & (INST_64BITS | INST_PRE_REX)) == INST_64BITS)) {
+				operands_set_tsi(op, O_REG, 64, REGS64_BASE + reg);
+				break;
+			}
+			/* Give a chance to REX.W. Because if it was a promoted instruction we don't care about REX.W anyways. */
+			if (vrex & PREFIX_EX_W) {
+				ps->usedPrefixes |= INST_PRE_REX;
+				operands_set_tsi(op, O_REG, 64, REGS64_BASE + reg);
+			} else operands_set_tsi(op, O_REG, 32, REGS32_BASE + reg);
+		break;
+		case OT_FREG32_64_RM: /* Force decoding mode. Used for MOV CR(n)/DR(n) which defaults to 64 bits operand size in 64 bits. */
+			if (vrex & PREFIX_EX_B) {
+				ps->usedPrefixes |= INST_PRE_REX;
+				rm += EX_GPR_BASE;
+			}
+
+			if (ci->dt == Decode64Bits) operands_set_tsi(op, O_REG, 64, REGS64_BASE + rm);
+			else operands_set_tsi(op, O_REG, 32, REGS32_BASE + rm);
+		break;
+		case OT_MM: /* MMX register */
+			operands_set_tsi(op, O_REG, 64, MMXREGS_BASE + reg);
+		break;
+		case OT_MM_RM: /* MMX register, this time from the RM field */
+			operands_set_tsi(op, O_REG, 64, MMXREGS_BASE + rm);
+		break;
+		case OT_REGXMM0: /* Implicit XMM0 operand. */
+			reg = 0;
+			vrex = 0;
+		/* FALL THROUGH */
+		case OT_XMM: /* SSE register */
+			if (vrex & PREFIX_EX_R) {
+				ps->usedPrefixes |= INST_PRE_REX;
+				reg += EX_GPR_BASE;
+			}
+			operands_set_tsi(op, O_REG, 128, SSEREGS_BASE + reg);
+		break;
+		case OT_XMM_RM: /* SSE register, this time from the RM field */
+			if (vrex & PREFIX_EX_B) {
+				ps->usedPrefixes |= INST_PRE_REX;
+				rm += EX_GPR_BASE;
+			}
+			operands_set_tsi(op, O_REG, 128, SSEREGS_BASE + rm);
+		break;
+		case OT_CREG:
+			/*
+			 * Don't parse if the reg exceeds the bounds of the array.
+			 * Most of the CR's are not implemented, so if there's no matching string, the operand is invalid.
+			 */
+			if (vrex & PREFIX_EX_R) {
+				ps->usedPrefixes |= INST_PRE_REX;
+				reg += EX_GPR_BASE;
+			} else if ((ci->dt == Decode32Bits) && (ps->decodedPrefixes & INST_PRE_LOCK)) {
+				/*
+				 * NOTE: In 32 bits decoding mode,
+				 * if the lock prefix is set before MOV CR(n) it will become the 4th bit of the REG field like REX.R in 64 bits.
+				 */
+				reg += EX_GPR_BASE;
+				ps->usedPrefixes |= INST_PRE_LOCK;
+			}
+			/* Ignore some registers which do not exist. */
+			if ((reg >= CREGS_MAX) || (reg == 1) || ((reg >= 5) && (reg <= 7))) return FALSE;
+
+			op->type = O_REG;
+			if (ci->dt == Decode64Bits) op->size = 64;
+			else op->size = 32;
+			op->index = (uint8_t)(CREGS_BASE + reg);
+		break;
+		case OT_DREG:
+			/*
+			 * In 64 bits there are 16 debug registers.
+			 * but accessing any of dr8-15 which aren't implemented will cause an #ud.
+			 */
+			if ((reg == 4) || (reg == 5) || (vrex & PREFIX_EX_R)) return FALSE;
+
+			op->type = O_REG;
+			if (ci->dt == Decode64Bits) op->size = 64;
+			else op->size = 32;
+			op->index = (uint8_t)(DREGS_BASE + reg);
+		break;
+		case OT_SREG: /* Works with REG16 only! */
+			/* If lockableInstruction pointer is non-null we know it's the first operand. */
+			if (lockableInstruction && (reg == 1)) return FALSE; /* Can't MOV CS, <REG>. */
+			/*Don't parse if the reg exceeds the bounds of the array. */
+			if (reg <= SEG_REGS_MAX - 1) operands_set_tsi(op, O_REG, 16, SREGS_BASE + reg);
+			else return FALSE;
+		break;
+		case OT_SEG:
+			op->type = O_REG;
+			/* Size of reg is always 16, it's up to caller to zero extend it to operand size. */
+			op->size = 16;
+			ps->usedPrefixes |= INST_PRE_OP_SIZE;
+			/*
+			 * Extract the SEG from ii->flags this time!!!
+			 * Check whether an operand size prefix is used.
+			 */
+			switch (instFlags & INST_PRE_SEGOVRD_MASK)
+			{
+				case INST_PRE_ES: op->index = R_ES; break;
+				case INST_PRE_CS: op->index = R_CS; break;
+				case INST_PRE_SS: op->index = R_SS; break;
+				case INST_PRE_DS: op->index = R_DS; break;
+				case INST_PRE_FS: op->index = R_FS; break;
+				case INST_PRE_GS: op->index = R_GS; break;
+			}
+		break;
+		case OT_ACC8:
+			operands_set_tsi(op, O_REG, 8, R_AL);
+		break;
+		case OT_ACC16:
+			operands_set_tsi(op, O_REG, 16, R_AX);
+		break;
+		case OT_ACC_FULL_NOT64: /* No REX.W support for IN/OUT. */
+			vrex &= ~PREFIX_EX_W;
+		case OT_ACC_FULL:
+			if (effOpSz == Decode16Bits) {
+				ps->usedPrefixes |= INST_PRE_OP_SIZE;
+				operands_set_tsi(op, O_REG, 16, R_AX);
+			} else if (effOpSz == Decode32Bits) {
+				ps->usedPrefixes |= INST_PRE_OP_SIZE;
+				operands_set_tsi(op, O_REG, 32, R_EAX);
+			} else { /* Decode64Bits */
+				/* Only non-promoted instructions need REX in order to decode in 64 bits. */
+				/* MEM-OFFSET MOV's are NOT automatically promoted to 64 bits. */
+				if (~instFlags & INST_64BITS) {
+					ps->usedPrefixes |= INST_PRE_REX;
+				}
+				operands_set_tsi(op, O_REG, 64, R_RAX);
+			}
+		break;
+		case OT_PTR16_FULL:
+			/* ptr16:full - full is size of operand size to read, therefore Operand Size Prefix affects this. So we need to handle it. */
+			if (effOpSz == Decode16Bits) {
+				ps->usedPrefixes |= INST_PRE_OP_SIZE;
+				ci->codeLen -= sizeof(int16_t)*2;
+				if (ci->codeLen < 0) return FALSE;
+
+				operands_set_ts(op, O_PTR, 16);
+				di->imm.ptr.off = RUSHORT(ci->code); /* Read offset first. */
+				di->imm.ptr.seg = RUSHORT((ci->code + sizeof(int16_t))); /* And read segment. */
+
+				ci->code += sizeof(int16_t)*2;
+			} else { /* Decode32Bits, for Decode64Bits this instruction is invalid. */
+				ps->usedPrefixes |= INST_PRE_OP_SIZE;
+				ci->codeLen -= sizeof(int32_t) + sizeof(int16_t);
+				if (ci->codeLen < 0) return FALSE;
+
+				operands_set_ts(op, O_PTR, 32);
+				di->imm.ptr.off = RULONG(ci->code); /* Read 32bits offset this time. */
+				di->imm.ptr.seg = RUSHORT((ci->code + sizeof(int32_t))); /* And read segment, 16 bits. */
+				
+				ci->code += sizeof(int32_t) + sizeof(int16_t);
+			}
+		break;
+		case OT_RELCB:
+		case OT_RELC_FULL:
+
+			if (type == OT_RELCB) {
+				operands_set_ts(op, O_PC, 8);
+				if (!read_stream_safe_sint(ci, &di->imm.sqword, sizeof(int8_t))) return FALSE;
+			} else { /* OT_RELC_FULL */
+
+				/* Yep, operand size prefix affects relc also.  */
+				ps->usedPrefixes |= INST_PRE_OP_SIZE;
+				if (effOpSz == Decode16Bits) {
+					operands_set_ts(op, O_PC, 16);
+					if (!read_stream_safe_sint(ci, &di->imm.sqword, sizeof(int16_t))) return FALSE;
+				} else { /* Decode32Bits or Decode64Bits = for now they are the same */
+					operands_set_ts(op, O_PC, 32);
+					if (!read_stream_safe_sint(ci, &di->imm.sqword, sizeof(int32_t))) return FALSE;
+				}
+			}
+
+			/* Support for hint, see if there's a segment override. */
+			if ((ii->opcodeId >= I_JO) && (ii->opcodeId <= I_JG)) {
+				if (ps->decodedPrefixes & INST_PRE_CS) {
+					ps->usedPrefixes |= INST_PRE_CS;
+					di->flags |= FLAG_HINT_NOT_TAKEN;
+				} else if (ps->decodedPrefixes & INST_PRE_DS) {
+					ps->usedPrefixes |= INST_PRE_DS;
+					di->flags |= FLAG_HINT_TAKEN;
+				}
+			}
+		break;
+		case OT_MOFFS8:
+			op->size = 8;
+			/* FALL THROUGH, size won't be changed. */
+		case OT_MOFFS_FULL:
+			op->type = O_DISP;
+			if (op->size == 0) {
+				/* Calculate size of operand (same as ACC size). */
+				switch (effOpSz)
+				{
+					case Decode16Bits: op->size = 16; break;
+					case Decode32Bits: op->size = 32; break;
+					case Decode64Bits: op->size = 64; break;
+				}
+			}
+
+			prefixes_use_segment(INST_PRE_DS, ps, ci->dt, di);
+
+			/*
+			 * Just a pointer to a BYTE, WORD, DWORD, QWORD. Works only with ACC8/16/32/64 respectively. 
+			 * MOV [0x1234], AL ; MOV AX, [0x1234] ; MOV EAX, [0x1234], note that R/E/AX will be chosen by OT_ACC_FULL.
+			 */
+			if (effAdrSz == Decode16Bits) {
+				ps->usedPrefixes |= INST_PRE_ADDR_SIZE;
+
+				di->dispSize = 16;
+				if (!read_stream_safe_uint(ci, &di->disp, sizeof(int16_t))) return FALSE;
+			} else if (effAdrSz == Decode32Bits) {
+				ps->usedPrefixes |= INST_PRE_ADDR_SIZE;
+
+				di->dispSize = 32;
+				if (!read_stream_safe_uint(ci, &di->disp, sizeof(int32_t))) return FALSE;
+			} else { /* Decode64Bits */
+				di->dispSize = 64;
+				if (!read_stream_safe_uint(ci, &di->disp, sizeof(int64_t))) return FALSE;
+			}
+		break;
+		case OT_CONST1:
+			operands_set_ts(op, O_IMM, 8);
+			di->imm.byte = 1;
+		break;
+		case OT_REGCL:
+			operands_set_tsi(op, O_REG, 8, R_CL);
+		break;
+
+		case OT_FPU_SI:
+			/* Low 3 bits specify the REG, similar to the MODR/M byte reg. */
+			operands_set_tsi(op, O_REG, 32, FPUREGS_BASE + (*(ci->code-1) & 7));
+		break;
+		case OT_FPU_SSI:
+			operands_set_tsi(op, O_REG, 32, R_ST0);
+			operands_set_tsi(op + 1, O_REG, 32, FPUREGS_BASE + (*(ci->code-1) & 7));
+		break;
+		case OT_FPU_SIS:
+			operands_set_tsi(op, O_REG, 32, FPUREGS_BASE + (*(ci->code-1) & 7));
+			operands_set_tsi(op + 1, O_REG, 32, R_ST0);
+		break;
+
+		/*
+		 * Special treatment for Instructions-Block:
+		 * INC/DEC (only 16/32 bits) /PUSH/POP/XCHG instructions, which get their REG from their own binary code.
+
+		 * Notice these instructions are 1 or 2 byte long,
+		 * code points after the byte which represents the instruction itself,
+		 * thus, even if the instructions are 2 bytes long it will read its last byte which contains the REG info.
+		 */
+		case OT_IB_RB:
+			/* Low 3 bits specify the REG, similar to the MODR/M byte reg. */
+			operands_set_ts(op, O_REG, 8);
+			reg = *(ci->code-1) & 7;
+			if (vrex & PREFIX_EX_B) {
+				ps->usedPrefixes |= INST_PRE_REX;
+				op->index = (uint8_t)operands_fix_8bit_rex_base(reg + EX_GPR_BASE);
+			} else if (ps->prefixExtType == PET_REX) {
+				ps->usedPrefixes |= INST_PRE_REX;
+				op->index = (uint8_t)operands_fix_8bit_rex_base(reg);
+			} else op->index = (uint8_t)(REGS8_BASE + reg);
+		break;
+		case OT_IB_R_FULL:
+			reg = *(ci->code-1) & 7;
+			switch (effOpSz)
+			{
+				case Decode16Bits:
+					ps->usedPrefixes |= INST_PRE_OP_SIZE;
+					if (vrex & PREFIX_EX_B) {
+						ps->usedPrefixes |= INST_PRE_REX;
+						reg += EX_GPR_BASE;
+					}
+					operands_set_tsi(op, O_REG, 16, REGS16_BASE + reg);
+				break;
+				case Decode32Bits:
+					if (vrex & PREFIX_EX_B) {
+						ps->usedPrefixes |= INST_PRE_REX;
+						reg += EX_GPR_BASE;
+					} else ps->usedPrefixes |= INST_PRE_OP_SIZE;
+					operands_set_tsi(op, O_REG, 32, REGS32_BASE + reg);
+				break;
+				case Decode64Bits:
+					/*
+					 * Automatically promoted instruction can drop REX prefix if not required.
+					 * PUSH/POP defaults to 64 bits. --> INST_64BITS
+					 * MOV imm64 / BSWAP requires REX.W to be 64 bits --> INST_64BITS | INST_PRE_REX
+					 */
+					if ((instFlags & INST_64BITS) && ((instFlags & INST_PRE_REX) == 0)) {
+						if (vrex & PREFIX_EX_B) {
+							ps->usedPrefixes |= INST_PRE_REX;
+							reg += EX_GPR_BASE;
+						}
+					} else {
+						ps->usedPrefixes |= INST_PRE_REX;
+						reg += (vrex & PREFIX_EX_B) ? EX_GPR_BASE : 0;
+					}
+					operands_set_tsi(op, O_REG, 64, REGS64_BASE + reg);
+				break;
+			}
+		break;
+
+		/*
+		 * Special treatment for repeatable instructions.
+
+		 * We want the following output:
+		 * If there's only the REP/NZ prefix, we won't output anything (All operands are implicit).
+		 * If there's an operand size prefix, we will change the suffix letter of the mnemonic, which specifies the size of operand to the required one.
+		 * If there's a segment override prefix, we will output the segment and the used index register (EDI/ESI).
+		 * If there's an address size prefix, we will output the (segment if needed and) the used and inverted index register (DI/SI).
+
+		 * Example:
+		 * :: Decoding in 16 bits mode! ::
+		 * AD ~ LODSW
+		 * 66 AD ~ LODSD
+		 * F3 AC ~ REP LODSB
+		 * F3 66 AD ~ REP LODSD
+		 * F3 3E AC ~ REP LODS BYTE DS:[SI]
+		 * F3 67 AD ~ REP LODS WORD [ESI]
+
+		 * The basic form of a repeatable instruction has its operands hidden and has a suffix letter
+		 * which implies on the size of operation being done.
+		 * Therefore, we cannot change the mnemonic here when we encounter another prefix and its not the decoder's responsibility to do so.
+		 * That's why the caller is responsible to add the suffix letter if no other prefixes are used.
+		 * And all we are doing here is formatting the operand correctly.
+		 */
+		case OT_REGI_ESI:
+			ps->usedPrefixes |= INST_PRE_ADDR_SIZE;
+
+			op->type = O_SMEM;
+
+			/* This might be a 16, 32 or 64 bits instruction, depends on the decoding mode. */
+			if (instFlags & INST_16BITS) {
+				ps->usedPrefixes |= INST_PRE_OP_SIZE;
+
+				if (effOpSz == Decode16Bits) op->size = 16;
+				else if ((effOpSz == Decode64Bits) && (instFlags & INST_64BITS)) {
+					ps->usedPrefixes |= INST_PRE_REX;
+					op->size = 64;
+				} else op->size = 32;
+			} else op->size = 8;
+
+			/*
+			 * Clear segment in case OT_REGI_EDI was parsed earlier,
+			 * DS can be overridden and therefore has precedence.
+			 */
+			di->segment = 0;
+			prefixes_use_segment(INST_PRE_DS, ps, ci->dt, di);
+
+			if (effAdrSz == Decode16Bits) op->index = R_SI;
+			else if (effAdrSz == Decode32Bits) op->index = R_ESI;
+			else op->index = R_RSI;
+		break;
+		case OT_REGI_EDI:
+			ps->usedPrefixes |= INST_PRE_ADDR_SIZE;
+
+			op->type = O_SMEM;
+
+			/* This might be a 16 or 32 bits instruction, depends on the decoding mode. */
+			if (instFlags & INST_16BITS) {
+				ps->usedPrefixes |= INST_PRE_OP_SIZE;
+
+				if (effOpSz == Decode16Bits) op->size = 16;
+				else if ((effOpSz == Decode64Bits) && (instFlags & INST_64BITS)) {
+					ps->usedPrefixes |= INST_PRE_REX;
+					op->size = 64;
+				} else op->size = 32;
+			} else op->size = 8;
+
+			/* Note: The [rDI] operand can't be prefixed by a segment override, therefore we don't set usedPrefixes. */
+			if ((opNum == ONT_1) && (ci->dt != Decode64Bits)) di->segment = R_ES | SEGMENT_DEFAULT; /* No ES in 64 bits mode. */
+
+			if (effAdrSz == Decode16Bits) op->index = R_DI;
+			else if (effAdrSz == Decode32Bits) op->index = R_EDI;
+			else op->index = R_RDI;
+		break;
+
+		/* Used for In/Out instructions varying forms. */
+		case OT_REGDX:
+			/* Simple single IN/OUT instruction. */
+			operands_set_tsi(op, O_REG, 16, R_DX);
+		break;
+
+		/* Used for INVLPGA instruction. */
+		case OT_REGECX:
+			operands_set_tsi(op, O_REG, 32, R_ECX);
+		break;
+		case OT_REGI_EBXAL:
+			/* XLAT BYTE [rBX + AL] */
+			ps->usedPrefixes |= INST_PRE_ADDR_SIZE;
+
+			prefixes_use_segment(INST_PRE_DS, ps, ci->dt, di);
+
+			/* Size of deref is always 8 for xlat. */
+			operands_set_tsi(op, O_MEM, 8, R_AL);
+
+			if (effAdrSz == Decode16Bits) di->base = R_BX;
+			else if (effAdrSz == Decode32Bits) di->base = R_EBX;
+			else {
+				ps->usedPrefixes |= INST_PRE_REX;
+				di->base = R_RBX;
+			}
+		break;
+		case OT_REGI_EAX:
+			/*
+			 * Implicit rAX as memory indirection operand. Used by AMD's SVM instructions.
+			 * Since this is a memory indirection, the default address size in 64bits decoding mode is 64.
+			 */
+
+			if (effAdrSz == Decode64Bits) operands_set_tsi(op, O_SMEM, 64, R_RAX);
+			else if (effAdrSz == Decode32Bits) {
+				ps->usedPrefixes |= INST_PRE_ADDR_SIZE;
+				operands_set_tsi(op, O_SMEM, 32, R_EAX);
+			} else {
+				ps->usedPrefixes |= INST_PRE_ADDR_SIZE;
+				operands_set_tsi(op, O_SMEM, 16, R_AX);
+			}
+		break;
+		case OT_VXMM:
+			operands_set_tsi(op, O_REG, 128, SSEREGS_BASE + vexV);
+		break;
+		case OT_XMM_IMM:
+			ci->codeLen -= sizeof(int8_t);
+			if (ci->codeLen < 0) return FALSE;
+
+			if (ci->dt == Decode32Bits) reg = (*ci->code >> 4) & 0x7;
+			else reg = (*ci->code >> 4) & 0xf;
+			operands_set_tsi(op, O_REG, 128, SSEREGS_BASE + reg);
+
+			ci->code += sizeof(int8_t);
+		break;
+		case OT_YXMM:
+			if (vrex & PREFIX_EX_R) reg += EX_GPR_BASE;
+			if (ps->vrex & PREFIX_EX_L) operands_set_tsi(op, O_REG, 256, AVXREGS_BASE + reg);
+			else operands_set_tsi(op, O_REG, 128, SSEREGS_BASE + reg);
+		break;
+		case OT_YXMM_IMM:
+			ci->codeLen -= sizeof(int8_t);
+			if (ci->codeLen < 0) return FALSE;
+
+			if (ci->dt == Decode32Bits) reg = (*ci->code >> 4) & 0x7;
+			else reg = (*ci->code >> 4) & 0xf;
+
+			if (ps->vrex & PREFIX_EX_L) operands_set_tsi(op, O_REG, 256, AVXREGS_BASE + reg);
+			else operands_set_tsi(op, O_REG, 128, SSEREGS_BASE + reg);
+
+			ci->code += sizeof(int8_t);
+		break;
+		case OT_YMM:
+			if (vrex & PREFIX_EX_R) reg += EX_GPR_BASE;
+			operands_set_tsi(op, O_REG, 256, AVXREGS_BASE + reg);
+		break;
+		case OT_VYMM:
+			operands_set_tsi(op, O_REG, 256, AVXREGS_BASE + vexV);
+		break;
+		case OT_VYXMM:
+			if (ps->vrex & PREFIX_EX_L) operands_set_tsi(op, O_REG, 256, AVXREGS_BASE + vexV);
+			else operands_set_tsi(op, O_REG, 128, SSEREGS_BASE + vexV); 
+		break;
+		case OT_WREG32_64:
+			if (vrex & PREFIX_EX_R) reg += EX_GPR_BASE;
+			if (ps->vrex & PREFIX_EX_W) operands_set_tsi(op, O_REG, 64, REGS64_BASE + reg);
+			else operands_set_tsi(op, O_REG, 32, REGS32_BASE + reg);
+		break;
+		default: return FALSE;
+	}
+
+	if ((op->type == O_REG) || (op->type == O_SMEM) || (op->type == O_MEM)) {
+		di->usedRegistersMask |= _REGISTERTORCLASS[op->index];
+	}
+
+	return TRUE;
+}