badline 0.9.0 → 0.10.1

data/lib/badline/via/shift_register.rb

@@ -13,14 +13,20 @@ module Badline
     # modes 3 and 7 off whatever drives CB1 from outside.
     #
     # Under its own clock the register drives CB1, idling high. Reading or
-    # writing the data register starts a byte: CB1 falls on the first clock
-    # tick after the access and rises on the second, and so on, so a byte is
-    # eight pulses over sixteen ticks. The interrupt flag is set on the tick
-    # that raises CB1 over the eighth bit, and CB1 then stays high until the
-    # next access. A tick is a φ2 cycle in modes 2 and 6, which makes a byte
-    # sixteen cycles, and a timer 2 low byte underflow in modes 1, 4 and 5,
-    # which makes it sixteen underflows. Mode 4 never stops and never
-    # interrupts: its counter is disabled, and the byte goes round and round.
+    # writing the data register starts a byte, but only while the register
+    # is idle and enabled: an access in mode 0, or one before the eighth bit
+    # is in, leaves the count alone. CB1 falls on the first clock tick of
+    # the byte and rises on the second, and so on, so a byte is eight pulses
+    # over sixteen ticks. The interrupt flag is set on the tick that raises
+    # CB1 over the eighth bit, and CB1 then stays high until the next
+    # access.
+    #
+    # In modes 2 and 6 a tick is a φ2 cycle, from the second cycle after
+    # the access on, which makes a byte sixteen cycles. In modes 1, 4 and 5
+    # it comes two cycles after each timer 2 low byte underflow, on the
+    # cycle after the low byte reloads, which makes a byte sixteen
+    # underflows. Mode 4 never stops and never interrupts: its counter is
+    # disabled, and the byte goes round and round.
     #
     # Under an external clock the register shifts on every CB1 edge, access
     # or not. The access only arms the counter: the flag is set on the eighth
@@ -43,6 +49,10 @@ module Badline
         @data = 0x00
         # Bits still to count before the flag, zero when the counter is idle.
         @bits = 0
+        # The clock's last two cycles, newest in bit 0: timer 2 low byte
+        # underflows in modes 1, 4 and 5, and whether the byte has started
+        # in modes 2 and 6.
+        @delay = 0
         @clock = true
         @cb2 = true
         # Nothing drives CB2 from outside, so it floats high.
@@ -57,10 +67,13 @@ module Badline
         @data = value & 0xff
       end
 
-      # Every read or write of the data register (re)starts the count of
-      # eight bits.
+      # A read or write of the data register, which starts a byte if the
+      # register is idle and enabled.
       def access!
+        return if @mode == DISABLED || @bits.nonzero?
+
         @bits = 8
+        @delay = 0 if @mode == IN_PHI2 || @mode == OUT_PHI2
       end
 
       # Whether the register is counting bits off its own clock, which
@@ -68,20 +81,21 @@ module Badline
       def clocking? = @bits.nonzero? && internal_clock?
 
       def save_state(out)
-        out.int(@mode).int(@data).int(@bits).boolean(@clock).boolean(@cb2).boolean(@cb2_input)
+        out.int(@mode).int(@data).int(@bits).int(@delay).boolean(@clock).boolean(@cb2).boolean(@cb2_input)
       end
 
       def load_state(input)
         @mode = input.int
         @data = input.int
         @bits = input.int
+        @delay = input.schema > 4 ? input.int : 0
         @clock = input.boolean?
         @cb2 = input.boolean?
         @cb2_input = input.boolean?
       end
 
       # Everything the register holds, for comparing it at two points.
-      def state = [@mode, @data, @bits, @clock, @cb2, @cb2_input]
+      def state = [@mode, @data, @bits, @delay, @clock, @cb2, @cb2_input]
 
       # The CB1 level the register drives, or nil when CB1 is an input.
       def cb1_output
@@ -96,11 +110,9 @@ module Badline
       # Clocked once per φ2 cycle, with whether timer 2's low byte underflowed
       # on it. Returns true on the cycle that sets the interrupt flag.
       def cycle!(t2_low_underflow)
-        return false if @bits.zero?
-
         case @mode
-        when IN_PHI2, OUT_PHI2 then tick
-        when IN_T2, OUT_T2, OUT_FREE_RUNNING then t2_low_underflow && tick
+        when IN_PHI2, OUT_PHI2 then @bits.nonzero? && phi2_tick
+        when IN_T2, OUT_T2, OUT_FREE_RUNNING then t2_tick(t2_low_underflow)
         else false
         end
       end
@@ -123,6 +135,21 @@ module Badline
         @mode != DISABLED && @mode != IN_EXTERNAL && @mode != OUT_EXTERNAL
       end
 
+      # A φ2 cycle of a byte: every one but the first ticks.
+      def phi2_tick
+        started = @delay.nonzero?
+        @delay = 1
+        started && tick
+      end
+
+      # Ticks on the underflow from two cycles back, while a byte is under
+      # way.
+      def t2_tick(underflow)
+        due = @delay.anybits?(2)
+        @delay = ((@delay << 1) & 2) | (underflow ? 1 : 0)
+        due && @bits.nonzero? && tick
+      end
+
       # One half period of the register's own clock: a falling edge puts a
       # bit out, and a rising one takes a bit in and counts it.
       def tick

data/lib/badline/vic/bank.rb

@@ -5,44 +5,81 @@ module Badline
     # The 16K window the VIC sees into RAM, selected by CIA2 $DD00, in the
     # bank a +256K picks for it. Character
     # ROM shadows $1000-$1FFF in banks 0 and 2.
+    #
+    # The machine's bus pushes in what the VIC sees through #connect,
+    # #map_character_rom and #map whenever it changes. Until then the bank
+    # has a CIA 2, RAM, colour RAM and character ROM of its own.
     class Bank
       include Addressable
 
       # The CIA2 port A bank bits are inverted: %11 selects bank 0.
       BANK_STARTS = [0xc000, 0x8000, 0x4000, 0x0000].freeze
 
-      attr_reader :address_bus
+      attr_reader :ram, :color_ram
 
       # The bank lines as #sample_lines last saw them.
       attr_accessor :lines
 
-      def initialize(address_bus = nil)
+      def initialize(vic)
         addressable_at(0x0000, length: 2**14)
-        @address_bus = address_bus || AddressBus.new
+        connect(cia2: CIA.new(start: 0xdd00), color_ram: ColorMemory.new(vic))
+        map_character_rom(ROM.load("character.rom", 0xd000))
+        @base = 0
+        @starts = BANK_STARTS
+        map(Memory.new([], length: 2**16, start: 0))
         @lines = 0b11
         @swapped = false
       end
 
+      # CIA 2, whose port A picks the bank, and the colour RAM, read from
+      # the address +color_base+ gives offset 0.
+      def connect(cia2:, color_ram:, color_base: 0xd800)
+        @cia2 = cia2
+        @color_ram = color_ram
+        @color_base = color_base
+      end
+
+      # The character ROM, read from the address +base+ gives offset 0. It
+      # shows in the banks whose low line is high, unless +shadow+ is false.
+      def map_character_rom(rom, base: 0xc000, shadow: true)
+        @character_rom = rom
+        @character_base = base
+        @shadow_mask = shadow ? 0b01 : 0b00
+      end
+
+      # The RAM the VIC's 64K starts at +base+ in, and the cartridge's
+      # Ultimax lines in each half of the cycle with the ROMH bank they
+      # show.
+      def map(ram, base: 0, phi1_ultimax: false, ultimax: false, romh: nil)
+        @ram = ram
+        unless base == @base
+          @base = base
+          @starts = BANK_STARTS.map { |start| base + start }.freeze
+        end
+        @phi1_ultimax = phi1_ultimax
+        @ultimax = ultimax
+        @romh = romh
+      end
+
       # On the 8565, a port A write that swaps the two bank lines, driving
       # one high as the other goes low, shows the VIC both lines low for the
       # cycle after it: every access in that cycle reads bank 3. A swap that
       # the DDR makes, releasing a line to float high, shows nothing.
       # Called once a cycle, ahead of the cycle's accesses.
       def sample_lines
-        cia2 = @address_bus.cia2
-        lines = cia2.port_a_lines & 0b11
-        @swapped = swap?(@lines, lines) && cia2.port_registers[2].allbits?(0b11)
+        lines = @cia2.port_a_lines & 0b11
+        @swapped = swap?(@lines, lines) && @cia2.port_registers[2].allbits?(0b11)
         @lines = lines
       end
 
       def peek(offset)
-        return ultimax_peek(offset) if @address_bus.phi1_ultimax
+        return ultimax_peek(offset) if @phi1_ultimax
 
         bits = bank_switch_register
-        if bits.allbits?(0b01) && (offset & 0xf000) == 0x1000
-          @address_bus.character_rom.peek(0xc000 + offset)
+        if (bits & @shadow_mask) == 0b01 && (offset & 0xf000) == 0x1000
+          @character_rom.peek(@character_base + offset)
         else
-          @address_bus.video_ram.peek(BANK_STARTS[bits] + offset)
+          @ram.peek(@starts[bits] + offset)
         end
       end
 
@@ -50,11 +87,11 @@ module Badline
       # memory configuration the CPU does in that half. No cartridge drives
       # Ultimax mode in the first half alone, so otherwise it reads as #peek.
       def peek_phi2(offset)
-        @address_bus.ultimax ? ultimax_peek(offset) : peek(offset)
+        @ultimax ? ultimax_peek(offset) : peek(offset)
       end
 
       def peek_color(offset)
-        address_bus.color_ram.nibble(0xd800 + offset)
+        @color_ram.nibble(@color_base + offset)
       end
 
       def poke(_addr, _value)
@@ -63,7 +100,7 @@ module Badline
 
       # True if the VIC reads the character ROM at this offset.
       def character_rom?(offset)
-        !@address_bus.phi1_ultimax && bank_switch_register.allbits?(0b01) && (offset & 0xf000) == 0x1000
+        !@phi1_ultimax && (bank_switch_register & @shadow_mask) == 0b01 && (offset & 0xf000) == 0x1000
       end
 
       def start
@@ -73,13 +110,14 @@ module Badline
       private
 
       # In Ultimax mode the cartridge ROMH replaces the character ROM
-      # shadow, visible at $3000-$3FFF of the window.
+      # shadow, visible at $3000-$3FFF of the window. The MAX is in
+      # Ultimax mode with no cartridge too.
       def ultimax_peek(offset)
-        romh = @address_bus.cartridge.romh
+        romh = @romh
         if romh && offset.allbits?(0x3000)
           romh.peek(0xe000 + (offset & 0x1fff))
         else
-          @address_bus.video_ram.peek(BANK_STARTS[bank_switch_register] + offset)
+          @ram.peek(@starts[bank_switch_register] + offset)
         end
       end
 
@@ -88,7 +126,7 @@ module Badline
       def bank_switch_register
         return 0 if @swapped
 
-        @address_bus.cia2.port_a_lines & 0b11
+        @cia2.port_a_lines & 0b11
       end
     end
   end

data/lib/badline/vic/registers.rb

@@ -69,7 +69,13 @@ module Badline
     #   $D02D: Sprite 6 color
     #   $D02E: Sprite 7 color
     #
-    # $D02F-$D03F: Not in use, always reads 0xff
+    # == VIC-IIe (8566 and 8564)
+    #
+    #   $D02F: Extra keyboard lines K0-K2 in bits 0-2, bits 3-7 read 1
+    #   $D030: FAST (2 MHz) in bit 0 and TEST in bit 1, bits 2-7 read 1
+    #
+    # $D02F-$D03F: Not in use on the 6569 and 8565, always reads 0xff,
+    # and $D031-$D03F on the VIC-IIe
     # $D040-$D3FF: Repeat $D0000 to $D03F every 64 bytes
     class Registers
       include IntegerHelper
@@ -77,10 +83,12 @@ module Badline
       # The raw register bytes, for the per-column reads on the hot path.
       attr_reader :bytes
 
-      # Every register powers on as zero, as in VICE.
-      def initialize
+      # Every register powers on as zero, as in VICE. A VIC-IIe reads
+      # $D02F and $D030 back as registers.
+      def initialize(iie: false)
         @bytes = Array.new(2**6, 0)
         @irq_line = false
+        @iie = iie
       end
 
       # True while any enabled latch bit is set in $D019/$D01A. Cached and
@@ -95,7 +103,9 @@ module Badline
         when 0x18 then @bytes[reg] | 0x01 # bit 0 unused, reads 1
         when 0x1a, 0x20..0x2e then @bytes[reg] | 0xf0
         when 0x1e, 0x1f then read_clear(reg) # collision registers clear on read
-        when 0x2f..0x3f then 0xff
+        when 0x2f then @iie ? @bytes[reg] | 0xf8 : 0xff
+        when 0x30 then @iie ? @bytes[reg] | 0xfc : 0xff
+        when 0x31..0x3f then 0xff
         else @bytes[reg]
         end
       end
@@ -134,6 +144,12 @@ module Badline
       def border = @bytes[0x20] & 0x0f
       def background(index = 0) = @bytes[0x21 + index] & 0x0f
 
+      # The VIC-IIe's $D02F and $D030 bits. The 6569 and 8565 drive no
+      # extra keyboard lines and run at 1 MHz.
+      def extra_keyboard_lines = @iie ? @bytes[0x2f] & 0x07 : 0x07
+      def fast? = @iie && @bytes[0x30].anybits?(0x01)
+      def test? = @iie && @bytes[0x30].anybits?(0x02)
+
       def raster_target = uint16(@bytes[0x12], (@bytes[0x11] & 0x80) >> 7)
 
       def latch_irq!(bit)

data/lib/badline/vic.rb

@@ -11,12 +11,37 @@ module Badline
     include Addressable
     include IntegerHelper
 
-    # The 6569 of the breadbin C64, and the HMOS 8565 of the C64C.
-    MODELS = %i[mos6569 mos8565].freeze
-
-    attr_reader :address_bus, :display, :width, :height, :vic_bank, :column,
+    # The 6569 of the breadbin C64, the HMOS 8565 of the C64C, and the
+    # C128's VIC-IIe, the 8566 (PAL) and 8564 (NTSC). The VIC-IIe draws as
+    # the 8565 and adds the $D02F and $D030 registers.
+    MODELS = %i[mos6569 mos8565 mos8566 mos8564].freeze
+
+    # The sixteen colours #display's palette indices stand for, as RGB.
+    PALETTE = [
+      0x000000, 0xffffff, 0x924a40, 0x84c5cc,
+      0x9351b6, 0x72b14b, 0x483aaa, 0xd5df7c,
+      0x675200, 0xc33d00, 0xc18178, 0x606060,
+      0x8a8a8a, 0xb3ec91, 0x867ade, 0xb3b3b3
+    ].freeze
+
+    # The sixteen colours' luminances, out of 32, as Philip Timmermann
+    # (Pepto) measured them on the 6569.
+    LUMINANCES = [0, 32, 10, 20, 12, 16, 8, 24, 12, 8, 16, 10, 15, 24, 15, 20].freeze
+
+    # The sixteen colours on a green monochrome monitor, which shows only
+    # their luminance, as the PET 64's does.
+    GREEN_PALETTE = LUMINANCES.map do |luminance|
+      green = luminance * 255 / 32
+      ((green / 4) << 16) | (green << 8) | (green / 4)
+    end.freeze
+
+    attr_reader :display, :width, :height, :vic_bank, :column,
                 :rasterline, :dirty_lines, :model, :region
 
+    # The RGB colours #display's palette indices stand for: PALETTE, or
+    # GREEN_PALETTE on a monochrome monitor.
+    attr_accessor :palette
+
     # The parts a VICE snapshot reads and sets.
     attr_reader :registers, :display_state, :sequencer, :sprites, :character_buffer, :color_buffer,
                 :fetch_d011
@@ -76,19 +101,21 @@ module Badline
     SPRITE_BA_FIRST = 54
     SPRITE_BA_LENGTH = 5
 
-    def initialize(address_bus = nil, debug: false, model: :mos6569, region: Region::PAL)
+    def initialize(debug: false, model: :mos6569, region: Region::PAL)
       raise ArgumentError, "unknown VIC-II model #{model}" unless MODELS.include?(model)
 
       addressable_at(0xd000, length: 2**10)
       @model = model
+      @iie = %i[mos8566 mos8564].include?(model)
+      @core = model == :mos6569 ? :mos6569 : :mos8565
       @region = region
-      @lightpen_extra = model == :mos8565 ? 1 : 2
-      @grey_dots = model == :mos8565
-      @delayed_fetch = model == :mos8565
-      @dma_delay_idle = model == :mos6569
-      @bank_swaps = model == :mos8565
-      @address_bus = address_bus || AddressBus.new
-      @vic_bank = VIC::Bank.new(@address_bus)
+      @palette = PALETTE
+      @lightpen_extra = @core == :mos8565 ? 1 : 2
+      @grey_dots = @core == :mos8565
+      @delayed_fetch = @core == :mos8565
+      @dma_delay_idle = @core == :mos6569
+      @bank_swaps = @core == :mos8565
+      @vic_bank = VIC::Bank.new(self)
       @debug = debug
 
       @columns_per_line = region.cycles_per_line
@@ -114,12 +141,12 @@ module Badline
     # registers, the raster position and the fetch and sprite state it
     # starts with. The display keeps its buffers, cleared to black.
     def power_on!
-      @registers = VIC::Registers.new
+      @registers = VIC::Registers.new(iie: @iie)
       @register_bytes = @registers.bytes
       @display_state = VIC::DisplayState.new(@registers, @last_column)
-      @sequencer = VIC::Sequencer.new(@width, @registers, @vic_bank, model: @model, region: @region)
+      @sequencer = VIC::Sequencer.new(@width, @registers, @vic_bank, model: @core, region: @region)
       @sequencer.render = @render
-      @sprites = VIC::Sprites.new(@registers, @vic_bank, @width, model: @model, region: @region)
+      @sprites = VIC::Sprites.new(@registers, @vic_bank, @width, model: @core, region: @region)
       @display.fill(0)
       @lines.each { |line| line.fill(0) }
       @dirty_lines.fill(true)
@@ -222,6 +249,12 @@ module Badline
       @registers.irq_line?
     end
 
+    # The VIC-IIe's $D02F lines K0-K2 and $D030 bits, for the machine to
+    # read. The 6569 and 8565 give 7, false and false.
+    def extra_keyboard_lines = @registers.extra_keyboard_lines
+    def fast? = @registers.fast?
+    def test? = @registers.test?
+
     def peek(addr)
       i = offset_of(addr) % (2**6)
       case i

data/lib/badline/vic20/attachments.rb

@@ -0,0 +1,103 @@
+# frozen_string_literal: true
+
+module Badline
+  class Vic20
+    # What plugs into the VIC-20 besides its chips: cartridge ROM in the
+    # expansion blocks, the disk device 8 serves through the KERNAL traps,
+    # and a true 1541 on the serial bus.
+    module Attachments
+      # The cycle by which a 1541 switched on with the machine has run its
+      # DOS's reset, the RAM test and the ROM checksum, and waits on the
+      # bus, with a margin: about 1.1 million of the VIC-20's cycles.
+      DRIVE_BOOT_CYCLES = 1_300_000
+
+      # Where BASIC's program starts, from TXTTAB, which the KERNAL sets at
+      # boot by the RAM it finds: $1001 unexpanded, $0401 with the 3K
+      # expansion and $1201 with 8K or more in BLK1.
+      def basic_start = ram.peek16(0x2b)
+
+      # Puts a cartridge's ROM chips, each a CRTFile::Chip with its address
+      # and bytes, into their blocks, and switches the machine off and on,
+      # as a cartridge goes in with the power off. The KERNAL then starts
+      # the cartridge in BLK5 that signs itself with A0CBM.
+      def attach_cartridge(chips)
+        chips.each { |chip| @bus.map_rom(chip.address, chip.data) }
+        power_cycle!
+      end
+
+      # Puts the storage in device 8. Mounting again swaps the disk at any
+      # point while the machine runs: the drive keeps its RAM and its
+      # status.
+      def mount(storage)
+        return @drive.insert(storage) if @drive
+
+        @drive = KernalTrap::Drive.new(storage)
+        layout = KernalTrap::VIC20_LAYOUT
+        load_trap = KernalTrap::Load.new(cpu:, bus:, layout:, drive: @drive)
+        cpu.install_trap(layout.load) { load_trap.call }
+        @serial_trap = KernalTrap::Serial.new(cpu:, bus:, layout:, drive: @drive, device: serial_trap_device).install
+        save_trap = @save_trap = KernalTrap::Save.new(cpu:, bus:, layout:, drive: @drive)
+        cpu.install_trap(layout.save) { save_trap.call }
+      end
+
+      # Takes device 8's mounted storage out, and with it the LOAD, SAVE and
+      # serial traps, so the KERNAL's routines go out over the serial bus.
+      # Mounting again starts a new drive, with its RAM cleared.
+      def unmount
+        return unless @drive
+
+        cpu.remove_trap(KernalTrap::VIC20_LAYOUT.load)
+        cpu.remove_trap(KernalTrap::VIC20_LAYOUT.save)
+        @serial_trap.device = nil
+        @serial_trap = nil
+        @save_trap = nil
+        @drive = nil
+      end
+
+      # Whether device 8 serves a disk or directory through the traps.
+      def mounted? = !@drive.nil?
+
+      # Plugs in a Drive1541, which then runs alongside the VIC-20 on its own
+      # clock and talks to it over the serial bus. The serial traps stop
+      # answering the drive's device number, so the KERNAL's TALK, LISTEN
+      # and byte transfers reach the drive. The LOAD and SAVE traps stay,
+      # and still serve a mounted image.
+      #
+      # A drive that powers on with the machine takes longer to boot than
+      # the KERNAL, and doesn't answer the bus until it has, so the
+      # machine's on_init handlers wait for it too.
+      def attach_drive1541(drive)
+        @init_threshold = [@init_threshold, DRIVE_BOOT_CYCLES].max if @cycles < @init_threshold
+        @iec_bus.detach(@drive1541) if @drive1541
+        drive.host_clock_hz = timing.clock_hz
+        @drive1541 = drive
+        drive.connect(@iec_bus)
+        @serial_trap&.device = serial_trap_device
+      end
+
+      # Unplugs the Drive1541, leaving the serial bus with nothing on it.
+      def detach_drive1541
+        return unless @drive1541
+
+        @iec_bus.detach(@drive1541)
+        @drive1541 = nil
+        @serial_trap&.device = serial_trap_device
+      end
+
+      # Records what the KERNAL prints through CHROUT (ChroutTrap).
+      def capture_output
+        @capture_output ||= ChroutTrap.new(cpu:, bus:, layout: KernalTrap::VIC20_LAYOUT).tap do |trap|
+          cpu.install_trap(ChroutTrap::ADDRESS) { trap.call }
+        end
+      end
+
+      private
+
+      # The device number the serial traps answer: device 8, unless a true
+      # drive is on the bus as device 8.
+      def serial_trap_device
+        @drive1541&.device == KernalTrap::Routine::DEVICE ? nil : KernalTrap::Routine::DEVICE
+      end
+    end
+  end
+end