badline 0.5.1 → 0.6.1

data/lib/badline/cpu/core.rb

@@ -0,0 +1,165 @@
+# frozen_string_literal: true
+
+require "badline/cpu/microcode"
+require "badline/cpu/addressing"
+require "badline/cpu/operations"
+require "badline/cpu/stack_operations"
+require "badline/cpu/boundary"
+require "badline/cpu/saved_state"
+
+module Badline
+  class CPU
+    STATUS_FLAGS = [:carry, :zero, :interrupt, :decimal, :break, 1, :overflow, :negative].freeze
+
+    # The 6502 core, on whatever bus +memory+ is. The C64's 6510 (CPU) and
+    # the 1541's 6502 (Drive1541::CPU) each include it.
+    module Core
+      include IntegerHelper
+      include InstructionSet
+      include Interrupts
+      include Traps
+      include Addressing
+      include Operations
+      include StackOperations
+      include Boundary
+      include SavedState
+
+      attr_reader :memory, :instructions, :boundary_crossed, :cycles, :pending_write
+      attr_accessor :program_counter, :stack_pointer, :status, :a, :x, :y, :nmi, :irq
+
+      alias pending_write? pending_write
+
+      # +ane_constant+ is ANE's magic constant, which varies from chip to
+      # chip. The default is the C64 6510's.
+      def initialize(memory, debug: false, ane_constant: 0xef)
+        @debug = debug
+        @ane_constant = ane_constant
+        @memory = memory
+        @status = CPUStatus.new(STATUS_FLAGS, value: 0b00100000)
+        reset_registers
+
+        @nmi = @irq = false
+        @irq_sample = @irq_pending = false
+        @nmi_sample = @nmi_pending = false
+        @skip_poll = false
+        @boundary_crossed = false
+        @interrupt = nil
+        @brk = false
+        @pending_write = false
+        @stalled_at = nil
+        @so_high = true
+
+        @cycles = 0
+        @instructions = 0
+        @traps = nil
+        end_sequence
+      end
+
+      def reset!
+        status.interrupt = true
+        reset_registers
+        @nmi = false
+        @irq_sample = @irq_pending = false
+        @nmi_sample = @nmi_pending = false
+        @skip_poll = false
+        @pending_write = false
+        end_sequence
+      end
+
+      def p
+        status.value
+      end
+
+      def p=(new_value)
+        status.value = new_value
+      end
+
+      def cycle!
+        poll # the interrupt lines
+
+        # Run the next step
+        index = @index
+        @index = index + 1
+        send(@plan[index])
+        @cycles += 1
+
+        # Record if the next step writes to memory
+        @pending_write = @writes[@index]
+        nil
+      end
+
+      # Called instead of #cycle! on a cycle the VIC holds the CPU through
+      # BA. Records which cycle the CPU was stalled before, and keeps
+      # sampling the interrupt lines.
+      def stall!
+        @stalled_at = @cycles
+        sample_while_stalled
+      end
+
+      # The 6502's SO (set overflow) pin, which the 6510 leaves out, so the
+      # C64 never drives it. A falling edge sets V and a held level does
+      # nothing more.
+      def so=(high)
+        @status.overflow = true if @so_high && !high
+        @so_high = high
+      end
+
+      # Pulses SO: pulls it low, which sets V, and releases it.
+      def so!
+        @status.overflow = true
+        @so_high = true
+      end
+
+      def jammed?
+        @plan.equal?(JAMMED_PLAN)
+      end
+
+      # Runs to the end of the instruction, or until the CPU jams.
+      def step!
+        cycle!
+        cycle! until @plan.equal?(FETCH_PLAN) || jammed?
+        nil
+      end
+
+      # Whether the next cycle fetches an opcode.
+      def boundary? = @index.zero? && @plan.equal?(FETCH_PLAN)
+
+      def trapped? = !@traps.nil?
+
+      def inspect
+        "Cycles: #{@cycles}, PC: #{format16(program_counter)}, " \
+          "SP: #{format8(stack_pointer)}, A: #{format8(a)}, X: #{format8(x)}, " \
+          "Y: #{format8(y)}, P: #{format8(p)}"
+      end
+
+      private
+
+      # True when the CPU was stalled right before this cycle.
+      def stalled_before_this_cycle?
+        @stalled_at == @cycles
+      end
+
+      # True when the CPU was stalled right before the cycle that preceded
+      # this one.
+      def stalled_before_previous_cycle?
+        @stalled_at == @cycles - 1
+      end
+
+      def write_byte(addr, value)
+        @memory.poke(addr, value)
+      end
+
+      def stack_address(offset = 0)
+        0x0100 | ((@stack_pointer + offset) & 0xff)
+      end
+
+      def reset_registers
+        # The program counter is initialized from the reset vector
+        @program_counter = @memory.peek16(0xfffc)
+        # Stack pointer starts at 0x01ff and grows down
+        @stack_pointer = 0xff
+        @a = @x = @y = 0x0
+      end
+    end
+  end
+end

data/lib/badline/cpu/microcode.rb

@@ -165,5 +165,13 @@ module Badline
     INTERRUPT_WRITES = Microcode.write_mask(INTERRUPT_PLAN)
     JAMMED_WRITES = Microcode.write_mask(JAMMED_PLAN)
     MICROCODE = Microcode.table
+
+    # The instruction methods, in a fixed order a snapshot names them by.
+    OPERATIONS = MICROCODE.map(&:operation).uniq.freeze
+
+    # The plans a snapshot names that aren't an opcode's.
+    FETCH = -1
+    INTERRUPT = -2
+    JAMMED = -3
   end
 end

data/lib/badline/cpu/saved_state.rb

@@ -0,0 +1,115 @@
+# frozen_string_literal: true
+
+module Badline
+  class CPU
+    # The CPU's state for a snapshot: the registers, the interrupt lines and
+    # their pipeline, and the step of the instruction in flight, named by
+    # where its plan comes from.
+    module SavedState
+      # Writes everything the CPU holds, down to the step of the instruction
+      # it is in, for load_state to put back. The interrupt lines, BA stalls
+      # and SO are state too; the traps and the debug flag belong to the host.
+      def save_state(out)
+        out.marker("CPU")
+        out.int(@program_counter).int(@stack_pointer).int(@a).int(@x).int(@y).int(@status.value)
+        [@irq, @nmi, @irq_sample, @irq_pending, @nmi_sample, @nmi_pending, @skip_poll, @boundary_irq,
+         @boundary_nmi, @boundary_crossed, @brk, @pending_write, @so_high, @optional_dummy,
+         @branch_taken].each { |flag| out.boolean(flag) }
+        out.optional_int(@interrupt).optional_int(@stalled_at).int(@cycles).int(@instructions)
+        out.int(plan_source).int(@index).int(OPERATIONS.index(@operation) || -1)
+        [@address, @dummy_address, @value, @rmw_result, @pointer].each { |register| out.optional_int(register) }
+      end
+
+      def load_state(input)
+        input.marker("CPU")
+        @program_counter = input.int
+        @stack_pointer = input.int
+        @a = input.int
+        @x = input.int
+        @y = input.int
+        @status.value = input.int
+        load_flags(input)
+        @interrupt = input.optional_int
+        @stalled_at = input.optional_int
+        @cycles = input.int
+        @instructions = input.int
+        load_plan(input.int)
+        @index = input.int
+        operation = input.int
+        @operation = operation.negative? ? nil : OPERATIONS.fetch(operation)
+        load_working_registers(input)
+      end
+
+      # Drops the instruction or interrupt sequence in flight and the
+      # interrupt lines' pipeline, so the next cycle fetches an opcode at the
+      # program counter, and sets the cycle count. A snapshot taken between
+      # instructions, as VICE's are, restores through here.
+      def resume(cycles)
+        @irq_sample = @irq_pending = false
+        @nmi_sample = @nmi_pending = false
+        @skip_poll = false
+        @interrupt = nil
+        @brk = false
+        @stalled_at = nil
+        @cycles = cycles
+        end_sequence
+        @pending_write = false
+      end
+
+      private
+
+      # Where the plan running comes from: an opcode's microcode, or FETCH,
+      # INTERRUPT or JAMMED below it.
+      def plan_source
+        return FETCH if @plan.equal?(FETCH_PLAN)
+        return INTERRUPT if @plan.equal?(INTERRUPT_PLAN)
+        return JAMMED if @plan.equal?(JAMMED_PLAN)
+
+        MICROCODE.index { |micro| micro.plan.equal?(@plan) && micro.operation == @operation } ||
+          MICROCODE.index { |micro| micro.plan.equal?(@plan) }
+      end
+
+      def load_plan(source)
+        case source
+        when FETCH then use_plan(FETCH_PLAN, FETCH_WRITES)
+        when INTERRUPT then use_plan(INTERRUPT_PLAN, INTERRUPT_WRITES)
+        when JAMMED then use_plan(JAMMED_PLAN, JAMMED_WRITES)
+        else
+          micro = MICROCODE.fetch(source)
+          use_plan(micro.plan, micro.writes)
+        end
+      end
+
+      def use_plan(plan, writes)
+        @plan = plan
+        @writes = writes
+      end
+
+      def load_flags(input)
+        @irq = input.boolean?
+        @nmi = input.boolean?
+        @irq_sample = input.boolean?
+        @irq_pending = input.boolean?
+        @nmi_sample = input.boolean?
+        @nmi_pending = input.boolean?
+        @skip_poll = input.boolean?
+        @boundary_irq = input.boolean?
+        @boundary_nmi = input.boolean?
+        @boundary_crossed = input.boolean?
+        @brk = input.boolean?
+        @pending_write = input.boolean?
+        @so_high = input.boolean?
+        @optional_dummy = input.boolean?
+        @branch_taken = input.boolean?
+      end
+
+      def load_working_registers(input)
+        @address = input.optional_int
+        @dummy_address = input.optional_int
+        @value = input.optional_int
+        @rmw_result = input.optional_int
+        @pointer = input.optional_int
+      end
+    end
+  end
+end

data/lib/badline/cpu.rb

@@ -1,219 +1,10 @@
 # frozen_string_literal: true
 
-require "badline/cpu/microcode"
-require "badline/cpu/addressing"
-require "badline/cpu/operations"
-require "badline/cpu/stack_operations"
+require "badline/cpu/core"
 
 module Badline
+  # The C64's 6510, on the AddressBus.
   class CPU
-    STATUS_FLAGS = [:carry, :zero, :interrupt, :decimal, :break, 1, :overflow, :negative].freeze
-
-    include IntegerHelper
-    include InstructionSet
-    include Interrupts
-    include Traps
-    include Addressing
-    include Operations
-    include StackOperations
-
-    attr_reader :memory, :instructions, :boundary_crossed, :cycles, :pending_write
-    attr_accessor :program_counter, :stack_pointer, :status, :a, :x, :y, :nmi, :irq
-
-    alias pending_write? pending_write
-
-    # +ane_constant+ is ANE's magic constant, which varies from chip to
-    # chip. The default is the C64 6510's.
-    def initialize(memory, debug: false, ane_constant: 0xef)
-      @debug = debug
-      @ane_constant = ane_constant
-      @memory = memory
-      @status = CPUStatus.new(STATUS_FLAGS, value: 0b00100000)
-      reset_registers
-
-      @nmi = @irq = false
-      @irq_sample = @irq_pending = false
-      @nmi_sample = @nmi_pending = false
-      @skip_poll = false
-      @boundary_crossed = false
-      @interrupt = nil
-      @brk = false
-      @pending_write = false
-      @stalled_at = nil
-      @so_high = true
-
-      @cycles = 0
-      @instructions = 0
-      @traps = nil
-      end_sequence
-    end
-
-    def reset!
-      status.interrupt = true
-      reset_registers
-      @nmi = false
-      @irq_sample = @irq_pending = false
-      @nmi_sample = @nmi_pending = false
-      @skip_poll = false
-      @pending_write = false
-      end_sequence
-    end
-
-    def p
-      status.value
-    end
-
-    def p=(new_value)
-      status.value = new_value
-    end
-
-    def cycle!
-      poll # the interrupt lines
-
-      # Run the next step
-      index = @index
-      @index = index + 1
-      send(@plan[index])
-      @cycles += 1
-
-      # Record if the next step writes to memory
-      @pending_write = @writes[@index]
-      nil
-    end
-
-    # Called instead of #cycle! on a cycle the VIC holds the CPU through
-    # BA. Records which cycle the CPU was stalled before, and keeps
-    # sampling the interrupt lines.
-    def stall!
-      @stalled_at = @cycles
-      sample_while_stalled
-    end
-
-    # The 6502's SO (set overflow) pin, which the 6510 leaves out, so the
-    # C64 never drives it. A falling edge sets V and a held level does
-    # nothing more.
-    def so=(high)
-      @status.overflow = true if @so_high && !high
-      @so_high = high
-    end
-
-    # Pulses SO: pulls it low, which sets V, and releases it.
-    def so!
-      @status.overflow = true
-      @so_high = true
-    end
-
-    def jammed?
-      @plan.equal?(JAMMED_PLAN)
-    end
-
-    # Runs to the end of the instruction, or until the CPU jams.
-    def step!
-      cycle!
-      cycle! until @plan.equal?(FETCH_PLAN) || jammed?
-      nil
-    end
-
-    # Whether the next cycle fetches an opcode.
-    def boundary? = @index.zero? && @plan.equal?(FETCH_PLAN)
-
-    def trapped? = !@traps.nil?
-
-    # Everything the CPU holds but its cycle and instruction counts: the
-    # registers, the interrupt lines and pipeline, and what the last
-    # instruction left in its working registers. Drive1541::Idle compares
-    # it at two instruction boundaries.
-    def idle_state
-      [@program_counter, @stack_pointer, @a, @x, @y, @status.value,
-       @irq, @nmi, @irq_sample, @irq_pending, @nmi_sample, @nmi_pending, @skip_poll,
-       @boundary_irq, @boundary_nmi, @so_high, @interrupt, @brk, @pending_write, @stalled_at, @traps,
-       @operation, @optional_dummy, @boundary_crossed, @branch_taken,
-       @address, @pointer, @dummy_address, @value, @rmw_result]
-    end
-
-    # Counts +cycles+ cycles and +instructions+ instructions that ran
-    # without changing anything idle_state holds.
-    def fast_forward(cycles, instructions)
-      @cycles += cycles
-      @instructions += instructions
-    end
-
-    def inspect
-      "Cycles: #{@cycles}, PC: #{format16(program_counter)}, " \
-        "SP: #{format8(stack_pointer)}, A: #{format8(a)}, X: #{format8(x)}, " \
-        "Y: #{format8(y)}, P: #{format8(p)}"
-    end
-
-    private
-
-    # The first cycle of every instruction. Starts an interrupt if one was
-    # pending when the previous instruction ended. Otherwise reads the
-    # opcode and switches to its plan.
-    def op_fetch
-      return start_interrupt if @boundary_nmi || @boundary_irq
-
-      run_traps
-      opcode = @memory.peek(@program_counter)
-      log(opcode) if @debug
-      micro = MICROCODE[opcode]
-      @operation = micro.operation
-      @plan = micro.plan
-      @writes = micro.writes
-      @optional_dummy = micro.optional_dummy
-      @index = 1
-      @boundary_crossed = false
-      @program_counter = (@program_counter + 1) & 0xffff
-    end
-
-    def end_instruction
-      @instructions += 1
-      end_sequence
-    end
-
-    # Makes the next cycle an opcode fetch, and saves the pending interrupt
-    # flags for op_fetch. The next cycle polls before op_fetch runs, which
-    # updates the live flags.
-    def end_sequence
-      @plan = FETCH_PLAN
-      @writes = FETCH_WRITES
-      @index = 0
-      @boundary_irq = @irq_pending
-      @boundary_nmi = @nmi_pending
-    end
-
-    # True when the CPU was stalled right before this cycle.
-    def stalled_before_this_cycle?
-      @stalled_at == @cycles
-    end
-
-    # True when the CPU was stalled right before the cycle that preceded
-    # this one.
-    def stalled_before_previous_cycle?
-      @stalled_at == @cycles - 1
-    end
-
-    def write_byte(addr, value)
-      @memory.poke(addr, value)
-    end
-
-    def stack_address(offset = 0)
-      0x0100 | ((@stack_pointer + offset) & 0xff)
-    end
-
-    def reset_registers
-      # The program counter is initialized from the reset vector
-      @program_counter = @memory.peek16(0xfffc)
-      # Stack pointer starts at 0x01ff and grows down
-      @stack_pointer = 0xff
-      @a = @x = @y = 0x0
-    end
-
-    def log(opcode)
-      instruction = Instruction.find(opcode)
-      puts(
-        "#{@cycles}: PC: #{format16(@program_counter)} - " \
-        "#{instruction.name.upcase} #{instruction.addressing_mode}"
-      )
-    end
+    include Core
   end
 end

data/lib/badline/datasette.rb

@@ -54,6 +54,33 @@ module Badline
 
     def running? = @playing && @motor && !@tape.nil?
 
+    # The keys, the motor, the countdown to the next pulse and the tape: its
+    # path and how far it has played.
+    def save_state(out)
+      out.marker("DATASETTE")
+      out.boolean(@playing).boolean(@motor).int(@countdown).boolean(!@tape.nil?)
+      return unless @tape
+
+      out.string(@tape.path).int(@tape.position)
+    end
+
+    # A tape from another file goes in from its path, and a detached
+    # reader leaves the tape out. The sense and flag handlers don't fire.
+    def load_state(input)
+      input.marker("DATASETTE")
+      @playing = input.boolean?
+      @motor = input.boolean?
+      @countdown = input.int
+      return @tape = nil unless input.boolean?
+
+      path = input.string
+      position = input.int
+      return @tape = nil if input.detached?
+
+      @tape = Storage::TAP.new(path) unless @tape&.path&.b == path
+      @tape.position = position
+    end
+
     def cycle!
       return unless running?
 

data/lib/badline/drive1541/bus.rb

@@ -94,6 +94,19 @@ module Badline
         watching!
       end
 
+      # The last byte on the data bus and the RAM. What a watched stretch
+      # touched is Idle's, and a restored bus isn't watching.
+      def save_state(out)
+        out.int(@data)
+        @ram.save_state(out)
+      end
+
+      def load_state(input)
+        @data = input.int
+        @ram.load_state(input)
+        @watching = false
+      end
+
       def peek(addr)
         return @data = @rom.peek(addr | 0x4000) if addr >= 0x8000
 

data/lib/badline/drive1541/cpu.rb

@@ -0,0 +1,29 @@
+# frozen_string_literal: true
+
+module Badline
+  class Drive1541
+    # The drive's 6502, on the drive's Bus.
+    class CPU
+      include Badline::CPU::Core
+
+      # Everything the CPU holds but its cycle and instruction counts: the
+      # registers, the interrupt lines and pipeline, and what the last
+      # instruction left in its working registers. Drive1541::Idle compares
+      # it at two instruction boundaries.
+      def idle_state
+        [@program_counter, @stack_pointer, @a, @x, @y, @status.value,
+         @irq, @nmi, @irq_sample, @irq_pending, @nmi_sample, @nmi_pending, @skip_poll,
+         @boundary_irq, @boundary_nmi, @so_high, @interrupt, @brk, @pending_write, @stalled_at, @traps,
+         @operation, @optional_dummy, @boundary_crossed, @branch_taken,
+         @address, @pointer, @dummy_address, @value, @rmw_result]
+      end
+
+      # Counts +cycles+ cycles and +instructions+ instructions that ran
+      # without changing anything idle_state holds.
+      def fast_forward(cycles, instructions)
+        @cycles += cycles
+        @instructions += instructions
+      end
+    end
+  end
+end

data/lib/badline/drive1541/disk.rb

@@ -1,6 +1,7 @@
 # frozen_string_literal: true
 
 require "badline/drive1541/sector_reader"
+require "badline/drive1541/disk_state"
 
 module Badline
   class Drive1541
@@ -16,6 +17,8 @@ module Badline
     # host file. The disk is write-protected when the image won't take
     # writes.
     class Disk
+      include State
+
       MAX_HALF_TRACK = 84
 
       # GCR bytes around a track in each speed zone: 200 ms of rotation at
@@ -52,9 +55,9 @@ module Badline
       # anything else as a .d64, formatted. `read_only` opens the image
       # write-protected.
       def self.open(path, read_only: false)
-        return from_g64(Storage::G64Image.new(path, read_only:)) if File.extname(path).casecmp?(".g64")
+        return from_g64(Storage::G64Image.new(path, read_only:)).opened(path, read_only) if State.g64?(path)
 
-        from_d64(Storage::D64Image.new(path, read_only:))
+        from_d64(Storage::D64Image.new(path, read_only:)).opened(path, read_only)
       end
 
       # A disk from a G64 image, each half track as the image stores it,
@@ -145,6 +148,8 @@ module Badline
         @image = image
         @tracks = Array.new(MAX_HALF_TRACK + 1)
         @written = {}
+        @path = nil
+        @read_only = false
       end
 
       # The Track at the half track, or nil where there's no data.