badline 0.5.1 → 0.6.1

data/lib/badline/cia/serial.rb

@@ -62,6 +62,19 @@ module Badline
         @sp_out = true
       end
 
+      # The bits shifted so far, and the byte waiting to go out after the
+      # one shifting.
+      attr_reader :steps, :pending
+
+      def shift_register = @shift
+
+      # Sets the data register and the shift register, as a VICE snapshot
+      # gives them.
+      def restore_shift(data, shift)
+        @data = data
+        @shift = shift
+      end
+
       def output?
         @control.serial_mode?
       end
@@ -71,6 +84,25 @@ module Badline
         @cnt = level unless output?
       end
 
+      def save_state(out)
+        out.int(@data).int(@shift).int(@steps).optional_int(@empty_in).optional_int(@busy_in)
+        out.boolean(@busy).boolean(@abandoned).optional_int(@pending).boolean(@underflow_high).boolean(@in_flight)
+        out.int(@flight_up).int(@flight_down).boolean(@idle)
+        [@cnt, @cnt_in, @sp_in, @sp_out].each { |level| out.boolean(level) }
+      end
+
+      def load_state(input)
+        @data = input.int
+        @shift = input.int
+        @steps = input.int
+        @empty_in = input.optional_int
+        @busy_in = input.optional_int
+        @busy = input.boolean?
+        @abandoned = input.boolean?
+        @pending = input.optional_int
+        load_lines(input)
+      end
+
       def write(value)
         @data = value
         @pending = LOAD_DELAY
@@ -132,6 +164,18 @@ module Badline
 
       private
 
+      def load_lines(input)
+        @underflow_high = input.boolean?
+        @in_flight = input.boolean?
+        @flight_up = input.int
+        @flight_down = input.int
+        @idle = input.boolean?
+        @cnt = input.boolean?
+        @cnt_in = input.boolean?
+        @sp_in = input.boolean?
+        @sp_out = input.boolean?
+      end
+
       # Without an underflow, a register with nothing counting down and
       # nothing in the delay lines has nothing to do on a cycle.
       def idle?

data/lib/badline/cia/state.rb

@@ -0,0 +1,47 @@
+# frozen_string_literal: true
+
+module Badline
+  class CIA
+    # A snapshot of the chip: everything it holds but its wiring, the ports,
+    # the PB4 and CNT levels, the timers, the interrupt register, the serial
+    # port and the TOD clock.
+    module State
+      def save_state(out)
+        out.marker("CIA")
+        out.int(@data_port_a).int(@data_port_b).int(@data_dir_a).int(@data_dir_b)
+        out.boolean(@port_b4_high).boolean(@port_b4_driven_high).boolean(@cnt_high).boolean(@cnt_rise)
+        out.int(@control_a.value).int(@control_b.value)
+        @ta.save_state(out)
+        @tb.save_state(out)
+        @icr.save_state(out)
+        @serial.save_state(out)
+        @tod.save_state(out)
+      end
+
+      def load_state(input)
+        input.marker("CIA")
+        @data_port_a = input.int
+        @data_port_b = input.int
+        @data_dir_a = input.int
+        @data_dir_b = input.int
+        @port_b4_high = input.boolean?
+        @port_b4_driven_high = input.boolean?
+        @cnt_high = input.boolean?
+        @cnt_rise = input.boolean?
+        @control_a.value = input.int
+        @control_b.value = input.int
+        load_parts(input)
+      end
+
+      private
+
+      def load_parts(input)
+        @ta.load_state(input)
+        @tb.load_state(input)
+        @icr.load_state(input)
+        @serial.load_state(input)
+        @tod.load_state(input)
+      end
+    end
+  end
+end

data/lib/badline/cia/timer.rb

@@ -42,6 +42,26 @@ module Badline
         settle
       end
 
+      # The counter, the latch and the pipeline between them. The control
+      # register is the CIA's to save.
+      def save_state(out)
+        out.int(@counter).int(@latch).int(@pipe).int(@load_delay).boolean(@reload).boolean(@underflowed)
+        out.int(@oneshot_linger).boolean(@toggle).boolean(@settled).boolean(@empty)
+      end
+
+      def load_state(input)
+        @counter = input.int
+        @latch = input.int
+        @pipe = input.int
+        @load_delay = input.int
+        @reload = input.boolean?
+        @underflowed = input.boolean?
+        @oneshot_linger = input.int
+        @toggle = input.boolean?
+        @settled = input.boolean?
+        @empty = input.boolean?
+      end
+
       def write_control(value)
         @toggle = true if value.anybits?(0x01) && !started?
         @oneshot_linger = 2 if control.run_mode? && value.nobits?(0x08)
@@ -59,6 +79,19 @@ module Badline
         @counter = @latch unless started?
       end
 
+      # Whether the timer's PB output toggle is high, and its count pipeline
+      # as two bits, the newer stage high.
+      attr_reader :toggle, :pipe
+
+      # Sets the control register without its load strobe, the toggle and
+      # the count pipeline, as a VICE snapshot gives them.
+      def restore_pipeline(control, toggle, pipe)
+        @control.value = control & ~0x10
+        @toggle = toggle
+        @pipe = pipe
+        settle
+      end
+
       private
 
       def started?

data/lib/badline/cia.rb

@@ -3,11 +3,13 @@
 require "badline/cia/interrupt_register"
 require "badline/cia/serial"
 require "badline/cia/timer"
+require "badline/cia/state"
 
 module Badline
   # CIA (Complex Interface Adapter) chip
   class CIA
     include Addressable
+    include State
 
     # The original NMOS 6526 of the breadbin C64, and the HMOS 6526A of the
     # C64C, which differs from it only in its interrupt control register.
@@ -19,6 +21,12 @@ module Badline
     # read_a and read_b, and on CIA 1 drives PB4 through port_b4_high?.
     attr_accessor :peripheral
 
+    # Timer A and timer B.
+    def timers = [@ta, @tb]
+
+    # Port A and B's data and direction registers.
+    def port_registers = [@data_port_a, @data_port_b, @data_dir_a, @data_dir_b]
+
     def interrupt_status = @icr.status
 
     def interrupt_control = @icr.mask

data/lib/badline/computer/attachments.rb

@@ -0,0 +1,132 @@
+# frozen_string_literal: true
+
+module Badline
+  class Computer
+    # What plugs into the machine besides its chips, the cartridge, the
+    # disk device 8 serves through the traps, a true 1541 and an REU, and
+    # their state for a snapshot.
+    module Attachments
+      # Puts the cartridge in the expansion port and wires its clock and NMI
+      # line to the machine, leaving the machine's state as it is. A
+      # restored snapshot's cartridge comes back through here.
+      def connect_cartridge(cartridge)
+        cartridge.clock = -> { @cycles }
+        cartridge.on_nmi_change { |level| @cartridge_nmi = level }
+        address_bus.attach_cartridge(cartridge)
+      end
+
+      # Puts the storage in device 8. Mounting again swaps the disk at any
+      # point while the machine runs: the drive keeps its RAM, which only a
+      # drive reset clears, and its status.
+      def mount(storage)
+        return @drive.insert(storage) if @drive
+
+        @drive = KernalTrap::Drive.new(storage)
+        load_trap = KernalTrap::Load.new(cpu:, bus: address_bus, drive: @drive)
+        cpu.install_trap(KernalTrap::Load::ADDRESS) { load_trap.call }
+        @serial_trap = KernalTrap::Serial.new(cpu:, bus: address_bus, drive: @drive, device: serial_trap_device).install
+        save_trap = @save_trap = KernalTrap::Save.new(cpu:, bus: address_bus, drive: @drive)
+        cpu.install_trap(KernalTrap::Save::ADDRESS) { save_trap.call }
+      end
+
+      # Takes device 8's mounted storage out, and with it the LOAD, SAVE and
+      # serial traps, so the KERNAL's routines go out over the serial bus.
+      # Mounting again starts a new drive, with its RAM cleared.
+      def unmount
+        return unless @drive
+
+        cpu.remove_trap(KernalTrap::Load::ADDRESS)
+        cpu.remove_trap(KernalTrap::Save::ADDRESS)
+        @serial_trap.device = nil
+        @serial_trap = nil
+        @save_trap = nil
+        @drive = nil
+      end
+
+      # Whether device 8 serves a disk or directory through the traps.
+      def mounted? = !@drive.nil?
+
+      # Unplugs the Drive1541, leaving the serial bus with nothing on it.
+      def detach_drive1541
+        return unless @drive1541
+
+        @iec_bus&.detach(@drive1541)
+        @drive1541 = nil
+        @serial_trap&.device = serial_trap_device
+      end
+
+      private
+
+      def save_cartridge(out)
+        cartridge = address_bus.cartridge
+        out.boolean(!cartridge.nil?)
+        cartridge&.save_setup(out)
+      end
+
+      # A cartridge comes back built afresh from the setup it was built
+      # with, before the address bus puts its state into it.
+      def load_cartridge(input)
+        if input.boolean?
+          connect_cartridge(Cartridge.from_setup(input))
+        elsif address_bus.cartridge
+          address_bus.detach_cartridge
+        end
+      end
+
+      # The disk device 8 serves through the traps, with the traps' own
+      # state: open channels, the drive's status and RAM, a SAVE under way.
+      def save_trap_drive(out)
+        out.boolean(!@drive.nil?)
+        return unless @drive
+
+        @drive.save_state(out)
+        @serial_trap.save_state(out)
+        @save_trap.save_state(out)
+      end
+
+      def load_trap_drive(input)
+        return unmount unless input.boolean?
+
+        storage = Storage.reopen(input)
+        unmount
+        mount(storage)
+        @drive.load_state(input)
+        @serial_trap.load_state(input)
+        @save_trap.load_state(input)
+      end
+
+      # The serial bus, whose presence decides what CIA 2's port A reads,
+      # and a true 1541 on it.
+      def save_serial_bus(out)
+        out.boolean(!@iec_bus.nil?).boolean(!@drive1541.nil?)
+        return unless @drive1541
+
+        out.int(@drive1541.device)
+        @drive1541.save_state(out)
+      end
+
+      def load_serial_bus(input)
+        iec_bus if input.boolean?
+        return detach_drive1541 unless input.boolean?
+
+        device = input.int
+        detach_drive1541 if @drive1541 && @drive1541.device != device
+        attach_drive1541(Drive1541.new(device:)) unless @drive1541
+        @drive1541.load_state(input)
+      end
+
+      # The REU, which the setup says the machine has, and whether it has
+      # asked for the bus. Its IRQ line reaches the CPU as it was.
+      def save_reu(out)
+        @reu&.save_state(out)
+        out.boolean(@dma)
+      end
+
+      def load_reu(input)
+        @reu&.load_state(input)
+        @reu_irq = @reu ? @reu.irq? : false
+        @dma = input.boolean?
+      end
+    end
+  end
+end

data/lib/badline/computer/saved_state.rb

@@ -0,0 +1,116 @@
+# frozen_string_literal: true
+
+module Badline
+  class Computer
+    # The keyword arguments Computer.new takes to build the machine a
+    # State from #snapshot was taken of.
+    def self.setup(state)
+      input = Snapshot::StateReader.new(state)
+      input.marker("COMPUTER")
+      input.check_stamp
+      Snapshot::Setup.read(input)
+    end
+
+    # A new machine, built as the one a State from #snapshot was taken of,
+    # at that state. `detached` builds it without the host's files
+    # (Snapshot::StateReader).
+    def self.restored(state, detached: false) = setup(state).build.apply_state(state, detached:)
+
+    # The whole machine's state for a snapshot: the machine's own latches,
+    # the bus and its chips, the CPU, and what is attached to it
+    # (Attachments).
+    module SavedState
+      # How many more on_init handlers the machine a State was taken of had
+      # yet to run than this one has: they are the host's blocks, which a
+      # State can't hold. Nil until the machine is restored.
+      attr_reader :init_handlers_lost
+
+      # The machine's whole state, in memory. #restore takes the machine, or
+      # another built with the same chip models, region and RAM expansion,
+      # back to it. The cartridge, the disk in device 8, a true 1541 and its
+      # disk and the tape go in the state too. What the host holds stays
+      # out: the keyboard, the joysticks and the pot devices, the traps and
+      # callbacks, whether the display renders and whether the SID records.
+      def snapshot
+        out = Snapshot::StateWriter.new
+        save_state(out)
+        out.state
+      end
+
+      # Takes the machine back to a State from #snapshot. The machine keeps
+      # its chips, its traps and its callbacks, and puts in the cartridge,
+      # drives and tape the state has, taking out any it hasn't. Raises
+      # Snapshot::FormatError for a state of a machine built another way.
+      # The state goes into a new machine first, so one that fails leaves
+      # this machine as it was.
+      def restore(state)
+        check_setup(Computer.setup(state))
+        Computer.restored(state)
+        apply_state(state)
+      end
+
+      # Puts a State into the machine without trying it on a new one
+      # first, for a machine built for it (Computer.restored): a state that
+      # fails leaves the machine part restored. `detached` restores it
+      # without the host's files (Snapshot::StateReader).
+      def apply_state(state, detached: false)
+        input = Snapshot::StateReader.new(state, detached:)
+        load_state(input)
+        raise Snapshot::FormatError, "the state goes on past the machine" unless input.finished?
+
+        self
+      end
+
+      # Sets the machine's cycle count, for a snapshot from VICE, which
+      # counts from its own clock.
+      def resume_at(cycles)
+        @cycles = cycles
+      end
+
+      def save_state(out)
+        out.marker("COMPUTER").stamp
+        Snapshot::Setup.of(address_bus).write(out)
+        out.int(@cycles).boolean(@nmi_asserted).boolean(@cartridge_nmi).boolean(@restore_pulse).boolean(@freezing)
+        out.int(@freeze_writes).boolean(!@pending_keys.nil?)
+        out.ints(@pending_keys) if @pending_keys
+        out.int(booting? ? @init_handlers.length : 0)
+        save_cartridge(out)
+        address_bus.save_state(out)
+        @cpu.save_state(out)
+        save_trap_drive(out)
+        save_serial_bus(out)
+        save_reu(out)
+      end
+
+      def load_state(input)
+        input.marker("COMPUTER")
+        input.check_stamp
+        check_setup(Snapshot::Setup.read(input))
+        @cycles = input.int
+        @nmi_asserted = input.boolean?
+        @cartridge_nmi = input.boolean?
+        @restore_pulse = input.boolean?
+        @freezing = input.boolean?
+        @freeze_writes = input.int
+        @pending_keys = nil
+        @pending_keys = input.ints if input.boolean?
+        @init_handlers_lost = [input.int - @init_handlers.length, 0].max
+        load_cartridge(input)
+        address_bus.load_state(input)
+        @cpu.load_state(input)
+        load_trap_drive(input)
+        load_serial_bus(input)
+        load_reu(input)
+      end
+
+      private
+
+      def check_setup(setup)
+        ours = Snapshot::Setup.of(address_bus)
+        return if setup == ours
+
+        raise Snapshot::FormatError, "the state is of a machine with #{setup}, not #{ours}"
+      end
+    end
+  end
+end

data/lib/badline/computer.rb

@@ -1,9 +1,14 @@
 # frozen_string_literal: true
 
+require "badline/computer/attachments"
+require "badline/computer/saved_state"
+
 module Badline
   class Computer
     include IntegerHelper
     include KeyboardBuffer
+    include Attachments
+    include SavedState
 
     attr_reader :address_bus, :cpu, :cycles, :drive1541
 
@@ -59,6 +64,7 @@ module Badline
       @pending_keys = nil
       @drive = nil
       @serial_trap = nil
+      @save_trap = nil
       @drive1541 = nil
       @iec_bus = nil
       @reu = reu ? plug_reu(reu) : nil
@@ -95,9 +101,7 @@ module Badline
     end
 
     def attach_cartridge(cartridge)
-      cartridge.clock = -> { @cycles }
-      cartridge.on_nmi_change { |level| @cartridge_nmi = level }
-      address_bus.attach_cartridge(cartridge)
+      connect_cartridge(cartridge)
       power_cycle!
     end
 
@@ -151,33 +155,6 @@ module Badline
       @restore_pulse = true
     end
 
-    # Puts the storage in device 8. Mounting again swaps the disk at any
-    # point while the machine runs: the drive keeps its RAM, which only a
-    # drive reset clears, and its status.
-    def mount(storage)
-      return @drive.insert(storage) if @drive
-
-      @drive = KernalTrap::Drive.new(storage)
-      load_trap = KernalTrap::Load.new(cpu:, bus: address_bus, drive: @drive)
-      cpu.install_trap(KernalTrap::Load::ADDRESS) { load_trap.call }
-      @serial_trap = KernalTrap::Serial.new(cpu:, bus: address_bus, drive: @drive, device: serial_trap_device).install
-      save_trap = KernalTrap::Save.new(cpu:, bus: address_bus, drive: @drive)
-      cpu.install_trap(KernalTrap::Save::ADDRESS) { save_trap.call }
-    end
-
-    # Takes device 8's mounted storage out, and with it the LOAD, SAVE and
-    # serial traps, so the KERNAL's routines go out over the serial bus.
-    # Mounting again starts a new drive, with its RAM cleared.
-    def unmount
-      return unless @drive
-
-      cpu.remove_trap(KernalTrap::Load::ADDRESS)
-      cpu.remove_trap(KernalTrap::Save::ADDRESS)
-      @serial_trap.device = nil
-      @serial_trap = nil
-      @drive = nil
-    end
-
     # Plugs in a Drive1541, which then runs alongside the C64 on its own
     # clock and talks to it over the serial bus. The serial traps stop
     # answering the drive's device number, so the KERNAL's TALK, LISTEN and
@@ -249,12 +226,15 @@ module Badline
       @cpu.pending_write? || !@vic.ba_low? ? @cpu.cycle! : @cpu.stall!
     end
 
+    # The REU's /DMA line takes the bus from the CPU from the cycle after
+    # it asks for it, even while it waits for BA, but RDY only halts the
+    # CPU on a read, so a write it makes then goes nowhere.
     def dma_cycle!
       writing = @cpu.pending_write?
-      @reu.dma_cycle!(@vic.reu_ba_low?, writing)
-      return @cpu.stall! if @reu.holds_bus?
+      @reu.dma_cycle!(@vic.ba_low?)
+      return writing ? @address_bus.cycle_cpu_off_bus(@cpu) : @cpu.stall! if @reu.dma?
 
-      @dma = @reu.dma?
+      @dma = false
       writing || !@vic.ba_low? ? @cpu.cycle! : @cpu.stall!
     end
 

data/lib/badline/cpu/boundary.rb

@@ -0,0 +1,54 @@
+# frozen_string_literal: true
+
+module Badline
+  class CPU
+    # The steps at an instruction boundary: the opcode fetch that starts
+    # an instruction, and the ends of one.
+    module Boundary
+      private
+
+      # The first cycle of every instruction. Starts an interrupt if one was
+      # pending when the previous instruction ended. Otherwise reads the
+      # opcode and switches to its plan.
+      def op_fetch
+        return start_interrupt if @boundary_nmi || @boundary_irq
+
+        run_traps
+        opcode = @memory.peek(@program_counter)
+        log(opcode) if @debug
+        micro = MICROCODE[opcode]
+        @operation = micro.operation
+        @plan = micro.plan
+        @writes = micro.writes
+        @optional_dummy = micro.optional_dummy
+        @index = 1
+        @boundary_crossed = false
+        @program_counter = (@program_counter + 1) & 0xffff
+      end
+
+      def end_instruction
+        @instructions += 1
+        end_sequence
+      end
+
+      # Makes the next cycle an opcode fetch, and saves the pending interrupt
+      # flags for op_fetch. The next cycle polls before op_fetch runs, which
+      # updates the live flags.
+      def end_sequence
+        @plan = FETCH_PLAN
+        @writes = FETCH_WRITES
+        @index = 0
+        @boundary_irq = @irq_pending
+        @boundary_nmi = @nmi_pending
+      end
+
+      def log(opcode)
+        instruction = Instruction.find(opcode)
+        puts(
+          "#{@cycles}: PC: #{format16(@program_counter)} - " \
+          "#{instruction.name.upcase} #{instruction.addressing_mode}"
+        )
+      end
+    end
+  end
+end