badline 0.4.2 → 0.5.1

data/lib/badline/kernal_trap/serial.rb

@@ -6,7 +6,12 @@ module Badline
     # device 8 go to a virtual drive instead of out over the IEC lines, so
     # OPEN/CHKIN/CHRIN reach a CBM DOS, and so do the block reads that
     # loaders make through them. Other devices fall through to the ROM.
+    #
+    # With +device+ nil the traps answer no device, and every frame goes
+    # out over the bus, to a true drive if one is plugged in.
     class Serial < Routine
+      attr_accessor :device
+
       ROUTINES = {
         0xed09 => :talk,
         0xed0c => :listen,
@@ -29,9 +34,10 @@ module Badline
 
       NO_DATA = [0x0d, EOI | READ_TIMEOUT].freeze
 
-      def initialize(cpu:, bus:, drive:)
+      def initialize(cpu:, bus:, drive:, device: DEVICE)
         super(cpu:, bus:)
         @drive = drive
+        @device = device
         @listening = false
         @talking = false
         @listen_channel = nil
@@ -66,13 +72,13 @@ module Badline
       # in the secondary address that follows.
       def talk
         @talk_channel = nil
-        @talking = @cpu.a == DEVICE
+        @talking = @cpu.a == @device
         return_to_caller if @talking
       end
 
       def listen
         @listen_channel = nil
-        @listening = @cpu.a == DEVICE
+        @listening = @cpu.a == @device
         return_to_caller if @listening
       end
 

data/lib/badline/media/true_drive.rb

@@ -0,0 +1,54 @@
+# frozen_string_literal: true
+
+module Badline
+  module Media
+    # Device 8 as a true 1541 instead of the KERNAL traps. Once a Drive1541
+    # is plugged in as device 8, disk media go into it rather than into the
+    # traps, so a LOAD runs the DOS and every byte crosses the serial bus.
+    # A .g64 holds the disk's raw GCR, which only a true drive reads, so it
+    # plugs one in when there's none yet. The 1541 reads only .d64 and .g64
+    # images, so the traps' other disk media, a .d71, .d81 or .t64 or a host
+    # directory, raise Error.
+    module TrueDrive
+      class Error < ArgumentError; end
+
+      class << self
+        # Plugs a Drive1541 in as device 8, unless one is there already, and
+        # returns it.
+        def plug(computer)
+          drive(computer) || Drive1541.new.tap { |drive| computer.attach_drive1541(drive) }
+        end
+
+        # The Drive1541 on device 8, or nil.
+        def drive(computer)
+          drive = computer.drive1541
+          drive if drive && drive.device == KernalTrap::Routine::DEVICE
+        end
+
+        # Whether the path goes in a true drive: a .g64 always, and other
+        # disk media, which the traps would mount, when a true drive is
+        # device 8.
+        def takes?(computer, path)
+          return true if File.extname(path).casecmp?(".g64")
+
+          !drive(computer).nil? && (File.directory?(path) || MOUNT_TYPES.key?(File.extname(path).downcase))
+        end
+
+        # Puts the .d64 or .g64 in the drive on device 8, plugging one in
+        # when there's none, and takes out what was mounted through the
+        # traps, so LOAD and SAVE reach the drive too. `read_only` puts it
+        # in write-protected.
+        def insert(computer, path, read_only: false)
+          unless %w[.d64 .g64].include?(File.extname(path).downcase)
+            raise Error, "#{path} is not a .d64 or .g64 image, which the 1541 reads"
+          end
+
+          disk = Drive1541::Disk.open(path, read_only:)
+          computer.unmount
+          plug(computer).insert(disk)
+          "Inserted #{path} in the 1541 as device 8"
+        end
+      end
+    end
+  end
+end

data/lib/badline/media.rb

@@ -1,5 +1,7 @@
 # frozen_string_literal: true
 
+require "badline/media/true_drive"
+
 module Badline
   module Media
     AUTOSTART = %(lO"*",8,1\rrun\r)
@@ -19,8 +21,14 @@ module Badline
       # the Retro Replay's flash mode, and `disk: { read_only: true }` mounts
       # a disk image write-protected, so nothing the program does writes to
       # its file. Media they don't apply to ignore them.
+      #
+      # A .g64 plugs in a true drive as device 8 (TrueDrive), and with one
+      # there, a .d64 goes into it instead of the KERNAL traps too. The
+      # autostart then loads through it.
       def attach(computer, path, autostart: true, song: nil, **options)
-        if File.directory?(path)
+        if TrueDrive.takes?(computer, path)
+          attach_true_drive(computer, path, options.fetch(:disk, {}), autostart:)
+        elsif File.directory?(path)
           computer.mount(Storage::HostDirectory.new(path))
           "Mounted #{path} as device 8"
         elsif File.extname(path).downcase == ".crt"
@@ -40,7 +48,14 @@ module Badline
       # while the machine runs, without loading anything. The drive keeps
       # its RAM and its status. `read_only` inserts a disk image
       # write-protected.
+      #
+      # A .g64 goes in a true 1541, which is plugged in as device 8 when
+      # there's none yet (TrueDrive). Once a true 1541 is device 8, a .d64
+      # goes in its drive as well, and other disks, which a 1541 can't
+      # read, raise TrueDrive::Error, an ArgumentError.
       def insert_disk(computer, path, read_only: false)
+        return TrueDrive.insert(computer, path, read_only:) if TrueDrive.takes?(computer, path)
+
         raise ArgumentError, "#{path} is not a disk image or a directory" unless disk?(path)
 
         computer.mount(open_storage(path, { read_only: }))
@@ -98,6 +113,12 @@ module Badline
         "Inserted #{path} in the datasette"
       end
 
+      def attach_true_drive(computer, path, disk, autostart:)
+        message = TrueDrive.insert(computer, path, read_only: disk.fetch(:read_only, false))
+        computer.type_text(AUTOSTART) if autostart
+        message
+      end
+
       def attach_storage(computer, path, disk, autostart:)
         computer.mount(open_storage(path, disk))
         computer.type_text(AUTOSTART) if autostart

data/lib/badline/memory.rb

@@ -22,6 +22,9 @@ module Badline
       (addr...(addr + length)).to_a.map { |a| peek(a) }
     end
 
+    # Every byte, as a copy.
+    def snapshot = @storage.dup
+
     def write(addr, bytes)
       Array(bytes).each_with_index { |b, i| poke(addr + i, b) }
     end

data/lib/badline/options.rb

@@ -21,9 +21,13 @@ module Badline
              badline-ruby --headless [options] tune.sid
              badline-ruby [options] tune.sid --audio-out FILE
 
-      Media can be a .prg/.p00 program, a .d64/.d71/.d81 disk image,
-      a .t64 tape archive, a .tap tape, a .crt cartridge, a .sid tune, or
-      a directory to mount as device 8. It opens in the emulator window.
+      Media can be a .prg/.p00 program, a .d64/.d71/.d81 disk image, a
+      .g64 disk image for the true 1541, a .t64 tape archive, a .tap
+      tape, a .crt cartridge, a .sid tune, or a directory to mount as
+      device 8. It opens in the emulator window. Device 8 answers through
+      traps on the KERNAL's disk routines, unless --true-drive puts an
+      emulated 1541 there, which runs its own DOS and reads .d64 and .g64
+      images only.
 
       --headless plays a .sid tune on the host's audio device without the
       window, and --audio-out renders it to 16-bit PCM instead. The
@@ -43,7 +47,7 @@ module Badline
 
     BANNER
 
-    attr_reader :media_path, :audio_out, :song, :seconds, :songlengths, :sid_model, :filter_chunk
+    attr_reader :media_path, :audio_out, :song, :seconds, :songlengths, :sid_model, :filter_chunk, :reu
 
     alias tune_path media_path
 
@@ -54,6 +58,8 @@ module Badline
       @read_only = false
       @sound = false
       @verbose = false
+      @true_drive = false
+      @ntsc = false
       @headless = false
       @jit = true
       @quiet = false
@@ -99,6 +105,10 @@ module Badline
 
     def verbose? = @verbose
 
+    def true_drive? = @true_drive
+
+    def ntsc? = @ntsc
+
     def quiet? = @quiet
 
     def tui? = @tui
@@ -168,6 +178,16 @@ module Badline
       opts.on("--sound", "Play the SID through the host's audio device (F10 mutes)") do
         window_only("--sound") { @sound = true }
       end
+      opts.on("--true-drive", "Put a true 1541 on device 8 instead of the KERNAL traps") do
+        window_only("--true-drive") { @true_drive = true }
+      end
+      opts.on("--reu SIZE", %w[128 256 512 1024 2048 4096 8192 16384],
+              "Plug in an REU of SIZE K: 128, 256, 512 (a 1750) or up to 16384") do |size|
+        window_only("--reu") { @reu = size.to_i }
+      end
+      opts.on("--ntsc", "Run an NTSC C64, with the 6567R8 VIC-II, instead of a PAL one") do
+        window_only("--ntsc") { @ntsc = true }
+      end
       opts.on("--verbose", "Print the display, sound and gamepad setup and the frame timing") do
         window_only("--verbose") { @verbose = true }
       end

data/lib/badline/region.rb

@@ -6,8 +6,9 @@ module Badline
   # The timing and geometry a video standard gives the machine.
   module Region
     # The CPU clock, the VIC's raster, where the beam is blanked, the display
-    # window's edges, the part of the raster a front end shows, and the
-    # mains frequency that feeds the CIAs' TOD pins.
+    # window's edges, the part of the raster a front end shows, the mains
+    # frequency that feeds the CIAs' TOD pins, and where the VIC's sprite
+    # fetches and X counter sit in the line.
     #
     # Columns are the VIC's cycles within a line, counted from 0, and a
     # column draws 8 pixels, so the raster is `cycles_per_line * 8` pixels
@@ -16,8 +17,15 @@ module Badline
     # is the larger. `display_x_bounds` holds the display window's
     # [left, right] pixels per CSEL state, 38 columns then 40, and `crop`
     # the [left, top, width, height] a front end shows.
+    #
+    # `sprite_cycle` is Bauer's cycle for sprite 0's p-access, and each
+    # sprite after it takes two more. `sprite_display_cycle` is the cycle
+    # that turns a sprite's display on or off. `x_hold` is how many pixels
+    # the X counter spends past its run, repeating $184-$187, and a raster
+    # of more than 512 pixels needs them.
     Profile = Data.define(:name, :clock_hz, :cycles_per_line, :lines_per_frame, :hblank, :vblank,
-                          :display_x_bounds, :crop, :mains_hz)
+                          :display_x_bounds, :crop, :mains_hz, :sprite_cycle, :sprite_display_cycle,
+                          :x_hold)
 
     # The 6569 of a PAL C64: 63 cycles by 312 lines at 985,248 Hz, with
     # 50 Hz mains.
@@ -25,19 +33,36 @@ module Badline
       name: :pal, clock_hz: 985_248, cycles_per_line: 63, lines_per_frame: 312,
       hblank: [61, 9].freeze, vblank: [300, 15].freeze,
       display_x_bounds: [[135, 438].freeze, [128, 447].freeze].freeze,
-      crop: [96, 20, 384, 272].freeze, mains_hz: 50
+      crop: [96, 20, 384, 272].freeze, mains_hz: 50,
+      sprite_cycle: 58, sprite_display_cycle: 58, x_hold: 0
     )
 
     # The 6567R8 of an NTSC C64: 65 cycles by 263 lines at 1,022,727 Hz,
-    # with 60 Hz mains, and lines 13-40 blanked (Bauer). The machine does
-    # not run it yet: the blanked columns and the display window are PAL's
-    # stand-ins, and the crop leaves out lines 0-12, which show below the
-    # last line.
+    # with 60 Hz mains. The sprite fetches and the compares ahead of them
+    # run a cycle later than on the 6569 (the spritesteal, spritex and
+    # phi1timing testprogs), and the X counter pauses near $184, as Bauer's
+    # 6567R8 diagram shows, reading $184-$187 for 8 pixels more. The
+    # blanked lines are the ones VICE's NTSC view leaves out, 12-27. It shows lines 0-11 below
+    # line 262, and the crop leaves those out.
     NTSC = Profile.new(
       name: :ntsc, clock_hz: 1_022_727, cycles_per_line: 65, lines_per_frame: 263,
-      hblank: [61, 9].freeze, vblank: [13, 40].freeze,
+      hblank: [63, 9].freeze, vblank: [12, 27].freeze,
+      display_x_bounds: [[135, 438].freeze, [128, 447].freeze].freeze,
+      crop: [96, 28, 384, 235].freeze, mains_hz: 60,
+      sprite_cycle: 59, sprite_display_cycle: 59, x_hold: 8
+    )
+
+    # The 6567R56A of the first NTSC C64s: 64 cycles by 262 lines at
+    # 1,022,727 Hz. Its sprite fetches run a cycle later than the 6569's,
+    # as on the 6567R8, but it turns the display on in the same cycle as
+    # the 6569, and its X counter runs straight through 512 pixels, one
+    # coordinate for each.
+    NTSC_OLD = Profile.new(
+      name: :ntscold, clock_hz: 1_022_727, cycles_per_line: 64, lines_per_frame: 262,
+      hblank: [62, 9].freeze, vblank: [13, 27].freeze,
       display_x_bounds: [[135, 438].freeze, [128, 447].freeze].freeze,
-      crop: [96, 41, 384, 222].freeze, mains_hz: 60
+      crop: [96, 28, 384, 234].freeze, mains_hz: 60,
+      sprite_cycle: 59, sprite_display_cycle: 58, x_hold: 0
     )
 
     # Whether a column or line lies in a [first, last] blanking span.

data/lib/badline/reu/dma.rb

@@ -0,0 +1,228 @@
+# frozen_string_literal: true
+
+module Badline
+  class REU
+    # One transfer between the C64 and the REU's RAM, clocked a cycle at a
+    # time while the REC holds the bus. The REC only reads the C64's bus
+    # while BA is high, so a read followed by BA low waits for BA to rise.
+    # After a write it goes on through the first BA-low cycle and stops at
+    # the second. See doc/pinned-behaviour.md, REU DMA.
+    class DMA
+      # Transfer types, as the command register's bottom two bits give
+      # them.
+      STASH = 0
+      FETCH = 1
+      SWAP = 2
+      VERIFY = 3
+
+      # What the REC did on the cycle before.
+      IDLE = 0
+      READ = 1
+      WRITE = 2
+
+      # Where the transfer stopped, what it left for the length register,
+      # and the status bits it ended with.
+      attr_reader :c64, :expansion, :length, :events
+
+      def initialize(ram, span, bus)
+        @ram = ram
+        @span = span
+        @bus = bus
+        @c64 = @expansion = @length = @events = 0
+        @holding = false
+      end
+
+      # Whether the REC held the bus on the last cycle clocked, which it
+      # does while it waits for BA too, since the CPU stays halted.
+      def holds_bus? = @holding
+
+      # A length of 0 moves 64K. control is the address control register,
+      # which can hold either address where it is.
+      def start(type, c64, expansion, length, control)
+        @type = type
+        @c64 = c64
+        @expansion = expansion
+        @length = length.zero? ? 0x10000 : length
+        @c64_step = control.anybits?(FIX_C64) ? 0 : 1
+        @expansion_step = control.anybits?(FIX_EXPANSION) ? 0 : 1
+        @events = 0
+        @holding = true
+        @last = IDLE
+        @waiting = false
+        @ba_low_after_writes = 0
+        @stopped_after_write = false
+        @swap_write_due = false
+        @swap_byte = 0
+        @held_read = 0
+        @moved_all = false
+        @extra_cycle = false
+      end
+
+      # One cycle of the transfer. The cycle the REC lets go of the bus on
+      # is the CPU's.
+      def cycle!(ba_low)
+        note_ba(ba_low)
+        settle_held_read(ba_low) if @held_read.positive?
+        return if @waiting && ba_low
+
+        @waiting = false
+        @moved_all ? wind_down : move(ba_low)
+      end
+
+      private
+
+      # The second BA-low cycle in a row after writes stops the REC, and so
+      # does any BA-low cycle after a read. It then waits for BA to rise.
+      def note_ba(ba_low)
+        if @last == READ
+          @waiting = ba_low
+        elsif @last == WRITE
+          @ba_low_after_writes = ba_low ? @ba_low_after_writes + 1 : 0
+          @stopped_after_write = @ba_low_after_writes == 2
+          if @stopped_after_write
+            @waiting = true
+            @ba_low_after_writes = 0
+          end
+        end
+        @last = IDLE
+      end
+
+      # A fetch or a swap whose last write ran into BA, or a verify that
+      # found a difference before its last byte, takes one more cycle before
+      # the REC lets go of the bus.
+      def wind_down
+        if @extra_cycle || (@stopped_after_write && (@type == FETCH || @type == SWAP))
+          @extra_cycle = @stopped_after_write = false
+          @last = READ
+          return
+        end
+
+        @holding = false
+        settle
+      end
+
+      def move(ba_low)
+        case @type
+        when STASH then stash
+        when FETCH then fetch
+        when SWAP then swap(ba_low)
+        else verify
+        end
+      end
+
+      # The REU's data bus latch keeps the last byte the REC stored.
+      def stash
+        byte = read_c64
+        @ram.poke(@expansion, byte)
+        @ram.latch = byte
+        step
+        @last = READ
+      end
+
+      def fetch
+        byte = @ram.peek(@expansion)
+        @ram.latch = byte
+        write_c64(byte)
+        step
+        @last = WRITE
+      end
+
+      # Two cycles a byte: the C64's byte is read and stored while the
+      # REU's is fetched, and the REU's is written to the C64 on the next.
+      def swap(ba_low)
+        if @swap_write_due
+          @swap_write_due = false
+          write_c64(@swap_byte)
+          step
+          @last = WRITE
+          return
+        end
+
+        @swap_byte = @ram.peek(@expansion)
+        @swap_write_due = true
+        @last = READ
+        return swap_read_on_ba if ba_low
+
+        @ram.poke(@expansion, read_c64)
+      end
+
+      # A swap's read on the first BA-low cycle after a write, while AEC is
+      # still high. On the last byte the read is made there, the write
+      # follows on the next cycle whatever BA does, and the REC lets go.
+      # Otherwise the read stays open and takes what is on the bus two
+      # cycles later, or on the cycle BA rises if that comes first. Pinned
+      # by REU/reutiming2/e5-m2, f3-m2 and f4-m2.
+      def swap_read_on_ba
+        return @held_read = 2 unless @length == 1
+
+        @ram.poke(@expansion, read_c64)
+        @last = IDLE
+        @ba_low_after_writes = 0
+      end
+
+      def settle_held_read(ba_low)
+        @held_read -= 1
+        return if @held_read.positive? && ba_low
+
+        @held_read = 0
+        @ram.poke(@expansion, read_c64)
+      end
+
+      # A difference ends the transfer, with one cycle more if bytes were
+      # left to compare.
+      def verify
+        same = @ram.peek(@expansion) == read_c64
+        step
+        @last = READ
+        return if same
+
+        @events |= FAULT
+        @extra_cycle = @length.positive?
+        @moved_all = true
+      end
+
+      # The REC reaches C64 memory as the CPU sees it, but at $00 and $01
+      # it reaches the RAM under the CPU's port.
+      def read_c64
+        @c64 < 0x02 ? @bus.ram.peek(@c64) : @bus.peek(@c64)
+      end
+
+      def write_c64(byte)
+        @c64 < 0x02 ? @bus.ram.poke(@c64, byte) : @bus.poke(@c64, byte)
+      end
+
+      # The REC counts the expansion address in its 19 low bits, from the
+      # top of its span back to 0, and leaves the bank bits above them as
+      # they were.
+      def step
+        @c64 = (@c64 + @c64_step) & 0xffff
+        low = (@expansion & 0x7ffff) + @expansion_step
+        @expansion = (@expansion & 0xf80000) | (low == @span ? 0 : low)
+        @length -= 1
+        @moved_all = true if @length.zero?
+      end
+
+      # The length register is left at 1 after a whole block. A fetch has
+      # already fetched the byte after its last into the latch.
+      def settle
+        return settle_verify if @type == VERIFY
+
+        @length += 1
+        @events |= END_OF_BLOCK
+        @ram.latch = @ram.peek(@expansion) if @type == FETCH
+      end
+
+      # A verify that compared every byte ends the block. One that found a
+      # difference on the byte before the last compares the last too, and
+      # ends the block if that one is the same.
+      def settle_verify
+        if @length.zero?
+          @length = 1
+          @events |= END_OF_BLOCK
+        elsif @length == 1 && @ram.peek(@expansion) == read_c64
+          @events |= END_OF_BLOCK
+        end
+      end
+    end
+  end
+end

data/lib/badline/reu/ram.rb

@@ -0,0 +1,65 @@
+# frozen_string_literal: true
+
+module Badline
+  class REU
+    # The REU's DRAM, as the REC addresses it. The REC counts 19 address
+    # bits, 17 on the 1700, and the 1764 fills only the first 256K of
+    # them: past that a read finds the latch on the REU's data bus, which
+    # holds the last byte the REC moved. A unit past 512K takes its upper
+    # address lines from the bank register.
+    class RAM
+      BANK_SIZE = 0x10000
+
+      # Where a bank of a 1764 that has just been switched on reads
+      # inverted, over the first 128K of each 256K. Over the second 128K
+      # it is the rest of the bank that reads inverted. Measured from
+      # REU/raminitpattern/dumpfile-256k-x1541.bin, a real 1764's dump.
+      INVERTED = [0x2a00...0x5400, 0x8000...0xac00, 0xd600...0x10000].freeze
+
+      attr_reader :size
+      attr_accessor :latch
+
+      def initialize(size, span)
+        @size = size
+        @mask = (size > 0x80000 ? size : span) - 1
+        @banks = Array.new(size / BANK_SIZE) { [] }
+        @power_on = [[], []]
+        @latch = 0xff
+      end
+
+      def peek(addr)
+        addr &= @mask
+        addr < @size ? bank(addr >> 16)[addr & 0xffff] : @latch
+      end
+
+      def poke(addr, value)
+        addr &= @mask
+        bank(addr >> 16)[addr & 0xffff] = value if addr < @size
+      end
+
+      private
+
+      # A bank takes its power-on contents the first time it is touched,
+      # so an REU costs only the memory a program uses.
+      def bank(number)
+        bank = @banks[number]
+        return bank unless bank.empty?
+
+        half = (number >> 1) & 1
+        @power_on[half] = power_on_bank(half == 1) if @power_on[half].empty?
+        @banks[number] = @power_on[half].dup
+      end
+
+      # Pairs of $FF and $00 bytes, starting with a single $FF, and each
+      # odd page the inverse of the even one before it.
+      def power_on_bank(upper)
+        Array.new(BANK_SIZE) do |offset|
+          byte = (offset + 1).anybits?(2) ? 0x00 : 0xff
+          byte ^= 0xff if offset.anybits?(0x100)
+          inverted = INVERTED.any? { |range| range.cover?(offset) }
+          inverted == upper ? byte : byte ^ 0xff
+        end
+      end
+    end
+  end
+end

data/lib/badline/reu/trigger.rb

@@ -0,0 +1,32 @@
+# frozen_string_literal: true
+
+module Badline
+  class REU
+    # Stands in for the page at $FF00 in the write table, passing each
+    # write on to what is mapped there and telling the REC when $FF00 is
+    # written, which starts an armed transfer.
+    class Trigger
+      ADDRESS = 0xff00
+
+      def initialize(reu)
+        @reu = reu
+        @target = nil
+      end
+
+      # Puts the trigger in front of target and returns it.
+      def wrap(target)
+        @target = target
+        self
+      end
+
+      def peek(addr)
+        @target.peek(addr)
+      end
+
+      def poke(addr, value)
+        @target.poke(addr, value)
+        @reu.ff00_written if addr == ADDRESS
+      end
+    end
+  end
+end