badline 0.4.2 → 0.5.1

data/lib/badline/drive1541/sleep.rb

@@ -0,0 +1,114 @@
+# frozen_string_literal: true
+
+module Badline
+  class Drive1541
+    # The drive asleep, as Idle and Orbit let it: host_cycle! counts the
+    # host cycles that go by, and waking turns them into drive cycles
+    # through the phase accumulator and runs them. Whole orbits and whole
+    # passes go in bulk, and the rest cycle by cycle, which may find the
+    # idle loop and put the drive back to sleep.
+    #
+    # The drive looks at ATN only when the C64 may have moved it, on a
+    # bus that says when (IECBus#notifies?), and every host cycle on one
+    # that doesn't.
+    module Sleep
+      # Whether the drive is skipping its idle loop right now.
+      def asleep? = @asleep
+
+      # Brings the drive up to the present, cycle for cycle, and drops the
+      # pass it was recording and the orbits it found, since whoever called
+      # may change it. Every reader of the drive's parts calls this.
+      def settle!
+        if @asleep
+          wake!
+          @serial_port.latch_host
+          @asleep = false
+          @orbit_cycles = nil
+        end
+        stop_recording if @recording
+        forget_orbits
+      end
+
+      private
+
+      def init_sleep
+        @asleep = false
+        @host_still = false
+        @owed = 0
+        @budget = 0
+        @slept = 0
+        @wake_at = 0
+      end
+
+      # A host cycle asleep that may wake the drive. The bus says whether
+      # the next ones need a look at ATN.
+      def doze
+        @host_still = @serial_bus.notifies?
+        if @serial_port.atn_moved?
+          settle!
+        elsif @slept == @wake_at
+          wake!
+          @serial_port.latch_host
+          plan_wake if @asleep
+        end
+      end
+
+      # Asleep, host_cycle! counts host cycles, and leaves it to wake! to
+      # turn them into drive cycles through the phase accumulator. This sets
+      # the host cycle that brings the drive cycles owed up to the budget.
+      # On an orbit the drive sleeps until something outside wakes it:
+      # @slept counts from 1, so it never comes to 0.
+      def plan_wake
+        @slept = 0
+        return @wake_at = 0 if @orbit_cycles
+
+        needed = ((@budget - @owed) * @host_clock_hz) - @phase
+        @wake_at = needed.positive? ? (needed + CLOCK_HZ - 1) / CLOCK_HZ : 1
+      end
+
+      # Runs the cycles owed.
+      def wake!
+        phase = @phase + (@slept * CLOCK_HZ)
+        @phase = phase % @host_clock_hz
+        owed = @owed + (phase / @host_clock_hz)
+        @owed = 0
+        @slept = 0
+        catch_up(owed)
+      end
+
+      # Runs +owed+ drive cycles: whole orbits and whole passes in bulk,
+      # passes only up to the budget, and the rest cycle by cycle, which
+      # may put the drive back to sleep.
+      def catch_up(owed)
+        while owed.positive?
+          if @asleep
+            if @orbit_cycles && owed >= @orbit_cycles
+              owed -= skip_orbits(owed / @orbit_cycles)
+              next
+            end
+            @orbit_cycles = nil
+            passes = [owed, @budget].min / @pass_cycles
+            if passes.positive?
+              owed -= skip_passes(passes)
+              next
+            end
+            @asleep = false
+          end
+          run_cycle
+          owed -= 1
+        end
+      end
+
+      # Runs whole passes, moving the counters on. Returns the cycles.
+      def skip_passes(passes)
+        cycles = passes * @pass_cycles
+        @cpu.fast_forward(cycles, passes * @pass_instructions)
+        @via1.fast_forward(cycles)
+        @via2.fast_forward(cycles)
+        @cycles += cycles
+        @budget -= cycles
+        cycles
+      end
+    end
+  end
+end

data/lib/badline/drive1541/track.rb

@@ -0,0 +1,98 @@
+# frozen_string_literal: true
+
+module Badline
+  class Drive1541
+    # One ring of flux on the disk, as the GCR bytes the head reads from it,
+    # most significant bit first, and the speed zone it was written in
+    # (0-3). The bytes wrap around: the last one's bits run into the
+    # first's. A track is as long as its bytes, which is what a .g64 image
+    # stores for each half track.
+    #
+    # The disk turns at 300 rpm, so every track passes under the head in
+    # the same 200 ms, and its bits pass at the rate they were written at.
+    # Each bit is a cell of time, starting at the track's index angle with
+    # the first byte's top bit, and a 1 bit is a flux transition at the
+    # start of its cell. The cells are spread evenly over the turn, so a
+    # track as long as a turn holds at its zone's rate
+    # (Disk::TRACK_LENGTHS) passes at that rate, within the part of a byte
+    # the length rounds off, and a longer or shorter one faster or slower.
+    # A .g64 speed map gives each byte the zone it was written in, and the
+    # cells of each byte are as wide as their zone's, scaled together to
+    # fill the turn.
+    #
+    # Times are in TICKs, 1/65536 of a tick of the drive's 16 MHz crystal,
+    # so the cells add up to a turn within a tick.
+    class Track
+      TICK = 1 << 16
+      TURN = 200_000 * 16 * TICK
+
+      # A bit cell at the zone's rate, in TICKs.
+      def self.cell(zone) = 4 * (16 - zone) * TICK
+
+      attr_reader :bytes, :zone, :speeds, :width, :widths
+
+      # +speeds+ holds each byte's zone, where the track's rate changes
+      # along it.
+      def initialize(bytes, zone, speeds = nil)
+        @bytes = bytes
+        @zone = zone
+        @speeds = speeds
+        @widths = speeds && scaled_widths(speeds)
+        @width = speeds ? @widths[0] : TURN / (bytes.length * 8)
+      end
+
+      def length = @bytes.length
+
+      # Whether the whole track was written at the +zone+'s rate.
+      def written_at?(zone) = @widths.nil? && @zone == zone
+
+      # The bit cell under the head +time+ TICKs into the turn, as
+      # [byte, mask, the time the cell ends].
+      def cell_at(time)
+        start = 0
+        index = 0
+        if @widths
+          while index < length - 1 && time >= start + (@widths[index] * 8)
+            start += @widths[index] * 8
+            index += 1
+          end
+        else
+          index = [time / (@width * 8), length - 1].min
+          start = index * @width * 8
+        end
+        width = @widths ? @widths[index] : @width
+        bit = [(time - start) / width, 7].min
+        cell_end = index == length - 1 && bit == 7 ? TURN : start + ((bit + 1) * width)
+        [index, 0x80 >> bit, cell_end]
+      end
+
+      # The track laid out again as one turn at the +zone+'s rate, each
+      # flux transition in the cell under it.
+      def relaid(zone)
+        bits = Disk::TRACK_LENGTHS[zone] * 8
+        cell = TURN / bits
+        relaid = Array.new(bits / 8, 0)
+        time = 0
+        @bytes.each_with_index do |byte, index|
+          width = @widths ? @widths[index] : @width
+          8.times do |bit|
+            if byte.anybits?(0x80 >> bit)
+              cell_index = [time / cell, bits - 1].min
+              relaid[cell_index >> 3] |= 0x80 >> (cell_index & 7)
+            end
+            time += width
+          end
+        end
+        Track.new(relaid, zone)
+      end
+
+      private
+
+      def scaled_widths(speeds)
+        units = 0
+        speeds.each { |zone| units += 16 - zone }
+        speeds.map { |zone| TURN * (16 - zone) / (units * 8) }
+      end
+    end
+  end
+end

data/lib/badline/drive1541.rb

@@ -0,0 +1,234 @@
+# frozen_string_literal: true
+
+require "badline/drive1541/bus"
+require "badline/drive1541/serial_port"
+require "badline/drive1541/gcr"
+require "badline/drive1541/track"
+require "badline/drive1541/disk"
+require "badline/drive1541/mechanism"
+require "badline/drive1541/disk_via"
+require "badline/drive1541/sleep"
+require "badline/drive1541/idle"
+require "badline/drive1541/orbit"
+
+module Badline
+  # The 1541 disk drive as a machine of its own: a 6502 running the DOS
+  # ROM at 1 MHz, with 2 KB of RAM and two VIAs on its bus. VIA 1 faces
+  # the serial bus and VIA 2 the disk mechanism.
+  #
+  # The drive runs on its own crystal, so it clocks against the host's
+  # clock through a fractional accumulator: each host cycle adds 1 MHz
+  # worth of phase, and every whole host period in it runs a drive cycle.
+  # Against the PAL C64's 985,248 Hz that's one drive cycle per host cycle
+  # and a second one about every 67. The host sets its clock on attaching
+  # the drive, and until then the drive runs one cycle per host cycle.
+  #
+  # VIA 2's port B runs the Mechanism, which reads a Disk put in with
+  # insert.
+  #
+  # While the DOS idles, host_cycle! skips the drive's cycles and catches
+  # up on them later, exactly (see Idle). The readers of the drive's parts
+  # catch up first, so they find the drive as running every cycle would
+  # have left it. Once the DOS's timer interrupts come round, the drive
+  # sleeps through them too (see Orbit).
+  class Drive1541
+    include Sleep
+    include Idle
+    include Orbit
+
+    CLOCK_HZ = 1_000_000
+
+    attr_reader :device, :serial_bus
+
+    def cpu
+      settle!
+      @cpu
+    end
+
+    def bus
+      settle!
+      @bus
+    end
+
+    def via1
+      settle!
+      @via1
+    end
+
+    def via2
+      settle!
+      @via2
+    end
+
+    def mechanism
+      settle!
+      @mechanism
+    end
+
+    def cycles
+      settle!
+      @cycles
+    end
+
+    def ram = bus.ram
+
+    def host_clock_hz=(clock_hz)
+      settle!
+      @host_clock_hz = clock_hz
+    end
+
+    # +rom+ covers $C000-$FFFF, and defaults to the DOS image in the ROM
+    # path. +device+ is the number the jumpers on VIA 1's PB5 and PB6 set,
+    # 8 to 11.
+    def initialize(rom: nil, host_clock_hz: CLOCK_HZ, device: 8, debug: false)
+      @device = device
+      @serial_port = SerialPort.new(device:)
+      @via1 = VIA.new(start: 0x1800, peripheral: @serial_port)
+      @mechanism = Mechanism.new(self)
+      @via2 = DiskVIA.new(start: 0x1c00, mechanism: @mechanism)
+      @bus = Bus.new(rom: rom || ROM.load("dos1541.rom", 0xc000), via1: @via1, via2: @via2)
+      @cpu = CPU.new(@bus, debug:)
+      @host_clock_hz = host_clock_hz
+      @phase = 0
+      @cycles = 0
+      @so_pending = false
+      @serial_bus = nil
+      init_idle(debug)
+      # CA1 powers up at the level of a released ATN, without an edge.
+      @via1.ca1 = false
+      @via1.reset!
+      connect(IECBus.new)
+    end
+
+    # Plugs the drive into a serial bus, leaving the one it was on. A drive
+    # starts out on a bus of its own, with nothing else on it.
+    def connect(serial_bus)
+      settle!
+      @serial_bus&.detach(self)
+      @serial_bus = serial_bus
+      @serial_port.bus = serial_bus
+      serial_bus.attach(self)
+      @via1.ca1 = @serial_port.atn_low?
+    end
+
+    # Puts a Disk in the drive (Disk.from_d64 makes one from an image).
+    # Nil takes the disk out.
+    def insert(disk)
+      settle!
+      @mechanism.insert(disk)
+    end
+
+    def disk = mechanism.disk
+
+    # Whether the LED is lit. Reading it leaves the drive asleep: the LED
+    # is the same at the end of every pass the drive sleeps through.
+    def led_on? = @mechanism.led_on?
+
+    # VIA 1's port B as it drives the serial bus. It holds still while the
+    # drive sleeps, so reading it leaves the drive asleep.
+    def serial_output = @via1.port_b_output
+
+    # Stores what the head wrote since the motor last stopped in the
+    # disk's image, as the motor stopping does.
+    def flush
+      settle!
+      @mechanism.flush
+    end
+
+    # The serial bus's RESET line reaches the CPU and both VIAs. RAM keeps
+    # its contents.
+    def reset!
+      settle!
+      @via1.reset!
+      @via2.reset!
+      @cpu.reset!
+    end
+
+    # Runs the drive cycles that fall in one host cycle: none, one or two.
+    # The host has run this cycle already, and the drive sees what it did
+    # from the next one on (see SerialPort). Asleep, the drive owes the
+    # cycles instead, until ATN moves or its counters are due (see Idle).
+    # It looks at ATN only after the C64 wrote CIA 2's port A, on a bus
+    # that says so (see host_written!).
+    def host_cycle!
+      if @asleep
+        return if (@slept += 1) != @wake_at && @host_still
+
+        return doze
+      end
+
+      phase = @phase + CLOCK_HZ
+      while phase >= @host_clock_hz
+        @asleep ? @owed += 1 : run_cycle
+        phase -= @host_clock_hz
+      end
+      @phase = phase
+      settle! if @serial_port.atn_moved?
+      @serial_port.latch_host
+      plan_wake if @asleep
+    end
+
+    # The C64 wrote CIA 2's port A, so ATN may have moved.
+    def host_written!
+      @host_still = false
+    end
+
+    # Runs one drive cycle, catching up first on any the drive owes (see
+    # step).
+    def cycle!
+      settle!
+      step
+    end
+
+    def inspect
+      "#<#{self.class.name} cycles=#{cycles} cpu=(#{cpu.inspect})>"
+    end
+
+    # The read electronics signal a whole GCR byte. BYTE READY pulls VIA 2's
+    # CA1 low, a falling edge that sets its flag and, with latching on,
+    # latches port A. It reaches the CPU's SO pin while VIA 2's CA2 (SOE)
+    # is high, which lets the DOS spin on BVC for each byte. The CPU
+    # samples SO on the next cycle (see step).
+    def byte_ready!
+      @via2.ca1 = false
+      @so_pending = true if @via2.ca2_output
+    end
+
+    # BYTE READY lets go of CA1 with the next bit.
+    def byte_ready_ended!
+      @via2.ca1 = true
+    end
+
+    private
+
+    # A drive cycle from host_cycle!, which may find the idle loop.
+    def run_cycle
+      step
+      idle_loop_reached if @cpu.program_counter == IDLE_LOOP && @idle_skip
+    end
+
+    # One drive cycle. The VIAs clock ahead of the CPU, as the C64's chips
+    # do, and either one pulls IRQ. Nothing drives NMI on the 1541. The CPU
+    # runs whether or not the motor turns, since it answers ATN.
+    #
+    # The disk mechanism runs first, so BYTE READY lands on the VIA ahead
+    # of the CPU's cycle. The CPU samples SO a cycle late: BYTE READY sets
+    # V for the next cycle's instruction step.
+    #
+    # ATN reaches VIA 1's CA1 through the same inverter as PB7, so CA1 goes
+    # high as the C64 asserts ATN, as the serial port sees it: from the
+    # host cycle after the one that asserts it.
+    def step
+      so = @so_pending
+      @so_pending = false
+      @mechanism.cycle!
+      @via1.ca1 = @serial_port.atn_low?
+      @via1.cycle!
+      @via2.cycle!
+      @cpu.irq = @via1.irq? || @via2.irq?
+      @cpu.so! if so
+      @cpu.cycle!
+      @cycles += 1
+    end
+  end
+end

data/lib/badline/gui/application.rb

@@ -28,15 +28,20 @@ module Badline
       }.freeze
       MOUSE_BUTTONS = { 1 => :left, 3 => :right }.freeze
 
-      # The media options (autostart:, song:, disk:) go to Media.attach.
-      def initialize(media_path: nil, sid_model: nil, sound: false, verbose: false, **media)
+      # The machine options (sid_model:, reu:, true_drive:, ntsc:) build
+      # the machine: reu plugs in an REU of that many K, true_drive puts a
+      # true 1541 on device 8, and ntsc makes it an NTSC C64. The media
+      # options (autostart:, song:, disk:) go to Media.attach.
+      def initialize(media_path: nil, machine: {}, sound: false, verbose: false, **media)
         @verbose = verbose
-        @computer = Computer.new(sid_model: sid_model || Media.sid_model(media_path))
+        @computer = Computer.new(**machine_options(machine, media_path))
+        Media::TrueDrive.plug(@computer) if machine[:true_drive]
         puts Media.attach(@computer, media_path, **media) if media_path
 
         @mode = :keyboard
         @pot_device = nil
         @panes = [ScreenPane.new(@computer)]
+        @panes << DriveLedPane.new(@computer.drive1541, @panes.first) if @computer.drive1541
         @stream = open_stream if sound
         @paced = ENV["NOVSYNC"].nil?
         @window = Window.new(
@@ -60,6 +65,7 @@ module Badline
           @stream.pace(@frame_seconds) if @stream && @paced
         end
       ensure
+        @computer.drive1541&.flush
         @stream&.close
         @gamepads.close
         @window.close
@@ -163,6 +169,12 @@ module Badline
         warn "badline: no sound, can't open the audio device: #{e.message}"
       end
 
+      def machine_options(machine, media_path)
+        options = { sid_model: machine[:sid_model] || Media.sid_model(media_path), **machine.slice(:reu) }
+        options[:region] = Region::NTSC if machine[:ntsc]
+        options
+      end
+
       def fit_frame
         rate = @window.refresh_rate
         clock_hz = @computer.region.clock_hz

data/lib/badline/gui/drive_led_pane.rb

@@ -0,0 +1,29 @@
+# frozen_string_literal: true
+
+module Badline
+  module GUI
+    # The true drive's red LED, in the bottom right corner of the screen
+    # pane's border: bright while the DOS lights it, as it does while a file
+    # is open or after an error, and dim otherwise.
+    class DriveLedPane < Pane
+      WIDTH = 12
+      HEIGHT = 4
+
+      LIT = [0xff, 0x20, 0x20].freeze
+      DARK = [0x40, 0x00, 0x00].freeze
+
+      def initialize(drive, screen)
+        super(width: WIDTH, height: HEIGHT,
+              left: screen.left + screen.width - WIDTH - 8, top: screen.top + screen.height - HEIGHT - 6)
+        @drive = drive
+      end
+
+      def color = @drive.led_on? ? LIT : DARK
+
+      def render(renderer)
+        SDL::SetRenderDrawColor.call(renderer, *color, 0xff)
+        SDL::RenderFillRect.call(renderer, @rect)
+      end
+    end
+  end
+end

data/lib/badline/gui.rb

@@ -8,5 +8,6 @@ require "badline/gui/joy_map"
 require "badline/gui/gamepads"
 require "badline/gui/pane"
 require "badline/gui/screen_pane"
+require "badline/gui/drive_led_pane"
 require "badline/gui/window"
 require "badline/gui/application"

data/lib/badline/iec_bus.rb

@@ -0,0 +1,109 @@
+# frozen_string_literal: true
+
+module Badline
+  # The serial bus between the C64 and its drives: ATN, CLK and DATA, each
+  # an open-collector line with a pull-up. A line is low while any device
+  # pulls it (wired-AND), and high otherwise. The bus holds no state of its
+  # own: every read works the levels out from what each side drives now.
+  #
+  # The C64 drives the lines from CIA 2's port A through 7406 inverters, so
+  # an output bit of 1 pulls its line low: PA3 ATN, PA4 CLK and PA5 DATA.
+  # PA6 and PA7 read CLK and DATA directly, 1 for a released line. The bus
+  # stands in as CIA 2's peripheral for those two inputs.
+  #
+  # A drive drives CLK and DATA from VIA 1's PB3 and PB1, the same way. It
+  # also pulls DATA while ATN IN differs from its ATN acknowledge on PB4
+  # (an XOR gate), which answers ATN in hardware before the DOS gets to it.
+  # SerialPort reads the lines back into VIA 1.
+  class IECBus
+    # CIA 2 port A
+    HOST_ATN_OUT = 0x08
+    HOST_CLK_OUT = 0x10
+    HOST_DATA_OUT = 0x20
+    HOST_CLK_IN = 0x40
+    HOST_DATA_IN = 0x80
+
+    # VIA 1 port B
+    DRIVE_DATA_OUT = 0x02
+    DRIVE_CLK_OUT = 0x08
+    DRIVE_ATNA = 0x10
+
+    # The lines pulled low, as ATN, CLK and DATA bits
+    ATN = 0x01
+    CLK = 0x02
+    DATA = 0x04
+
+    attr_reader :host, :drives
+
+    # +host+ is CIA 2, or nil for a bus with only drives on it.
+    def initialize(host: nil)
+      @host = host
+      @drives = []
+      @notifies = false
+    end
+
+    # Stands in as the host's peripheral, CIA 2's, and has it say when it
+    # writes port A (see notifies?).
+    def plug_in!
+      @host.peripheral = self
+      @host.on_port_a_write { host_written }
+      @notifies = true
+    end
+
+    # Whether the host says when it may have moved a line (see plug_in!).
+    # Without, a drive asleep checks ATN every cycle.
+    def notifies? = @notifies
+
+    # CIA 2 wrote its port A, which may have moved a line.
+    def host_written = @drives.each(&:host_written!)
+
+    def attach(drive)
+      @drives << drive unless @drives.include?(drive)
+    end
+
+    def detach(drive)
+      @drives.delete(drive)
+    end
+
+    # One pass over everything on the bus, for a reader that wants more
+    # than one line. +host+ is the C64's port A lines as the reader sees
+    # them, which a drive takes a cycle late (see Drive1541::SerialPort).
+    def low_lines(host = host_lines)
+      atn = host.anybits?(HOST_ATN_OUT)
+      low = atn ? ATN : 0
+      low |= CLK if host.anybits?(HOST_CLK_OUT)
+      low |= DATA if host.anybits?(HOST_DATA_OUT)
+      i = 0
+      while i < @drives.length
+        drive = @drives[i].serial_output
+        low |= CLK if drive.anybits?(DRIVE_CLK_OUT)
+        low |= DATA if drive.anybits?(DRIVE_DATA_OUT) || atn != drive.anybits?(DRIVE_ATNA)
+        i += 1
+      end
+      low
+    end
+
+    def atn_low?(host = host_lines) = host.anybits?(HOST_ATN_OUT)
+
+    def clk_low? = low_lines.anybits?(CLK)
+
+    def data_low? = low_lines.anybits?(DATA)
+
+    # CIA 2's port A pins as the bus leaves them: CLK IN and DATA IN low
+    # while their lines are.
+    def read_a(_port_a, _port_b)
+      low = low_lines
+      value = 0xff
+      value &= ~HOST_CLK_IN if low.anybits?(CLK)
+      value &= ~HOST_DATA_IN if low.anybits?(DATA)
+      value
+    end
+
+    # Port B goes to the user port, not the serial bus.
+    def read_b(_port_a, _port_b) = 0xff
+
+    # What the C64 pulls, as port A bits: its output bits, with input bits
+    # floating high as the 7406 inputs see them.
+    def host_lines = @host ? @host.port_a_lines : 0
+  end
+end

data/lib/badline/kernal_trap/channel.rb

@@ -53,8 +53,12 @@ module Badline
       # a LOAD (secondary address 0) opens at $7E and $026F of its memory,
       # and a LOAD of a name starting with "*" reopens that file rather than
       # the first one on the disk. Loaders write the block there with M-W
-      # to load a file the directory doesn't list.
+      # to load a file the directory doesn't list. A LOAD of "$" reads the
+      # directory as a BASIC program, which a pattern after a colon narrows
+      # to the files it names.
       def self.for_name(storage, memory, secondary, name, type)
+        return new(storage.directory.bytes(name)) if listing?(storage, secondary, name)
+
         file = Storage.parse_name(name).first
         return for_file(storage, file, type) unless secondary.zero? && storage.respond_to?(:first_block)
 
@@ -66,6 +70,10 @@ module Badline
         for_file(storage, file, type)
       end
 
+      def self.listing?(storage, secondary, name)
+        secondary.zero? && name.start_with?("$") && storage.respond_to?(:directory)
+      end
+
       # The file whose chain starts at the block.
       def self.at_block(storage, track, sector)
         data = storage.read_file_at(track, sector)