badline 0.2.0 → 0.3.0

data/lib/badline/kernal_trap/serial.rb

@@ -23,6 +23,7 @@ module Badline
       CLOSE = 0xe0
 
       # ST bits at $90
+      DEVICE_NOT_PRESENT = 0x80
       EOI = 0x40
       READ_TIMEOUT = 0x02
 
@@ -41,13 +42,26 @@ module Badline
 
       def install
         ROUTINES.each do |address, routine|
-          @cpu.install_trap(address) { send(routine) if kernal? }
+          @cpu.install_trap(address) { call_routine(routine) if kernal? }
         end
         self
       end
 
       private
 
+      def call_routine(routine)
+        case routine
+        when :talk then talk
+        when :listen then listen
+        when :second then second
+        when :tksa then tksa
+        when :ciout then ciout
+        when :untalk then untalk
+        when :unlisten then unlisten
+        when :acptr then acptr
+        end
+      end
+
       # Addressing the bus starts a new frame. The channel number arrives
       # in the secondary address that follows.
       def talk
@@ -82,22 +96,40 @@ module Badline
         return unless @listening
 
         @buffer << @cpu.a
+        update_status(DEVICE_NOT_PRESENT) unless accepted?
         @cpu.status.carry = false
         return_to_caller
       end
 
+      # The drive acknowledges every byte of an open or close frame, but
+      # takes data only on a channel it has open. Otherwise nothing holds
+      # the data line when a byte starts, so the KERNAL finds no device.
+      def accepted?
+        [OPEN, CLOSE].include?(@frame) || @drive.listening?(@listen_channel)
+      end
+
       def unlisten
         return unless @listening
 
         @listening = false
         deliver_frame
-        return_to_caller
+        release_bus
       end
 
       def untalk
         return unless @talking
 
         @talking = false
+        release_bus
+      end
+
+      # UNLSN and UNTLK end by releasing ATN, the clock and the data line on
+      # CIA 2's port A, and leave the port's last read in the accumulator.
+      def release_bus
+        @bus.poke(0xdd00, @bus.peek(0xdd00) & 0xc7)
+        @cpu.a = @bus.peek(0xdd00) & 0xdf
+        @cpu.status.negative = @cpu.a.anybits?(0x80)
+        @cpu.status.zero = @cpu.a.zero?
         return_to_caller
       end
 

data/lib/badline/media.rb

@@ -59,8 +59,8 @@ module Badline
 
       def start_tune(computer, tune, autostart:, song:)
         computer.ram.write(tune.load_address, tune.data)
-        computer.ram.write(tune.driver_address, tune.driver(song:))
-        computer.type_text("sys#{tune.driver_address}\r") if autostart
+        tune.boot_memory(song:).each { |address, bytes| computer.ram.write(address, bytes) }
+        computer.type_text(tune.boot_command) if autostart
       end
 
       def attach_tape(computer, path, autostart:)

data/lib/badline/memory.rb

@@ -10,11 +10,11 @@ module Badline
     end
 
     def peek(addr)
-      @storage[index(addr)]
+      @storage[offset_of(addr)]
     end
 
     def poke(addr, value)
-      @storage[index(addr)] = value
+      @storage[offset_of(addr)] = value
       value
     end
 
@@ -26,6 +26,11 @@ module Badline
       Array(bytes).each_with_index { |b, i| poke(addr + i, b) }
     end
 
+    # Refills the whole memory as if newly built with `initial`
+    def clear!(initial = [])
+      @storage.replace(zero_fill(initial))
+    end
+
     private
 
     def blank_value

data/lib/badline/rom.rb

@@ -1,17 +1,26 @@
 # frozen_string_literal: true
 
 module Badline
+  class << self
+    attr_writer :rom_path
+
+    # The directory ROM images and other bundled binaries load from.
+    # Defaults to $BADLINE_ROM_PATH, then to the roms directory next to this
+    # file. Assigning nil restores the default.
+    def rom_path
+      @rom_path ||= ENV.fetch("BADLINE_ROM_PATH", File.expand_path("roms", __dir__))
+    end
+  end
+
   class ROM < Memory
     class << self
       def load(filename, start = 0x0)
-        data = File.read(file_path(filename)).bytes
+        data = read(filename)
         new(data, length: data.length, start: start)
       end
 
-      private
-
-      def file_path(filename)
-        File.join(File.dirname(__FILE__), "roms", filename)
+      def read(filename)
+        File.binread(File.join(Badline.rom_path, filename)).bytes
       end
     end
 

data/lib/badline/sid/catch_up.rb

@@ -0,0 +1,110 @@
+# frozen_string_literal: true
+
+module Badline
+  class SID
+    # Running the DSP over the cycles that have passed since it last caught
+    # up, in spans that fast-forward the voices and end on a whole cycle.
+    module CatchUp
+      private
+
+      # Runs the cycles that have passed, landing each queued write on the
+      # cycle the CPU wrote it on.
+      def catch_up
+        replayed = 0
+        i = 0
+        while i < @deferred_writes.length
+          cycle = @deferred_writes[i]
+          run(cycle - replayed)
+          replayed = cycle
+          apply_write(@deferred_writes[i + 1], @deferred_writes[i + 2])
+          i += 3
+        end
+        run(@pending_cycles - replayed)
+        @deferred_writes.clear
+        @pending_cycles = 0
+      end
+
+      def run(cycles)
+        while cycles != 0
+          span = span(cycles)
+          fast_forward(span - 1) if span > 1
+          clock!(span)
+          cycles -= span
+        end
+      end
+
+      # The longest stretch that can be fast-forwarded. A combined waveform
+      # feeding back into its own oscillator steps cycle by cycle, and a span
+      # never runs past an MSB rise that hard-syncs the next voice, so both
+      # land on a whole cycle.
+      def span(cycles)
+        return 1 if @stepped
+
+        span = @synthesizing ? synthesis_span(cycles) : cycles
+        return span unless @synced
+
+        span = sync_span(@waveform1, span)
+        span = sync_span(@waveform2, span)
+        sync_span(@waveform3, span)
+      end
+
+      # The filter steps at most @filter_chunk cycles at a time, and never
+      # across the end of a recorded sample.
+      def synthesis_span(cycles)
+        span = [cycles, @filter_chunk].min
+        return span unless @decimator
+
+        [@decimator.cycles_to_close, span].min
+      end
+
+      # Whether a span has to step, or watch for hard sync, only changes with
+      # a voice's control register.
+      def update_span_rules
+        @stepped = @voices.any? { |voice| voice.waveform.stepped?(@synthesizing) }
+        @synced = @voices.any? { |voice| voice.waveform.sync? }
+      end
+
+      def sync_span(waveform, span)
+        return span unless waveform.sync_dest.sync?
+
+        rise = waveform.cycles_to_msb_rise
+        rise && rise < span ? rise : span
+      end
+
+      # Unrolled over the three voices: the per-cycle block calls cost
+      # measurably on the synthesis path.
+      def fast_forward(cycles)
+        @voice1.fast_forward(cycles)
+        @voice2.fast_forward(cycles)
+        @voice3.fast_forward(cycles)
+      end
+
+      # The last cycle of a span, run whole. The filter integrates the span
+      # from the voices' output at its end.
+      def clock!(span)
+        @voice1.cycle!
+        @voice2.cycle!
+        @voice3.cycle!
+        @waveform1.synchronize!
+        @waveform2.synchronize!
+        @waveform3.synchronize!
+        return unless @synthesizing
+
+        @filter.cycle!(@voices, span)
+        record_sample(span) if @decimator
+      end
+
+      def record_sample(span)
+        sample = @decimator.push(current_sample, span)
+        @samples << sample if sample
+      end
+
+      def current_sample
+        sample = @filter.output / SAMPLE_DIVISOR
+        return sample unless sample < -0x8000 || sample > 0x7fff
+
+        sample.clamp(-0x8000, 0x7fff)
+      end
+    end
+  end
+end

data/lib/badline/sid/decimator.rb

@@ -16,10 +16,11 @@ module Badline
         @phase = 0
         @sum = 0
         @count = 0
+        @cycles_to_close = window_cycles
       end
 
       # Cycles until the current window closes, counting the next one as 1.
-      def cycles_to_close = (@clock_hz - @phase + @rate - 1) / @rate
+      attr_reader :cycles_to_close
 
       # Returns the averaged sample when these cycles close a window, and
       # nil otherwise. They must not run past the window's end.
@@ -27,14 +28,18 @@ module Badline
         @sum += sample * cycles
         @count += cycles
         @phase += @rate * cycles
+        @cycles_to_close -= cycles
         return unless @phase >= @clock_hz
 
         @phase -= @clock_hz
+        @cycles_to_close = window_cycles
         average
       end
 
       private
 
+      def window_cycles = (@clock_hz - @phase + @rate - 1) / @rate
+
       def average
         value = @sum.fdiv(@count).round
         @sum = 0

data/lib/badline/sid/filter.rb

@@ -182,7 +182,7 @@ module Badline
         @unfiltered = 0
         route_voice(voice1.output >> 7, 0x1)
         route_voice(voice2.output >> 7, 0x2)
-        if @routing.anybits?(0x4)
+        if @routing & 0x4 != 0
           @input += voice3.output >> 7
         elsif !@voice3_off
           @unfiltered += voice3.output >> 7
@@ -190,7 +190,7 @@ module Badline
       end
 
       def route_voice(output, bit)
-        if @routing.anybits?(bit)
+        if @routing & bit == bit
           @input += output
         else
           @unfiltered += output
@@ -203,9 +203,9 @@ module Badline
 
       def filtered
         value = 0
-        value += @lowpass  if @mode.anybits?(0x1)
-        value += @bandpass if @mode.anybits?(0x2)
-        value += @highpass if @mode.anybits?(0x4)
+        value += @lowpass  if @mode & 0x1 != 0
+        value += @bandpass if @mode & 0x2 != 0
+        value += @highpass if @mode & 0x4 != 0
         value
       end
     end

data/lib/badline/sid/waveform/fast_forward.rb

@@ -14,11 +14,11 @@ module Badline
           if @test
             bleed_shift_register(cycles)
           else
-            while @shift_pipeline.positive? && cycles.positive?
+            while @shift_pipeline != 0 && cycles != 0
               advance
               cycles -= 1
             end
-            skip_ahead(cycles) if cycles.positive?
+            skip_ahead(cycles) if cycles != 0 && @frequency != 0
             compare_pulse(((@accumulator - @frequency) & 0xffffff) >> 12)
           end
           @stale = true
@@ -59,9 +59,9 @@ module Badline
           previous = @accumulator
           @accumulator += @frequency * cycles
           rises = bit19_rises(previous, @accumulator)
-          if rises.positive?
+          if rises != 0
             @shift_pipeline = pipeline_after(cycles)
-            rises -= 1 if @shift_pipeline.positive?
+            rises -= 1 if @shift_pipeline != 0
             rises.times { shift_noise }
           end
           @accumulator &= 0xffffff
@@ -74,27 +74,27 @@ module Badline
         # How far a rise on one of the last two cycles has come.
         def pipeline_after(cycles)
           last = @accumulator - @frequency
-          return 2 if bit19_rises(last, @accumulator).positive?
-          return 1 if cycles > 1 && bit19_rises(last - @frequency, last).positive?
+          return 2 if bit19_rises(last, @accumulator) != 0
+          return 1 if cycles > 1 && bit19_rises(last - @frequency, last) != 0
 
           0
         end
 
         def drain_floating(cycles)
-          return unless @floating_ttl.positive?
+          return if @floating_ttl.zero?
 
           @floating_ttl -= cycles
-          return if @floating_ttl.positive?
+          return unless @floating_ttl <= 0
 
           @floating_ttl = 0
           @floating = 0x000
         end
 
         def bleed_shift_register(cycles = 1)
-          return unless @shift_register_reset.positive?
+          return if @shift_register_reset.zero?
 
           @shift_register_reset -= cycles
-          return if @shift_register_reset.positive?
+          return unless @shift_register_reset <= 0
 
           @shift_register_reset = 0
           @shift_register = SHIFT_REGISTER_RESET

data/lib/badline/sid/waveform.rb

@@ -218,7 +218,7 @@ module Badline
       def compare_pulse(phase = @accumulator >> 12) = (@pulse = @test || phase >= @pulse_width ? 0xfff : 0x000)
 
       # More than one bit set in the selection.
-      def combined?(selected) = selected.anybits?(selected - 1)
+      def combined?(selected) = selected & (selected - 1) != 0
 
       # The one point in the cycle where the waveform selector drives the DAC:
       # either it latches a fresh value, or nothing drives the line and the
@@ -259,10 +259,10 @@ module Badline
       def advance
         previous = @accumulator
         @accumulator = (previous + @frequency) & 0xffffff
-        @msb_rising = previous.nobits?(MSB) && @accumulator.anybits?(MSB)
-        if previous.nobits?(0x080000) && @accumulator.anybits?(0x080000)
+        @msb_rising = @accumulator & ~previous & MSB != 0
+        if @accumulator & ~previous & 0x080000 != 0
           @shift_pipeline = 2
-        elsif @shift_pipeline.positive? && (@shift_pipeline -= 1).zero?
+        elsif @shift_pipeline != 0 && (@shift_pipeline -= 1).zero?
           write_shift_register(write_back(@selected, @output)) if release_writes_back?(@selected, @selected)
           shift_noise
         end
@@ -277,12 +277,12 @@ module Badline
       # TriXOR = !Saw & ((!V3 & Ring) ^ bit23), where V3 is the modulating
       # voice's MSB (SID/ringmod).
       def inverted?(selected)
-        return false if selected.anybits?(0x2)
+        return false if selected & 0x2 != 0
 
-        msb = @accumulator.anybits?(MSB)
+        msb = @accumulator & MSB != 0
         return msb unless @ring
 
-        msb != @sync_source.accumulator.nobits?(MSB)
+        msb == (@sync_source.accumulator & MSB != 0)
       end
     end
   end

data/lib/badline/sid.rb

@@ -5,6 +5,7 @@ require "badline/sid/envelope"
 require "badline/sid/voice"
 require "badline/sid/filter"
 require "badline/sid/decimator"
+require "badline/sid/catch_up"
 
 module Badline
   # SID (Sound Interface Device) chip, in either the 6581 or the 8580
@@ -31,6 +32,7 @@ module Badline
   # DC offset that the RC network on the C64 board filters out.
   class SID
     include Addressable
+    include CatchUp
 
     VOICES = 3
 
@@ -58,6 +60,7 @@ module Badline
       @bus_ttl_reset = BUS_TTL.fetch(model)
       @filter = Filter.new(model:)
       @synthesizing = false
+      @stepped = @synced = false
       @pending_cycles = 0
       @deferred_writes = []
       @decimator = nil
@@ -78,6 +81,7 @@ module Badline
       @bus_ttl = 0
       @voices.each(&:reset!)
       @filter.reset
+      update_span_rules
     end
 
     # The DSP only counts cycles as they pass. Whatever asks for its state
@@ -90,17 +94,19 @@ module Badline
       return if @synthesizing
 
       @synthesizing = true
+      update_span_rules
       catch_up
     end
 
     # Starts collecting the output, averaged down to `rate` samples a
     # second, for #drain_samples. `filter_chunk` overrides the one the SID
-    # was built with, for a machine that built its own.
-    def record(rate:, filter_chunk: @filter_chunk)
+    # was built with, for a machine that built its own. `clock_hz` is the
+    # rate the SID's cycles are taken to run at.
+    def record(rate:, filter_chunk: @filter_chunk, clock_hz: TimeOfDay::CLOCK_HZ)
       synthesize!
       catch_up
       @filter_chunk = filter_chunk
-      @decimator = Decimator.new(clock_hz: TimeOfDay::CLOCK_HZ, rate:)
+      @decimator = Decimator.new(clock_hz:, rate:)
       @samples = []
     end
 
@@ -152,7 +158,7 @@ module Badline
     end
 
     def peek(addr)
-      case index(addr) % (2**5)
+      case offset_of(addr) % (2**5)
       when 0x19 then latch(pots ? pots.pot_x : 0xff)
       when 0x1a then latch(pots ? pots.pot_y : 0xff)
       when 0x1b then latch(osc3)
@@ -162,7 +168,7 @@ module Badline
     end
 
     def poke(addr, value)
-      reg = index(addr) % (2**5)
+      reg = offset_of(addr) % (2**5)
       write_register(reg, value) if reg <= 0x18
       latch(value)
     end
@@ -172,90 +178,6 @@ module Badline
 
     private
 
-    # Runs the cycles that have passed, landing each queued write on the
-    # cycle the CPU wrote it on.
-    def catch_up
-      replayed = 0
-      @deferred_writes.each do |cycle, reg, value|
-        run(cycle - replayed)
-        replayed = cycle
-        apply_write(reg, value)
-      end
-      run(@pending_cycles - replayed)
-      @deferred_writes.clear
-      @pending_cycles = 0
-    end
-
-    def run(cycles)
-      while cycles.positive?
-        span = span(cycles)
-        fast_forward(span - 1) if span > 1
-        clock!(span)
-        cycles -= span
-      end
-    end
-
-    # The longest stretch that can be fast-forwarded. A combined waveform
-    # feeding back into its own oscillator steps cycle by cycle, and a span
-    # never runs past an MSB rise that hard-syncs the next voice, so both
-    # land on a whole cycle.
-    def span(cycles)
-      synthesizing = @synthesizing
-      return 1 if @waveform1.stepped?(synthesizing) || @waveform2.stepped?(synthesizing) ||
-                  @waveform3.stepped?(synthesizing)
-
-      span = synthesizing ? synthesis_span(cycles) : cycles
-      span = sync_span(@waveform1, span)
-      span = sync_span(@waveform2, span)
-      sync_span(@waveform3, span)
-    end
-
-    # The filter steps at most @filter_chunk cycles at a time, and never
-    # across the end of a recorded sample.
-    def synthesis_span(cycles)
-      span = [cycles, @filter_chunk].min
-      return span unless @decimator
-
-      [@decimator.cycles_to_close, span].min
-    end
-
-    def sync_span(waveform, span)
-      return span unless waveform.sync_dest.sync?
-
-      rise = waveform.cycles_to_msb_rise
-      rise && rise < span ? rise : span
-    end
-
-    # Unrolled over the three voices: the per-cycle block calls cost
-    # measurably on the synthesis path.
-    def fast_forward(cycles)
-      @voice1.fast_forward(cycles)
-      @voice2.fast_forward(cycles)
-      @voice3.fast_forward(cycles)
-    end
-
-    # The last cycle of a span, run whole. The filter integrates the span
-    # from the voices' output at its end.
-    def clock!(span)
-      @voice1.cycle!
-      @voice2.cycle!
-      @voice3.cycle!
-      @waveform1.synchronize!
-      @waveform2.synchronize!
-      @waveform3.synchronize!
-      return unless @synthesizing
-
-      @filter.cycle!(@voices, span)
-      record_sample(span) if @decimator
-    end
-
-    def record_sample(span)
-      sample = @decimator.push(current_sample, span)
-      @samples << sample if sample
-    end
-
-    def current_sample = (@filter.output / SAMPLE_DIVISOR).clamp(-0x8000, 0x7fff)
-
     def latch(value)
       @bus_ttl = @bus_ttl_reset
       @bus_value = value
@@ -268,8 +190,8 @@ module Badline
 
     def write_register(reg, value)
       @registers.poke(reg, value)
-      catch_up if @deferred_writes.length == DEFERRED_WRITES
-      @deferred_writes << [@pending_cycles, reg, value]
+      catch_up if @deferred_writes.length == DEFERRED_WRITES * 3
+      @deferred_writes.push(@pending_cycles, reg, value)
     end
 
     def apply_write(reg, value)
@@ -283,7 +205,9 @@ module Badline
       when 1 then voice.waveform.frequency_high = value
       when 2 then voice.waveform.pulse_width_low = value
       when 3 then voice.waveform.pulse_width_high = value
-      when 4 then voice.control = value
+      when 4
+        voice.control = value
+        update_span_rules
       when 5 then voice.envelope.attack_decay = value
       when 6 then voice.envelope.sustain_release = value
       end