badline 0.2.0 → 0.3.0

data/lib/badline/cartridge/rex_utility.rb

@@ -25,7 +25,7 @@ module Badline
       private
 
       def install_chips(chips)
-        @roml = banks_from(chips).first.compact.first
+        @roml = banks_from(chips).first.compact.first || EMPTY_BANK
         reset
       end
     end

data/lib/badline/cartridge/rgcd.rb

@@ -40,7 +40,7 @@ module Badline
 
       def install_chips(chips)
         @banks = banks_from(chips).first
-        @bank_mask = @hucky ? @banks.length - 1 : 0x07
+        @bank_mask = @hucky ? bank_mask(@banks) : 0x07
         reset
       end
     end

data/lib/badline/cartridge/simons_basic.rb

@@ -31,8 +31,8 @@ module Badline
 
       def install_chips(chips)
         roml, romh = banks_from(chips)
-        @roml = roml.first
-        @romh = romh.first
+        @roml = bank(roml, 0)
+        @romh = bank(romh, 0)
         reset
       end
     end

data/lib/badline/cartridge/westermann.rb

@@ -25,8 +25,8 @@ module Badline
 
       def install_chips(chips)
         roml, romh = banks_from(chips)
-        @roml = roml.first
-        @romh = romh.first
+        @roml = bank(roml, 0)
+        @romh = bank(romh, 0)
         reset
       end
     end

data/lib/badline/cartridge.rb

@@ -35,12 +35,12 @@ module Badline
     BANK_SIZE = 0x2000
 
     HARDWARE_TYPES = {
-      0 => :Standard, 1 => :ActionReplay, 2 => :KCSPower, 3 => :FinalCartridge3,
-      4 => :SimonsBasic, 5 => :Ocean, 7 => :FunPlay, 8 => :SuperGames,
-      9 => :AtomicPower, 10 => :EpyxFastload, 11 => :Westermann,
-      12 => :RexUtility, 15 => :GameSystem, 17 => :Dinamic, 18 => :Zaxxon,
-      19 => :MagicDesk, 21 => :Comal80, 32 => :EasyFlash, 36 => :RetroReplay,
-      51 => :Mach5, 53 => :Pagefox, 57 => :RGCD, 60 => :GMod2
+      0 => Standard, 1 => ActionReplay, 2 => KCSPower, 3 => FinalCartridge3,
+      4 => SimonsBasic, 5 => Ocean, 7 => FunPlay, 8 => SuperGames,
+      9 => AtomicPower, 10 => EpyxFastload, 11 => Westermann,
+      12 => RexUtility, 15 => GameSystem, 17 => Dinamic, 18 => Zaxxon,
+      19 => MagicDesk, 21 => Comal80, 32 => EasyFlash, 36 => RetroReplay,
+      51 => Mach5, 53 => Pagefox, 57 => RGCD, 60 => GMod2
     }.freeze
 
     # The EXROM and GAME line levels of each memory configuration. The lines
@@ -62,11 +62,11 @@ module Badline
       end
 
       def from_crt(crt, **)
-        type = HARDWARE_TYPES.fetch(crt.hardware_type) do
+        mapper = HARDWARE_TYPES.fetch(crt.hardware_type) do
           raise UnsupportedTypeError,
                 "Unsupported cartridge hardware type #{crt.hardware_type}"
         end
-        const_get(type).new(crt, **)
+        mapper.new(crt, **)
       end
     end
 
@@ -168,10 +168,18 @@ module Badline
       Bank.new(data)
     end
 
+    # A bank the image leaves out reads as erased ROM.
     def bank(banks, number)
       banks[number] || EMPTY_BANK
     end
 
+    # The bank register bits a ROM decodes. The ROM holds the highest bank
+    # in the image, and has address lines for the power of two that covers
+    # it; the register bits above those lines are ignored.
+    def bank_mask(banks)
+      (1 << (banks.length - 1).bit_length) - 1
+    end
+
     # Sorts the CHIP packets into ROML and ROMH banks by load address. A 16K
     # chip at $8000 spans both.
     def banks_from(chips)

data/lib/badline/checkpoint.rb

@@ -0,0 +1,98 @@
+# frozen_string_literal: true
+
+module Badline
+  # A digest of the machine's state at one cycle, for comparing two runs of
+  # the same scenario, on two builds or two revisions. Each component is
+  # hashed on its own with 32-bit FNV-1a, so a mismatch names the part of the
+  # machine that went its own way. Nothing is read through a chip's bus
+  # interface, so taking a checkpoint leaves the machine as it was.
+  #
+  # Colour RAM is digested as the four bits each cell stores: the upper
+  # nibble a CPU read sees comes off the open bus.
+  class Checkpoint
+    COMPONENTS = %w[cpu ram color_ram display vic cia1 cia2 sid].freeze
+
+    FNV_OFFSET = 0x811c9dc5
+    FNV_PRIME = 0x01000193
+
+    attr_reader :cycle, :digests
+
+    class << self
+      def take(computer)
+        new(computer.cycles, [
+              fnv1a(cpu_state(computer.cpu)),
+              fnv1a(ram(computer.ram)),
+              fnv1a(color_ram(computer.address_bus.color_ram)),
+              fnv1a(computer.vic.display),
+              fnv1a(vic_state(computer.vic)),
+              fnv1a(cia_state(computer.cia1)),
+              fnv1a(cia_state(computer.cia2)),
+              fnv1a(Array.new(0x20) { |reg| computer.sid.register(reg) })
+            ])
+      end
+
+      # Reads a line written by #to_s.
+      def parse(line)
+        fields = line.split
+        digests = COMPONENTS.map do |name|
+          field = fields.find { |f| f.start_with?("#{name}=") }
+          raise ArgumentError, "no #{name} digest in #{line.inspect}" unless field
+
+          field.split("=").last.to_i(16)
+        end
+        new(fields.first.to_i, digests)
+      end
+
+      def fnv1a(values)
+        hash = FNV_OFFSET
+        values.each { |value| hash = ((hash ^ (value & 0xffffffff)) * FNV_PRIME) & 0xffffffff }
+        hash
+      end
+
+      private
+
+      def cpu_state(cpu)
+        [cpu.program_counter, cpu.a, cpu.x, cpu.y, cpu.stack_pointer, cpu.p, cpu.cycles]
+      end
+
+      def ram(memory)
+        Array.new(0x10000) { |addr| memory.peek(addr) }
+      end
+
+      def color_ram(memory)
+        Array.new(0x400) { |offset| memory.nibble(0xd800 + offset) }
+      end
+
+      def vic_state(vic)
+        vic.register_file + [vic.rasterline, vic.column]
+      end
+
+      def cia_state(cia)
+        start = cia.start
+        [cia.peek(start), cia.peek(start + 1), cia.peek(start + 2), cia.peek(start + 3),
+         cia.timer_a, cia.timer_a_latch, cia.timer_b, cia.timer_b_latch, cia.serial.data,
+         cia.control_a.value, cia.control_b.value, cia.interrupt_status.value,
+         cia.interrupt_control.value] + cia.time_of_day.registers
+      end
+    end
+
+    def initialize(cycle, digests)
+      @cycle = cycle
+      @digests = digests
+    end
+
+    # The components whose digests differ from `other`'s.
+    def differences(other)
+      COMPONENTS.each_index.reject { |i| digests[i] == other.digests[i] }.map { |i| COMPONENTS[i] }
+    end
+
+    def ==(other)
+      other.is_a?(Checkpoint) && cycle == other.cycle && digests == other.digests
+    end
+
+    def to_s
+      fields = COMPONENTS.each_index.map { |i| "#{COMPONENTS[i]}=#{digests[i].to_s(16).rjust(8, '0')}" }
+      "#{cycle} #{fields.join(' ')}"
+    end
+  end
+end

data/lib/badline/cia/interrupt_register.rb

@@ -9,8 +9,8 @@ module Badline
       attr_reader :status, :mask, :quiet
 
       def initialize
-        @mask = Status.new([:timer_a, :timer_b, :alarm, :serial, :flag, 0, 0, 0])
-        @status = Status.new([:timer_a, :timer_b, :alarm, :serial, :flag, 0, 0, :interrupt])
+        @mask = InterruptFlags.new([:timer_a, :timer_b, :alarm, :serial, :flag, 0, 0, 0])
+        @status = InterruptFlags.new([:timer_a, :timer_b, :alarm, :serial, :flag, 0, 0, :interrupt])
         @pending = 0
         @read = @read_last_cycle = @read_two_cycles_ago = nil
         @timer_b_bug = false
@@ -40,8 +40,9 @@ module Badline
 
       # Latch a source, pulling the interrupt line if it is armed.
       def flag(source)
-        status.public_send(:"#{source}=", true)
-        assert! if mask.public_send(:"#{source}?")
+        bit = source_bit(source)
+        @status.value |= bit
+        assert! if mask.value.anybits?(bit)
       end
 
       # The 6526 timer B bug: an underflow on the cycle after a read still
@@ -70,9 +71,9 @@ module Badline
       # Bit 7 picks between setting and clearing the mask bits given.
       def write(value)
         if value.nobits?(0x80)
-          mask.value &= ~(value & 0x1f)
+          @mask.value &= ~(value & 0x1f)
         else
-          mask.value |= (value & 0x1f)
+          @mask.value |= (value & 0x1f)
         end
         if mask.value.anybits?(status.value & 0x1f)
           assert!(2) unless interrupted?
@@ -83,6 +84,19 @@ module Badline
           @pending = 0
         end
       end
+
+      private
+
+      def source_bit(source)
+        case source
+        when :timer_a then 0x01
+        when :timer_b then 0x02
+        when :alarm then 0x04
+        when :serial then 0x08
+        when :flag then 0x10
+        else raise ArgumentError, "unknown interrupt source #{source}"
+        end
+      end
     end
   end
 end

data/lib/badline/cia.rb

@@ -1,6 +1,5 @@
 # frozen_string_literal: true
 
-require "forwardable"
 require "badline/cia/interrupt_register"
 require "badline/cia/serial"
 require "badline/cia/timer"
@@ -9,22 +8,40 @@ module Badline
   # CIA (Complex Interface Adapter) chip
   class CIA
     include Addressable
-    extend Forwardable
 
     attr_reader :start, :control_a, :control_b, :peripheral, :serial
 
-    def_delegator :@icr, :status, :interrupt_status
-    def_delegator :@icr, :mask,   :interrupt_control
-    def_delegator :@icr, :assert!, :interrupt!
+    def interrupt_status = @icr.status
 
-    def_delegator :@ta, :counter,  :timer_a
-    def_delegator :@ta, :counter=, :timer_a=
-    def_delegator :@ta, :latch,    :timer_a_latch
-    def_delegator :@ta, :latch=,   :timer_a_latch=
-    def_delegator :@tb, :counter,  :timer_b
-    def_delegator :@tb, :counter=, :timer_b=
-    def_delegator :@tb, :latch,    :timer_b_latch
-    def_delegator :@tb, :latch=,   :timer_b_latch=
+    def interrupt_control = @icr.mask
+
+    def interrupt!(delay = 1) = @icr.assert!(delay)
+
+    def time_of_day = @tod
+
+    def timer_a = @ta.counter
+
+    def timer_a=(value)
+      @ta.counter = value
+    end
+
+    def timer_a_latch = @ta.latch
+
+    def timer_a_latch=(value)
+      @ta.latch = value
+    end
+
+    def timer_b = @tb.counter
+
+    def timer_b=(value)
+      @tb.counter = value
+    end
+
+    def timer_b_latch = @tb.latch
+
+    def timer_b_latch=(value)
+      @tb.latch = value
+    end
 
     def initialize(start: 0, peripheral: nil)
       addressable_at(start, length: 2**8)
@@ -49,10 +66,10 @@ module Badline
       @tod = TimeOfDay.new
       @icr = InterruptRegister.new
       @icr_status = @icr.status
-      @control_a = Status.new(%i[start output out_mode run_mode load
-                                 in_mode serial_mode clock_frequency])
-      @control_b = Status.new(%i[start output out_mode run_mode load
-                                 in_cnt in_timer_a alarm])
+      @control_a = ControlRegister.new(%i[start output out_mode run_mode load
+                                          in_mode serial_mode clock_frequency])
+      @control_b = ControlRegister.new(%i[start output out_mode run_mode load
+                                          in_cnt in_timer_a alarm])
       @ta = Timer.new(@control_a)
       @tb = Timer.new(@control_b)
       @serial = Serial.new(@control_a)
@@ -100,7 +117,7 @@ module Badline
     end
 
     def peek(addr)
-      case index(addr) & 0x0f
+      case offset_of(addr) & 0x0f
       when 0x00 then read_port_a
       when 0x01 then read_port_b
       when 0x02 then @data_dir_a
@@ -121,7 +138,7 @@ module Badline
     end
 
     def poke(addr, value)
-      case index(addr) & 0x0f
+      case offset_of(addr) & 0x0f
       when 0x00 then @data_port_a = value
       when 0x01 then update_port_b { @data_port_b = value }
       when 0x02 then @data_dir_a = value

data/lib/badline/color_memory.rb

@@ -10,7 +10,7 @@ module Badline
     end
 
     def peek(addr)
-      (@vic.phi1_data & 0xf0) | @storage[index(addr)]
+      (@vic.phi1_data & 0xf0) | @storage[offset_of(addr)]
     end
 
     def poke(addr, value)
@@ -19,7 +19,7 @@ module Badline
 
     # The four bits the cell stores, as the VIC's c-access sees them.
     def nibble(addr)
-      @storage[index(addr)]
+      @storage[offset_of(addr)]
     end
   end
 end

data/lib/badline/computer.rb

@@ -1,17 +1,33 @@
 # frozen_string_literal: true
 
-require "forwardable"
-
 module Badline
   class Computer
     include IntegerHelper
     include KeyboardBuffer
-    extend Forwardable
 
     attr_reader :address_bus, :cpu, :cycles
 
-    def_delegators :address_bus, :vic, :cia1, :cia2, :sid, :ram, :keyboard, :joystick1, :joystick2,
-                   :control_ports, :datasette, :install_debug_register
+    def vic = address_bus.vic
+
+    def cia1 = address_bus.cia1
+
+    def cia2 = address_bus.cia2
+
+    def sid = address_bus.sid
+
+    def ram = address_bus.ram
+
+    def keyboard = address_bus.keyboard
+
+    def joystick1 = address_bus.joystick1
+
+    def joystick2 = address_bus.joystick2
+
+    def control_ports = address_bus.control_ports
+
+    def datasette = address_bus.datasette
+
+    def install_debug_register(&) = address_bus.install_debug_register(&)
 
     def initialize(debug: false, sid_model: :mos6581)
       @address_bus = AddressBus.new(sid_model:)
@@ -29,6 +45,7 @@ module Badline
       @freeze_writes = 0
       @init_handlers = []
       @pending_keys = nil
+      @drive = nil
     end
 
     INIT_THRESHOLD = 2_500_000
@@ -64,17 +81,28 @@ module Badline
       cartridge.clock = -> { @cycles }
       cartridge.on_nmi_change { |level| @cartridge_nmi = level }
       address_bus.attach_cartridge(cartridge)
+      power_cycle!
+    end
+
+    # A cartridge goes in with the power off, so attaching one switches the
+    # machine off and on: the VIC and RAM start from their power-on state,
+    # and the RES line resets everything else.
+    def power_cycle!
+      vic.power_on!
+      address_bus.power_on!
       reset!
     end
 
-    # The RES line reaches the CPU and its port, both CIAs, the SID and the
-    # cartridge port. The VIC has no reset pin.
+    # The RES line reaches the CPU and its port, both CIAs, the SID, the
+    # cartridge port and, through the serial bus's RESET line, the drive.
+    # The VIC has no reset pin.
     def reset!
       address_bus.reset_port!
       @cia1.reset!
       @cia2.reset!
       @sid.reset!
       address_bus.cartridge&.reset
+      @drive&.reset!
       @freezing = false
       @nmi_asserted = false
       cpu.reset!
@@ -95,14 +123,16 @@ module Badline
       address_bus.cartridge&.release_button
     end
 
+    # A disk swap keeps the drive's RAM, which only a drive reset clears.
     def mount(storage)
-      load_trap = KernalTrap::Load.new(cpu:, bus: address_bus, storage:)
+      @drive_memory ||= KernalTrap::Drive::Memory.new
+      @drive = KernalTrap::Drive.new(storage, @drive_memory)
+      load_trap = KernalTrap::Load.new(cpu:, bus: address_bus, drive: @drive)
       cpu.install_trap(KernalTrap::Load::ADDRESS) { load_trap.call }
-      drive = KernalTrap::Drive.new(storage)
-      KernalTrap::Serial.new(cpu:, bus: address_bus, drive:).install
+      KernalTrap::Serial.new(cpu:, bus: address_bus, drive: @drive).install
       return unless storage.respond_to?(:write_file)
 
-      save_trap = KernalTrap::Save.new(cpu:, bus: address_bus, storage:)
+      save_trap = KernalTrap::Save.new(cpu:, bus: address_bus, drive: @drive)
       cpu.install_trap(KernalTrap::Save::ADDRESS) { save_trap.call }
     end
 

data/lib/badline/cpu/microcode.rb

@@ -107,60 +107,58 @@ module Badline
     # - +optional_dummy+: true for indexed reads, which skip the extra
     #   cycle unless indexing crosses a page
     Microcode = Struct.new(:operation, :plan, :writes, :optional_dummy) do
-      class << self
-        def table
-          Array.new(256) do |opcode|
-            instruction = Instruction.find(opcode)
-            raise InvalidOpcodeError, format("$%02x", opcode) unless instruction
-
-            build(instruction)
-          end.freeze
-        end
+      def self.table
+        Array.new(256) do |opcode|
+          instruction = Instruction.find(opcode)
+          raise InvalidOpcodeError, format("$%02x", opcode) unless instruction
 
-        def write_mask(plan)
-          plan.map { |step| WRITE_STEPS.include?(step) }.freeze
-        end
+          build(instruction)
+        end.freeze
+      end
 
-        private
+      def self.write_mask(plan)
+        plan.map { |step| WRITE_STEPS.include?(step) }.freeze
+      end
 
-        def build(instruction)
-          plan = plan_for(instruction)
-          new(instruction.name, plan, write_mask(plan),
-              instruction.boundary_cycle?)
-        end
+      def self.build(instruction)
+        plan = plan_for(instruction)
+        new(instruction.name, plan, write_mask(plan),
+            instruction.boundary_cycle?)
+      end
 
-        def plan_for(instruction)
-          case instruction.name
-          when :jmp
-            if instruction.addressing_mode == :indirect
-              JMP_INDIRECT_PLAN
-            else
-              JMP_ABSOLUTE_PLAN
-            end
-          when *BRANCHES then BRANCH_PLAN
-          else SPECIAL_PLANS[instruction.name] || addressed_plan(instruction)
+      def self.plan_for(instruction)
+        case instruction.name
+        when :jmp
+          if instruction.addressing_mode == :indirect
+            JMP_INDIRECT_PLAN
+          else
+            JMP_ABSOLUTE_PLAN
           end
+        when *BRANCHES then BRANCH_PLAN
+        else SPECIAL_PLANS[instruction.name] || addressed_plan(instruction)
         end
+      end
 
-        def addressed_plan(instruction)
-          mode = instruction.addressing_mode
-          case mode
-          when :implied then IMPLIED_PLAN
-          when :accumulator then ACCUMULATOR_PLAN
-          when :immediate then IMMEDIATE_PLAN
-          else
-            [:op_fetch, *ADDRESSING_STEPS.fetch(mode),
-             *OPERATION_STEPS.fetch(operation_kind(instruction.name))].freeze
-          end
+      def self.addressed_plan(instruction)
+        mode = instruction.addressing_mode
+        case mode
+        when :implied then IMPLIED_PLAN
+        when :accumulator then ACCUMULATOR_PLAN
+        when :immediate then IMMEDIATE_PLAN
+        else
+          [:op_fetch, *ADDRESSING_STEPS.fetch(mode),
+           *OPERATION_STEPS.fetch(operation_kind(instruction.name))].freeze
         end
+      end
 
-        def operation_kind(name)
-          return :write if STORES.include?(name)
-          return :rmw if READ_MODIFY_WRITES.include?(name)
+      def self.operation_kind(name)
+        return :write if STORES.include?(name)
+        return :rmw if READ_MODIFY_WRITES.include?(name)
 
-          :read
-        end
+        :read
       end
+
+      private_class_method :build, :plan_for, :addressed_plan, :operation_kind
     end
 
     FETCH_WRITES = Microcode.write_mask(FETCH_PLAN)

data/lib/badline/cpu.rb

@@ -24,11 +24,11 @@ module Badline
 
     # +ane_constant+ is ANE's magic constant, which varies from chip to
     # chip. The default is the C64 6510's.
-    def initialize(memory = nil, debug: false, ane_constant: 0xef)
+    def initialize(memory, debug: false, ane_constant: 0xef)
       @debug = debug
       @ane_constant = ane_constant
-      @memory = memory || Memory.new
-      @status = Status.new(STATUS_FLAGS, value: 0b00100000)
+      @memory = memory
+      @status = CPUStatus.new(STATUS_FLAGS, value: 0b00100000)
       reset_registers
 
       @nmi = @irq = false

data/lib/badline/gui/application.rb

@@ -6,6 +6,7 @@ module Badline
       PAL_CLOCK_HZ = 985_248
       TITLE = "Badline"
       TOGGLE_SYM = SDL2::Key::TAB
+      MUTE_SYM = SDL2::Key::F10
       REVERSE_MOD = SDL2::Key::Mod::SHIFT
 
       SHARED_KEYS = %i[up left cursor_h cursor_v space w a s d lshift].freeze
@@ -28,24 +29,23 @@ module Badline
       }.freeze
       MOUSE_BUTTONS = { 1 => :left, 3 => :right }.freeze
 
-      def initialize(media_path: nil, autostart: true, song: nil, sid_model: nil, debug: false)
-        @computer = Computer.new(debug:, sid_model: sid_model || Media.sid_model(media_path))
+      def initialize(media_path: nil, autostart: true, song: nil, sid_model: nil, sound: false)
+        @computer = Computer.new(sid_model: sid_model || Media.sid_model(media_path))
         puts Media.attach(@computer, media_path, autostart:, song:) if media_path
 
         @mode = :keyboard
         @pot_device = nil
         @panes = [ScreenPane.new(@computer)]
+        @stream = open_stream if sound
+        @paced = ENV["NOVSYNC"].nil?
         @window = Window.new(
           title: TITLE,
           width: canvas_width, height: canvas_height,
-          vsync: ENV["NOVSYNC"].nil?
+          vsync: @paced && !@stream
         )
         @gamepads = Gamepads.new(@computer)
         @gamepads.names.each { |name| puts "Gamepad: #{name}" }
-
-        rate = @window.refresh_rate
-        @cycles_per_frame = PAL_CLOCK_HZ / rate
-        puts "Display #{rate} Hz -> #{@cycles_per_frame} cycles/frame"
+        fit_frame
       end
 
       def run
@@ -54,9 +54,12 @@ module Badline
           handle_events
           @gamepads.poll
           @cycles_per_frame.times { @computer.cycle! }
+          @stream&.feed
           @window.draw(@panes)
+          @stream.pace(@frame_seconds) if @stream && @paced
         end
       ensure
+        @stream&.close
         @gamepads.close
         puts @computer.cpu.inspect
       end
@@ -84,6 +87,7 @@ module Badline
 
       def handle_key_down(event)
         return cycle_mode(event.mod.anybits?(REVERSE_MOD) ? -1 : 1) if event.sym == TOGGLE_SYM
+        return toggle_mute if event.sym == MUTE_SYM
 
         port, dir = JoyMap.parse(event) if @mode == :joystick
         if port
@@ -94,7 +98,7 @@ module Badline
       end
 
       def handle_key_up(event)
-        return if event.sym == TOGGLE_SYM
+        return if [TOGGLE_SYM, MUTE_SYM].include?(event.sym)
 
         port, dir = JoyMap.parse(event) if @mode == :joystick
         if port
@@ -123,7 +127,35 @@ module Badline
         @mode = modes[(modes.index(@mode) + step) % modes.size]
         release_inputs
         attach_pot_device
-        @window.title = [TITLE, MODES[@mode] && "[#{MODES[@mode]}]"].compact.join(" ")
+        update_title
+      end
+
+      def toggle_mute
+        return unless @stream
+
+        @stream.toggle_mute
+        update_title
+      end
+
+      def update_title
+        tags = [MODES[@mode], @stream&.muted? && "MUTED"].select(&:itself)
+        @window.title = [TITLE, *tags.map { |tag| "[#{tag}]" }].join(" ")
+      end
+
+      def open_stream
+        sink = Audio::SDLSink.new(rate: Audio::Renderer::DEFAULT_RATE)
+        puts "Sound at #{sink.rate} Hz, F10 mutes"
+        Audio::Stream.new(sink, @computer.sid,
+                          on_underrun: -> { puts "Running below real time, so the sound will stutter." })
+      rescue Audio::SDLSink::Error => e
+        warn "badline: no sound, can't open the audio device: #{e.message}"
+      end
+
+      def fit_frame
+        rate = @window.refresh_rate
+        @cycles_per_frame = PAL_CLOCK_HZ / rate
+        @frame_seconds = @cycles_per_frame.fdiv(PAL_CLOCK_HZ)
+        puts "Display #{rate} Hz -> #{@cycles_per_frame} cycles/frame"
       end
 
       def attach_pot_device