badline 0.18.0 → 0.19.0

data/lib/badline/snapshot/field_doc.rb

@@ -35,9 +35,10 @@ module Badline
       CARTRIDGES = [32, 5, 21, 18, 1, 53].freeze
 
       # The machines the doc is made from: each family at power-on, the C64
-      # with each kind of expansion, cartridge and media, and a second SID,
-      # the 264 series' models, its TCBM interface, cartridge, tape and
-      # true drives, the 1541 and the 1551, a CRTC PET, a 2001, an 8096,
+      # with each kind of expansion, cartridge and media, a second SID and
+      # its sound recording, the 264 series' models, its TCBM interface,
+      # cartridge, tape and true drives, the 1541 and the 1551, a CRTC PET,
+      # a 2001, an 8096,
       # an 8296 with its user port jumpered, a PET with a disk and tapes and
       # one with a true 2031, one with an 8050, one with an 8250, one with
       # a 4040 and one with a D9060, a SuperPET in 6809 mode with a disk in
@@ -48,7 +49,7 @@ module Badline
         {
           "c64" => [C64.new, C64.new(ram_expansion: :plus256k), C64.new(reu: 512),
                     *CARTRIDGES.map { |type| with_cartridge(type) }, with_trap_dos, with_tape, with_drive(:d64),
-                    with_drive(:d81), with_extra_sids],
+                    with_drive(:d81), with_extra_sids, with_recording],
           "vic20" => [Vic20.new, with_rom],
           "c128" => [C128.new(mode: :c128), with_drive(:d71)],
           "plus4" => [Plus4.new, Plus4.new(model: "c16"), Plus4.new(tcbm: true), Plus4.new(sid_card: :mos6581),
@@ -139,6 +140,9 @@ module Badline
         C64.new.tap { |machine| machine.address_bus.add_sid(Chips::SID.new(at: 0xd420)) }
       end
 
+      # A C64 recording its SID's output, as the window does with sound on.
+      def self.with_recording = C64.new.tap { |machine| machine.sound_source.record(rate: 44_100) }
+
       def self.with_trap_dos
         C64.new.tap { |machine| machine.mount(Storage::D64Image.new("", read_only: true, bytes: blank(174_848))) }
       end

data/lib/badline/snapshot/image.rb

@@ -40,8 +40,7 @@ module Badline
       # The snapshots VICE's emulators write that badline doesn't read, by
       # the machine their container names.
       UNREAD = {
-        Container::VIC20 => "VIC-20 snapshots, not xvic's", Container::C128 => "C128 snapshots, not x128's",
-        Container::PLUS4 => "Plus/4 snapshots, not xplus4's"
+        Container::C128 => "C128 snapshots, not x128's", Container::PLUS4 => "Plus/4 snapshots, not xplus4's"
       }.freeze
 
       attr_reader :container
@@ -62,8 +61,8 @@ module Badline
       end
 
       # The snapshot with VICE's modules ahead of the BL-* ones for a C64,
-      # a PET, a CBM-II's B series or a P500, so x64sc, xpet, xcbm2 or
-      # xcbm5x0 opens it too. Raises FormatError for a Plus/4, whose
+      # a VIC-20, a PET, a CBM-II's B series or a P500, so x64sc, xvic,
+      # xpet, xcbm2 or xcbm5x0 opens it too. Raises FormatError for a Plus/4, whose
       # snapshots badline doesn't write for xplus4.
       def self.exported(computer)
         raise FormatError, "badline doesn't export a Plus/4's snapshot for VICE" if computer.family == :plus4
@@ -73,6 +72,7 @@ module Badline
         sections = computer.save_modules
         case computer.family
         when :c64 then sections = Vice.export(computer) + sections
+        when :vic20 then sections = Vice::Vic20.export(computer, sections) + sections
         when :pet then sections = Vice::PET.export(computer, sections) + sections
         when :cbm2 then sections = cbm2_export(computer, sections) + sections
         end
@@ -87,6 +87,7 @@ module Badline
       # The VICE emulator a machine's VICE modules are for.
       def self.vice_emulator(computer)
         case machine_name(computer)
+        when Container::VIC20 then "xvic"
         when Container::PET then "xpet"
         when Container::CBM2 then "xcbm2"
         when Container::CBM2_5X0 then "xcbm5x0"
@@ -132,13 +133,14 @@ module Badline
 
       # A new machine, built as the snapshot's was and restored from it. A
       # badline snapshot restores from its BL-* modules alone, and a VICE
-      # one through the modules badline reads, x64sc's, xpet's, xcbm2's or xcbm5x0's. xvic's,
-      # x128's and xplus4's own modules aren't read. Yields a line for
+      # one through the modules badline reads, x64sc's, xvic's, xpet's,
+      # xcbm2's or xcbm5x0's. x128's and xplus4's own modules aren't read. Yields a line for
       # each thing left out, or warns it without a block. `detached`
       # restores it without the host's files (Keyed::Modules).
       def load(detached: false, &)
         refuse_old_layout
         refuse_unread
+        return load_xvic(&) if vic20? && !badline?
         return load_xpet(&) if pet? && !badline?
         return load_xcbm2(&) if cbm2? && !badline?
         return load_xcbm5x0(&) if p500? && !badline?
@@ -175,6 +177,7 @@ module Badline
       def restore(computer, &)
         refuse_old_layout
         report = if badline? then restore_modules(computer)
+                 elsif vic20? then Vice::Vic20::Restore.import(@container, computer)
                  elsif pet? then Vice::PET::Restore.import(@container, computer)
                  elsif cbm2? then Vice::CBM2::Restore.import(@container, computer)
                  elsif p500? then Vice::P500::Restore.import(@container, computer)
@@ -192,6 +195,12 @@ module Badline
         computer
       end
 
+      def load_xvic(&)
+        computer = Vice::Vic20.setup(@container).build
+        tell(Vice::Vic20::Restore.apply(@container, computer), &)
+        computer
+      end
+
       def load_xpet(&)
         computer = Vice::PET.setup(@container).build
         tell(Vice::PET::Restore.apply(@container, computer), &)

data/lib/badline/snapshot/vice/pet.rb

@@ -2,6 +2,7 @@
 
 require "badline/snapshot/vice/cbm2_acia"
 require "badline/snapshot/vice/pet_cpu"
+require "badline/snapshot/vice/pet_dongle"
 require "badline/snapshot/vice/pet_mem"
 require "badline/snapshot/vice/pet_pias"
 require "badline/snapshot/vice/pet_via"

data/lib/badline/snapshot/vice/pet_dongle.rb

@@ -0,0 +1,72 @@
+# frozen_string_literal: true
+
+module Badline
+  module Snapshot
+    module Vice
+      module PET
+        # The SuperPET's 6702 in PETMEM's settings at the end, from their
+        # fifth byte: the byte the 6702 reads, the last write that shifted
+        # it, 1 while the last write left D0 clear, then a little-endian word
+        # for each data line's shift register. Bit k of a word, below the
+        # register's last stage, is stage k XORed with stage k + 1, and its
+        # last stage's bit is that stage XORed with the stage the next shift
+        # brings in if the latch then holds the last write that shifted.
+        # Every PET's settings hold a 6702 as the RES line leaves it.
+        #
+        # Mapped from xpet 3.10's snapshots after each of 56 writes to $EFE0
+        # from its monitor, against PET::SuperPET::Dongle after the same
+        # writes.
+        #
+        # Written and read: the registers, and whether D0 was clear in the
+        # last write. A write the 6702 hasn't shifted on yet is written as
+        # shifted. Read, the latch is $00 or $FF by D0, and no shift waits.
+        module Dongle
+          # Offsets in PETMEM's settings.
+          AT = 4
+          LENGTH = 19
+          OUTPUT = 0
+          ARMED = 2
+          WORDS = 3
+          # The last write that shifted, as xpet has it after RES.
+          RESET_LAST = 0x01
+
+          module_function
+
+          # The settings' bytes for a 6702 with `registers`, after a write
+          # of `latch`.
+          def export(registers, latch)
+            incoming = RESET_LAST ^ Badline::PET::SuperPET::Dongle::FEEDBACK ^ 0xff
+            output = 0
+            words = []
+            8.times do |bit|
+              register = registers[bit]
+              output |= (register & 1) << bit
+              top = Badline::PET::SuperPET::Dongle::LENGTHS[bit] - 1
+              last = ((register >> top) ^ register ^ (incoming >> bit)) & 1
+              word = ((register ^ (register >> 1)) & ((1 << top) - 1)) | (last << top)
+              words << (word & 0xff) << (word >> 8)
+            end
+            [output ^ Badline::PET::SuperPET::Dongle::INVERTED, RESET_LAST, latch.nobits?(0x01) ? 1 : 0, *words]
+          end
+
+          # The 6702's BL-SUPERPET keys from the settings' `bytes`, in a keyed
+          # module's writer.
+          def import(bytes, out)
+            stages = bytes[OUTPUT] ^ Badline::PET::SuperPET::Dongle::INVERTED
+            registers = Array.new(8) do |bit|
+              word = bytes[WORDS + (bit * 2)] | (bytes[WORDS + (bit * 2) + 1] << 8)
+              stage = (stages >> bit) & 1
+              register = stage
+              (Badline::PET::SuperPET::Dongle::LENGTHS[bit] - 1).times do |index|
+                stage ^= (word >> index) & 1
+                register |= stage << (index + 1)
+              end
+              register
+            end
+            out.ints("dongle.registers", registers).int("dongle.latch", bytes[ARMED].zero? ? 0xff : 0x00)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/snapshot/vice/pet_mem.rb

@@ -9,7 +9,7 @@ module Badline
         # the RAM, the screen RAM, 1K or 2K as the board has, or on the 8296
         # its 32K from $8000, an 8096's, 8296's or SuperPET's 64K board, and
         # 24 bytes of xpet's own settings, which name the 2001, and on the
-        # SuperPET the CPU that has the bus.
+        # SuperPET the CPU that has the bus and the 6702.
         #
         # The board is 0 for the discrete video, 1 for a 40-column CRTC, 2
         # for an 80-column one, 3 for the SuperPET, 4 for the 8096 and 5 for
@@ -21,8 +21,8 @@ module Badline
         # while the 6809 has the bus. Both were inferred from xpet 3.10's
         # snapshots after writes to the bank latch and $EFFE, and in both
         # modes. xpet has no system latch, so the bank latch's bit 7 and the
-        # system latch aren't saved, and a restore clears them. Nor is the
-        # 6702: a restore leaves it as the RES line does.
+        # system latch aren't saved, and a restore clears them. The 6702 is
+        # in the settings from their fifth byte (Dongle).
         module PETMem
           NAME = "PETMEM"
           MAJOR = 1
@@ -77,7 +77,11 @@ module Badline
             fields.bytes(machine.board.cells) if superpet
             settings = SETTINGS.dup
             settings[1] = SETTINGS_2001 if machine.model.basic1?
-            settings[SETTINGS_CPU] = SETTINGS_M6809 if superpet && machine.m6809_running?
+            if superpet
+              settings[SETTINGS_CPU] = SETTINGS_M6809 if machine.m6809_running?
+              dongle = machine.dongle
+              settings[Dongle::AT, Dongle::LENGTH] = Dongle.export(dongle.settled_registers, dongle.latch)
+            end
             fields.bytes(settings).section(NAME, MAJOR, MINOR)
           end
 
@@ -90,7 +94,7 @@ module Badline
             offset >= 0 && data.getbyte(offset).to_i.anybits?(SETTINGS_M6809)
           end
 
-          # A SuperPET's bank latch, socket bit and 64K board by their
+          # A SuperPET's bank latch, socket bit, 64K board and 6702 by their
           # BL-SUPERPET keys, in a keyed module's writer.
           def import_superpet(section, out)
             fields = FieldReader.new(section).skip(4)
@@ -98,6 +102,8 @@ module Badline
             fields.skip(fields_before_board(section))
             out.int("bank_latch", latches >> 4).int("socket", latches.anybits?(BANK_RAM) ? 0 : 1)
             out.int("system_latch", 0).bytes("ram", fields.string(EXPANSION))
+            fields.skip(Dongle::AT)
+            Dongle.import(fields.bytes(Dongle::LENGTH), out)
           end
 
           # The RAM and the screen RAM before a SuperPET's board.

data/lib/badline/snapshot/vice/vic20.rb

@@ -0,0 +1,70 @@
+# frozen_string_literal: true
+
+require "badline/snapshot/vice/vic20_cpu"
+require "badline/snapshot/vice/vic20_mem"
+require "badline/snapshot/vice/vic20_vici"
+require "badline/snapshot/vice/vic20_restore"
+
+module Badline
+  module Snapshot
+    module Vice
+      # xvic's modules for the VIC-20, PAL and NTSC: the CPU, the RAM, the
+      # VIC-I with the colour RAM, and both VIAs, written from badline's
+      # machine and read into it. Each module's file says what maps and
+      # what is approximated. The VIAs' are xpet's (PET::VIA). They go
+      # through the machine's own keyed fields (Keyed), which a save writes
+      # and a load reads.
+      module Vic20
+        # The modules xvic 3.10 resets the machine without, each as xvic
+        # leaves them with nothing attached: no cartridge, no file system
+        # drive open, the cassette port on with a datasette in it, the
+        # control port on with the joystick released, and nothing in the
+        # user port. With no drive modules xvic keeps its own drives as they
+        # are.
+        CARTRIDGE = ["VIC20CART", 2, 1, [0xff, 0xff, 0xff, 0xff, 0x00]].freeze
+        PERIPHERALS = [
+          ["FSDRIVE", 0, 0, Array.new(258, 0)], ["TAPEPORT", 1, 0, [0x01, 0x01]], ["JOYPORT0", 0, 0, [0x01]],
+          ["JOYSTICK0", 1, 2, [0x00, 0x00]], ["USERPORT", 1, 0, [0x01, 0x00]]
+        ].freeze
+
+        module_function
+
+        # The modules xvic 3.10 needs, in its order, describing `machine`,
+        # which Machine::Settling has brought between instructions, from
+        # its keyed modules, `sections`.
+        def export(machine, sections)
+          readers = {}
+          sections.each { |section| readers[section.name] = Keyed::Reader.parse(section) }
+          [MainCPU.export(machine), Mem.export(machine, reader(readers, "BL-MACHINE")), section(*CARTRIDGE),
+           VICI.export(machine, reader(readers, "BL-VICI"), reader(readers, "BL-COLORRAM")),
+           PET::VIA.export(reader(readers, "BL-VIA1"), "VIA1"), PET::VIA.export(reader(readers, "BL-VIA2"), "VIA2")] +
+            PERIPHERALS.map { |entry| section(*entry) }
+        end
+
+        def section(name, major, minor, bytes) = FieldWriter.new.bytes(bytes).section(name, major, minor)
+
+        def reader(readers, name) = readers[name] || Keyed::Reader.missing(name)
+
+        # How the machine xvic saved was built: the RAM from VIC20MEM's
+        # blocks, and the model from the lines of the VIC-I's picture.
+        def setup(container)
+          memory = container[Mem::NAME]
+          raise FormatError, "the snapshot has no #{Mem::NAME} module" if memory.nil?
+          raise FormatError, "#{memory}: badline doesn't read this version" unless Mem.reads?(memory)
+
+          ram = Mem.ram_configuration(memory)
+          raise FormatError, "#{memory}: RAM in blocks badline doesn't fit together" if ram.nil?
+
+          Vic20Setup.new(ram:, model: model(container))
+        end
+
+        def model(container)
+          vic = container[VICI::NAME]
+          return "pal" if vic.nil? || !VICI.reads?(vic)
+
+          VICI.model(vic) || raise(FormatError, "#{vic}: a picture of a size badline's VIC-Is don't draw")
+        end
+      end
+    end
+  end
+end

data/lib/badline/snapshot/vice/vic20_cpu.rb

@@ -0,0 +1,61 @@
+# frozen_string_literal: true
+
+module Badline
+  module Snapshot
+    module Vice
+      module Vic20
+        # The 6502 as xvic 3.10 saves it, MAINCPU 1.4, 83 bytes: the clock,
+        # the registers, four dwords (the last opcode and three xvic keeps
+        # at 0 between instructions), five clocks of the IRQ and NMI
+        # bookkeeping, then the IRQ and NMI source counts and the pending
+        # interrupts. It is x64sc's MAINCPU 1.4 without the BA flags and
+        # the two clocks at its end, and xpet's MAINCPU 1.3 with one more
+        # dword. The layout was inferred from xvic's snapshots against its
+        # monitor's registers and clock.
+        #
+        # Written: the clock and the registers, which between instructions
+        # are the whole CPU, with VIA 2 counted as an IRQ source while it
+        # pulls the line, and VIA 1 as an NMI source. VICE's interrupt
+        # clocks are written as long past.
+        #
+        # Read: the clock and the registers. The CPU starts on an
+        # instruction boundary, as xvic's snapshot is taken on one.
+        module MainCPU
+          NAME = "MAINCPU"
+          MAJOR = 1
+          MINOR = 4
+          SIZE = 83
+          IK_IRQ = 0x02
+
+          module_function
+
+          def reads?(section) = section.major == MAJOR && section.minor == MINOR && section.data.bytesize == SIZE
+
+          def export(machine)
+            cpu = machine.cpu
+            fields = FieldWriter.new.qword(machine.cycles)
+            [cpu.a, cpu.x, cpu.y, cpu.stack_pointer].each { |register| fields.byte(register) }
+            fields.word(cpu.program_counter).byte(cpu.p)
+            4.times { fields.dword(0) }
+            5.times { fields.qword(0) }
+            irqs = machine.via2.irq? ? 1 : 0
+            fields.dword(irqs).dword(machine.via1.irq? ? 1 : 0).dword(irqs.positive? ? IK_IRQ : 0)
+            fields.section(NAME, MAJOR, MINOR)
+          end
+
+          # The clock and the registers by their BL-CPU keys, in a keyed
+          # module's writer, and the clock.
+          def import(section, out)
+            fields = FieldReader.new(section)
+            clock = fields.qword
+            out.int("a", fields.byte).int("x", fields.byte).int("y", fields.byte).int("sp", fields.byte)
+            out.int("pc", fields.word).int("p", fields.byte).int("cycles", clock)
+            clock
+          end
+
+          def clock(section) = FieldReader.new(section).qword
+        end
+      end
+    end
+  end
+end

data/lib/badline/snapshot/vice/vic20_mem.rb

@@ -0,0 +1,85 @@
+# frozen_string_literal: true
+
+module Badline
+  module Snapshot
+    module Vice
+      module Vic20
+        # The VIC-20's RAM as xvic 3.10 saves it, VIC20MEM 1.1: a byte of
+        # the expansion blocks that hold RAM (bit 0 the 3K at $0400, bits
+        # 1-3 BLK1-BLK3, bit 5 BLK5), the bytes the CPU's and the VIC's
+        # data lines last held, a byte badline doesn't model (0, 1 or 6 in
+        # xvic's snapshots, not following the blocks), then the RAM: $0000-$03FF, $1000-$1FFF, the 3K at
+        # $0400-$0FFF, and BLK1, BLK2, BLK3 and BLK5 in turn, each only if
+        # it holds RAM. The layout was inferred from xvic's snapshots of
+        # each -memory setting, with each block filled with a byte of its
+        # own and the data lines left at a byte the monitor wrote. Colour
+        # RAM is in the VIC-I's module (VICI).
+        #
+        # Written and read: the RAM and both data lines' bytes. The fourth
+        # byte is written as 0, and not read.
+        module Mem
+          NAME = "VIC20MEM"
+          MAJOR = 1
+          MINOR = 1
+          # Each expansion block's bit in the first byte, and the bytes it
+          # holds, as Badline::Vic20::Bus::BLOCKS names them.
+          BLOCK_BITS = { ram123: 0x01, blk1: 0x02, blk2: 0x04, blk3: 0x08, blk5: 0x20 }.freeze
+          INTERNAL = [[0x0000, 0x0400], [0x1000, 0x1000]].freeze
+
+          module_function
+
+          def reads?(section) = section.major == MAJOR && section.minor == MINOR
+
+          # The blocks the first byte names, or nil for bits no block has.
+          def blocks(section)
+            bits = FieldReader.new(section).byte
+            names = BLOCK_BITS.select { |_, bit| bits.anybits?(bit) }.keys
+            names.sum { |name| BLOCK_BITS[name] } == bits ? names : nil
+          end
+
+          # The RAM configuration (Badline::Vic20::Bus::RAM_CONFIGURATIONS)
+          # whose blocks the module has, or nil.
+          def ram_configuration(section)
+            names = blocks(section)
+            return nil if names.nil?
+
+            Badline::Vic20::Bus::RAM_CONFIGURATIONS.find { |_, blocks| blocks.sort == names.sort }&.first
+          end
+
+          # The regions the RAM comes in, as [address, length].
+          def regions(names)
+            INTERNAL + Badline::Vic20::Bus::BLOCKS.filter_map do |name, (page, pages)|
+              [page << 8, pages << 8] if names.include?(name)
+            end
+          end
+
+          # The module for `machine`, with the data lines' bytes from its
+          # BL-MACHINE fields, `machine_fields`.
+          def export(machine, machine_fields)
+            names = Badline::Vic20::Bus::RAM_CONFIGURATIONS.fetch(machine.ram_configuration)
+            fields = FieldWriter.new.byte(names.sum { |name| BLOCK_BITS[name] })
+            fields.byte(machine_fields.int("bus.data", 0)).byte(machine_fields.int("bus.video_data", 0))
+            fields.byte(0)
+            ram = machine.ram
+            regions(names).each do |address, length|
+              fields.bytes(Array.new(length) { |offset| ram.peek(address + offset) })
+            end
+            fields.section(NAME, MAJOR, MINOR)
+          end
+
+          # The RAM into `ram`, the machine's 48K at power-on, and the data
+          # lines' bytes into BL-MACHINE's writer `out`.
+          def import(section, ram, out)
+            fields = FieldReader.new(section)
+            names = blocks(section) || []
+            fields.skip(1)
+            out.int("bus.data", fields.byte).int("bus.video_data", fields.byte)
+            fields.skip(1)
+            regions(names).each { |address, length| ram[address, length] = fields.bytes(length) }
+            ram
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/snapshot/vice/vic20_restore.rb

@@ -0,0 +1,124 @@
+# frozen_string_literal: true
+
+module Badline
+  module Snapshot
+    module Vice
+      module Vic20
+        # Restores a VIC-20 from a snapshot xvic wrote. The modules badline
+        # reads become the machine's own keyed modules (Keyed), which it
+        # loads as it loads its own snapshot. Whatever they don't set stays
+        # as the machine has it at power-on: the VIC-I's sound and picture,
+        # which it paints afresh, a cartridge, the datasette's tape, the
+        # disk device 8 serves and a true drive, which xvic's drive modules
+        # don't reach.
+        module Restore
+          # MAINCPU and VIC20MEM hold the machine itself, so a version badline
+          # doesn't read fails the restore. The others are left out and
+          # reported.
+          READ = [MainCPU::NAME, Mem::NAME, VICI::NAME, "VIA1", "VIA2"].freeze
+          REQUIRED = [MainCPU::NAME, Mem::NAME].freeze
+
+          module_function
+
+          # Applies the modules badline reads to `computer`, and returns a
+          # Report. The snapshot goes into a new machine first, so one that
+          # fails leaves `computer` as it was, and one of a machine built
+          # another way fails too.
+          def import(container, computer)
+            unless computer.family == :vic20
+              raise FormatError, "the snapshot is of a VIC-20, not a #{Image::FAMILIES.fetch(computer.family.to_s)}"
+            end
+
+            setup = Vic20.setup(container)
+            ours = Vic20Setup.new(ram: computer.ram_configuration, model: computer.model)
+            raise FormatError, "the snapshot is of a VIC-20 with #{setup}, not #{ours}" unless setup == ours
+
+            apply(container, setup.build)
+            computer.power_cycle!
+            report = apply(container, computer)
+            kept = computer.mounted? ? ["the disk mounted in device 8 stays mounted"] : []
+            Report.new(applied: report.applied, ignored: report.ignored + kept)
+          end
+
+          # Applies the modules badline reads to `computer`, a machine built
+          # as the snapshot's was, and returns the Report.
+          def apply(container, computer)
+            applied = []
+            ignored = []
+            READ.each do |name|
+              section = container[name]
+              next if section.nil?
+
+              if reads?(section)
+                applied << name
+              else
+                raise FormatError, "#{section}: badline doesn't read this version" if REQUIRED.include?(name)
+
+                ignored << "#{section}: badline doesn't read this version, left out"
+              end
+            end
+            REQUIRED.each do |name|
+              raise FormatError, "the snapshot has no #{name} module" unless applied.include?(name)
+            end
+            computer.load_modules(Keyed::Modules.new(modules(container, computer, applied)))
+            Report.new(applied:, ignored: ignored + left_out(container, applied))
+          end
+
+          def reads?(section)
+            case section.name
+            when MainCPU::NAME then MainCPU.reads?(section)
+            when Mem::NAME then Mem.reads?(section)
+            when VICI::NAME then VICI.reads?(section)
+            else PET::VIA.reads?(section)
+            end
+          end
+
+          # The machine's keyed modules: its own as they stand, with those
+          # the modules `applied` names stand for in their place.
+          def modules(container, computer, applied)
+            own = {}
+            computer.save_modules.each { |section| own[section.name] = section }
+            ram = Keyed::Reader.parse(own.fetch("BL-RAM")).bytes("ram", "".b).bytes
+            own["BL-MACHINE"] = Keyed.section("BL-MACHINE") do |out|
+              out.text("family", "vic20")
+              Vic20Setup.new(ram: computer.ram_configuration, model: computer.model).write_fields(out)
+              out.int("cycles", MainCPU.clock(container[MainCPU::NAME]))
+              out.bool("nmi_asserted", via_irq?(container, "VIA1", applied))
+              Mem.import(container[Mem::NAME], ram, out)
+            end
+            own["BL-RAM"] = Keyed.section("BL-RAM") { |out| out.bytes("ram", ram) }
+            own["BL-CPU"] = Keyed.section("BL-CPU") { |out| MainCPU.import(container[MainCPU::NAME], out) }
+            vic(container, computer, applied, own)
+            %w[VIA1 VIA2].each do |name|
+              next unless applied.include?(name)
+
+              own["BL-#{name}"] = Keyed.section("BL-#{name}") { |out| PET::VIA.import(container[name], out) }
+            end
+            own.values
+          end
+
+          def vic(container, computer, applied, own)
+            return unless applied.include?(VICI::NAME)
+
+            section = container[VICI::NAME]
+            own["BL-VICI"] = Keyed.section("BL-VICI") { |out| VICI.import(section, out, computer.vic.profile) }
+            own["BL-COLORRAM"] = Keyed.section("BL-COLORRAM") { |out| out.bytes("ram", VICI.colors(section)) }
+          end
+
+          # Whether the VIA pulls its interrupt line: a flag it has enabled.
+          def via_irq?(container, name, applied)
+            return false unless applied.include?(name)
+
+            bytes = FieldReader.new(container[name]).bytes(PET::VIA::SIZE)
+            bytes[0x12].anybits?(bytes[0x13] & 0x7f)
+          end
+
+          def left_out(container, applied)
+            container.sections.reject { |section| applied.include?(section.name) }
+                     .map { |section| "#{section}: badline doesn't read this module, left out" }
+          end
+        end
+      end
+    end
+  end
+end