badline 0.18.0 → 0.19.0

data/lib/badline/chips/cpu/microcode.rb

@@ -95,6 +95,14 @@ module Badline
         op_int_vector_low op_int_vector_high
       ].freeze
 
+      # RES runs BRK's sequence with its three stack writes turned into
+      # reads, which still count S down, and reads the vector at $FFFC. Its
+      # first two cycles read the program counter and leave it where it was.
+      RESET_PLAN = %i[
+        op_reset_dummy op_reset_dummy op_reset_stack op_reset_stack op_reset_stack
+        op_int_vector_low op_int_vector_high
+      ].freeze
+
       SPECIAL_PLANS = {
         brk: BRK_PLAN, jam: JAM_PLAN, jsr: JSR_PLAN, rts: RTS_PLAN,
         rti: RTI_PLAN, pha: PUSH_PLAN, php: PUSH_PLAN,
@@ -181,6 +189,7 @@ module Badline
       FETCH_WRITES = Microcode.write_mask(FETCH_PLAN)
       INTERRUPT_WRITES = Microcode.write_mask(INTERRUPT_PLAN)
       JAMMED_WRITES = Microcode.write_mask(JAMMED_PLAN)
+      RESET_WRITES = Microcode.write_mask(RESET_PLAN)
       MICROCODE = Microcode.table
 
       # The instruction methods, in a fixed order a snapshot names them by.
@@ -190,6 +199,7 @@ module Badline
       FETCH = -1
       INTERRUPT = -2
       JAMMED = -3
+      RESET = -4
     end
   end
 end

data/lib/badline/chips/rriot.rb

@@ -74,7 +74,10 @@ module Badline
 
       # Everything the RRIOT holds but its timer's counter, for comparing
       # it at two points.
-      def idle_state = [*@ram, @ora, @orb, @ddra, @ddrb, *@timer.state, @timer.flag]
+      def idle_state = [*@ram, *port_state]
+
+      # The ports and the timer but for its counter.
+      def port_state = [@ora, @orb, @ddra, @ddrb, *@timer.state, @timer.flag]
 
       def read_rom(addr) = @rom[addr & 0x3ff]
 

data/lib/badline/chips/sid/decimator.rb

@@ -21,7 +21,7 @@ module Badline
         end
 
         # Cycles until the current window closes, counting the next one as 1.
-        attr_reader :cycles_to_close
+        attr_reader :cycles_to_close, :rate, :clock_hz
 
         # How far the current window has got, in a keyed snapshot module
         # (Snapshot::Keyed) under `prefix`. The clock and the rate are the

data/lib/badline/chips/sid/keyed_parts.rb

@@ -221,7 +221,11 @@ module Badline
       # voice's under voice1. to voice3., and the filter's under filter.
       # and ext. Saving catches the DSP up first, so no span or deferred
       # write is left to save. What the registers decode to is worked out
-      # from them on load.
+      # from them on load. A recording SID also saves how far its recording
+      # has got under rec., with the rate, the clock and the filter chunk it
+      # records at: the samples' windows bound the filter's steps, so a SID
+      # loaded from it that records at the same rate and clock carries on
+      # from that window and integrates the steps the saved one does.
       module KeyedState
         def save_fields(out)
           catch_up
@@ -230,6 +234,8 @@ module Badline
           @voice2.save_fields(out, "voice2.")
           @voice3.save_fields(out, "voice3.")
           @filter.save_fields(out, "filter.")
+          recording = @decimator || @resumed_recording
+          save_recording(out, recording) if recording
           out
         end
 
@@ -243,23 +249,7 @@ module Badline
           @voice2.load_fields(input, "voice2.")
           @voice3.load_fields(input, "voice3.")
           @filter.load_fields(input, "filter.")
-        end
-
-        # How far the recording has got into the sample it is averaging,
-        # under `prefix`, for a host that carries on recording from a
-        # snapshot: it calls #record, then #load_recording_fields.
-        def save_recording_fields(out, prefix)
-          decimator = @decimator
-          raise ArgumentError, "the SID isn't recording" if decimator.nil?
-
-          decimator.save_fields(out, prefix)
-        end
-
-        def load_recording_fields(input, prefix)
-          decimator = @decimator
-          raise ArgumentError, "the SID isn't recording" if decimator.nil?
-
-          decimator.load_fields(input, prefix)
+          load_recording(input)
         end
 
         def restored!
@@ -272,6 +262,49 @@ module Badline
 
         private
 
+        def save_recording(out, decimator)
+          out.int("rec.rate", decimator.rate).int("rec.clock_hz", decimator.clock_hz)
+          out.int("rec.filter_chunk", @filter_chunk)
+          decimator.save_fields(out, "rec.")
+        end
+
+        # A SID recording already carries on from the loaded window when it
+        # records at its rate, clock and filter chunk, and starts a new
+        # window otherwise.
+        def load_recording(input)
+          @resumed_recording = nil
+          live = @decimator
+          loaded = loaded_recording(input)
+          chunk = loaded ? input.int("rec.filter_chunk", @filter_chunk) : @filter_chunk
+          if live.nil?
+            @filter_chunk = chunk
+            @resumed_recording = loaded
+          elsif loaded && chunk == @filter_chunk && loaded.rate == live.rate && loaded.clock_hz == live.clock_hz
+            @decimator = loaded
+          else
+            @decimator = Decimator.new(clock_hz: live.clock_hz, rate: live.rate)
+          end
+        end
+
+        def loaded_recording(input)
+          rate = input.int("rec.rate", 0)
+          return unless rate.positive?
+
+          decimator = Decimator.new(clock_hz: input.int("rec.clock_hz", Region::PAL.clock_hz), rate:)
+          decimator.load_fields(input, "rec.")
+          decimator
+        end
+
+        # The window a loaded snapshot's recording had got to, when this
+        # recording is at its rate, clock and filter chunk.
+        def resumed_recording(rate, filter_chunk, clock_hz)
+          resumed = @resumed_recording
+          @resumed_recording = nil
+          return if resumed.nil? || filter_chunk != @filter_chunk
+
+          resumed if resumed.rate == rate && resumed.clock_hz == clock_hz
+        end
+
         def restore_voice(voice, base)
           control = register(base + 4)
           voice.waveform.restore_registers(register(base) | (register(base + 1) << 8),

data/lib/badline/chips/sid.rb

@@ -70,6 +70,7 @@ module Badline
         @pending_cycles = 0
         @deferred_writes = []
         @decimator = nil
+        @resumed_recording = nil
         @samples = []
         @voice_samples = nil
         @filter_chunk = filter_chunk
@@ -120,12 +121,15 @@ module Badline
       # Starts collecting the output, averaged down to `rate` samples a
       # second, for #drain_samples. `filter_chunk` overrides the one the SID
       # was built with, for a machine that built its own. `clock_hz` is the
-      # rate the SID's cycles are taken to run at.
+      # rate the SID's cycles are taken to run at. A SID loaded from a
+      # recording one carries on from the window that one had got to, at the
+      # same rate, clock and filter chunk.
       def record(rate:, filter_chunk: @filter_chunk, clock_hz: Region::PAL.clock_hz)
         synthesize!
         catch_up
+        resumed = resumed_recording(rate, filter_chunk, clock_hz)
         @filter_chunk = filter_chunk
-        @decimator = Decimator.new(clock_hz:, rate:)
+        @decimator = resumed || Decimator.new(clock_hz:, rate:)
         @samples = []
       end
 

data/lib/badline/chips/vic_i/keyed_parts.rb

@@ -88,7 +88,8 @@ module Badline
       # The VIC-I's fields in a keyed snapshot module (Snapshot::Keyed): the
       # registers, the beam, the frame's length in lines and whether the
       # next interlaced field is the long one, the text window's counters
-      # and the fetch in flight, the painter's lines under line.*, the picture, and the sound
+      # and the fetch in flight, the light pen's latch and line under pen.*,
+      # the painter's lines under line.*, the picture, and the sound
       # under sound.* What the registers decode to, where the line's fetches
       # end and the next event are worked out on load.
       module KeyedState
@@ -98,6 +99,7 @@ module Badline
           out.bool("window_open", @window_open).bool("window_done", @window_done).int("row_start", @row_start)
           out.int("matrix", @matrix).int("char_line", @char_line).int("text_rows", @text_rows)
           out.int("fetch_from", @fetch_from).int("fetched", @fetched).int("code", @code)
+          out.int("pen.x", @pen_x).int("pen.y", @pen_y).bool("pen.low", @pen_low)
           out.int("line.layout", LINE_LAYOUT)
           @painter.save_fields(out)
           @sound&.save_fields(out, "sound.")
@@ -119,6 +121,9 @@ module Badline
           @fetch_from = input.int("fetch_from", @fetch_from)
           @fetched = input.int("fetched", @fetched)
           @code = input.byte("code", @code)
+          @pen_x = input.byte("pen.x", @pen_x)
+          @pen_y = input.byte("pen.y", @pen_y)
+          @pen_low = input.bool("pen.low", @pen_low)
           line = input.int("line.layout", 0) == LINE_LAYOUT
           input.adjust("line in progress from another renderer, restarted") unless line || input.missing?
           @painter.load_fields(input, line)

data/lib/badline/chips/vic_i/light_pen.rb

@@ -0,0 +1,89 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class VICI
+      # The light pen input, the line the VIC-20 shares with the joystick's
+      # fire button, and the position a falling edge on it latches into
+      # $9006 and $9007.
+      #
+      # $9006 reads 2h + 1, where h is the edge's column plus two, wrapping
+      # at the line's end, and $9007 bits 8-1 of the raster count in the
+      # cycle after the edge. Around the cycle where the count turns to 0
+      # the latch reads otherwise:
+      #
+      # - An edge from 8 cycles before that cycle to 1 after it latches as
+      #   an edge in the cycle after it would, with $9007 at 0, but for an
+      #   edge 2 cycles before it, which latches an even $9006, one less.
+      # - Before that, an edge latches nothing while the count read its
+      #   last value of the frame in the cycle before the edge: line 311 on
+      #   the 6561, and 261, past the last line, on the 6560.
+      module LightPen
+        # Where the window around the count's turn to 0 starts and ends,
+        # in cycles from that turn, and the edge in it that latches an even
+        # $9006.
+        WRAP_WINDOW = (-8..1)
+        WRAP_EVEN = -2
+
+        # The pen's line, low while the pen sees the beam or fire is held.
+        def lightpen_level(high)
+          low = !high
+          return if low == @pen_low
+
+          @pen_low = low
+          pen_fell if low
+        end
+
+        private
+
+        def power_on_pen!
+          @pen_x = @pen_y = 0
+          @pen_low = false
+        end
+
+        def pen_fell
+          line = @rasterline
+          column = @column
+          from_wrap = cycles_from_wrap(line, column)
+          if WRAP_WINDOW.cover?(from_wrap)
+            latch_pen(@frame_wrap + 1, 0, from_wrap == WRAP_EVEN)
+          elsif !pen_blocked?(line, column)
+            next_column = column + 1
+            if next_column == @cycles_per_line
+              next_column = 0
+              line = line == @frame_lines - 1 ? 0 : line + 1
+            end
+            latch_pen(column, count_at(line, next_column) >> 1, false)
+          end
+        end
+
+        # How many cycles the beam is past the cycle where the count turns
+        # to 0, negative before it. On the 6561 the count turns as the
+        # frame starts, so the frame's first cycles are past it.
+        def cycles_from_wrap(line, column)
+          position = (line * @cycles_per_line) + column
+          return position if position < 2 && @frame_wrap == @cycles_per_line
+
+          position - ((@frame_lines - 1) * @cycles_per_line) - @frame_wrap
+        end
+
+        # Whether the count read its last value of the frame in the cycle
+        # before this one.
+        def pen_blocked?(line, column)
+          column -= 1
+          if column.negative?
+            column = @cycles_per_line - 1
+            line = line.zero? ? @frame_lines - 1 : line - 1
+          end
+          last = @frame_wrap > @count_column ? @frame_lines : @frame_lines - 1
+          count_at(line, column) == last
+        end
+
+        def latch_pen(column, count, even)
+          @pen_x = (2 * ((column + 2) % @cycles_per_line)) + (even ? 0 : 1)
+          @pen_y = count
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/vic_i.rb

@@ -2,6 +2,7 @@
 
 require "badline/chips/vic_i/painter"
 require "badline/chips/vic_i/text_window"
+require "badline/chips/vic_i/light_pen"
 require "badline/chips/vic_i/sound"
 require "badline/chips/vic_i/keyed_parts"
 
@@ -16,7 +17,7 @@ module Badline
     # The registers repeat through $9000-$90FF. $9003 bit 7 and $9004 read
     # the raster count, its bit 0 and bits 8-1, which on the 6561 is the
     # raster line (see Profile for the 6560's). $9006 and $9007 read the
-    # light pen, which nothing triggers yet, and $9008 and $9009 the two
+    # light pen's latch (LightPen), and $9008 and $9009 the two
     # pots, which read $FF with nothing plugged in. The other registers
     # read back what was written to them.
     #
@@ -45,6 +46,7 @@ module Badline
     # blanked.
     class VICI
       include TextWindow
+      include LightPen
 
       # What a VIC-I sets for the machine: the clock, the raster's cycles
       # per line and lines per frame, how many lines at the top of the frame
@@ -149,6 +151,7 @@ module Badline
         @fetched = @slot = 0
         @code = 0
         @painter.power_on!(@frame_lines - 1)
+        power_on_pen!
         schedule
       end
 
@@ -195,7 +198,8 @@ module Badline
         case register
         when 0x03 then ((raster_count & 0x01) << 7) | (@registers[3] & 0x7f)
         when 0x04 then raster_count >> 1
-        when 0x06, 0x07 then 0
+        when 0x06 then @pen_x
+        when 0x07 then @pen_y
         when 0x08, 0x09 then 0xff
         else @registers[register]
         end
@@ -218,17 +222,18 @@ module Badline
       end
 
       # The raster count $9003 and $9004 read (see Profile).
-      def raster_count
-        line = @rasterline
-        column = @column
+      def raster_count = count_at(@rasterline, @column)
+
+      private
+
+      # What the count reads at +column+ of +line+ in this frame.
+      def count_at(line, column)
         return line if column < @count_column
         return 0 if line == @frame_lines - 1 && column >= @frame_wrap
 
         line + 1
       end
 
-      private
-
       def event(column)
         if column == @cycles_per_line
           column = @column = 0

data/lib/badline/drives/model1541/sector_reader.rb

@@ -13,12 +13,22 @@ module Badline
       # that sector's data block, whatever it holds.
       module SectorReader
         HEADER_BITS = 10 * 8
-        DATA_BITS = 325 * 8
         SYNC = /1{10,}/
 
+        # A data block as far as its checksum: its ID, 256 bytes and the
+        # checksum. The DOS writes two more after them, and switches back to
+        # read mode a few bits into the last, so the gap that was there
+        # before finishes its last code.
+        CHECKED_BYTES = 258
+        CHECKED_BITS = CHECKED_BYTES * 10
+
+        # The codes of two $0 nibbles, which finish the last group of
+        # CHECKED_BITS.
+        PADDING = "01010" * 4
+
         # A sector as read: its decoded header, [ID, checksum, sector, track,
         # the second ID byte, the first, ...], and its decoded data block,
-        # [ID, 256 data bytes, checksum, ...], nil when there isn't one that
+        # [ID, 256 data bytes, checksum], nil when there isn't one that
         # decodes.
         Sector = Struct.new(:header, :data)
 
@@ -62,10 +72,17 @@ module Badline
             next unless header && header[0] == Disk::HEADER_ID
 
             data_sync = SYNC.match(bits, pos + HEADER_BITS)
-            yield header, data_sync && decode(bits, data_sync.end(0), DATA_BITS)
+            yield header, data_sync && decode_data(bits, data_sync.end(0))
           end
         end
 
+        def decode_data(bits, pos)
+          slice = bits[pos, CHECKED_BITS]
+          return unless slice.length == CHECKED_BITS
+
+          GCR.decode([slice + PADDING].pack("B*").bytes)&.first(CHECKED_BYTES)
+        end
+
         def decode(bits, pos, count)
           slice = bits[pos, count]
           return unless slice.length == count

data/lib/badline/drives/model1541.rb

@@ -39,6 +39,7 @@ module Badline
         @via2 = DiskVIA.new(start: 0x1c00, mechanism: @mechanism)
         @bus = Bus.new(rom: rom || ROM.load("dos1541.rom", 0xc000), via1: @via1, via2: @via2)
         @cpu = CPU.new(@bus, debug:)
+        @cpu.power_on!
         @clock_hz = CLOCK_HZ
         @idle_loop = IDLE_LOOP
         @host_clock_hz = host_clock_hz

data/lib/badline/drives/model1551.rb

@@ -97,6 +97,7 @@ module Badline
         @host_tia = Chips::TIA.new
         @bus = Bus.new(rom: rom || ROM.load("dos1551.rom", 0xc000), port: @port, tia: @tia)
         @cpu = CPU.new(@bus, debug:)
+        @cpu.power_on!
         @idle_loop = IDLE_LOOP
         @host_clock_hz = host_clock_hz
         @phase = 0

data/lib/badline/drives/model1571.rb

@@ -68,6 +68,7 @@ module Badline
         @fdc = WD1770.new
         @bus = Bus.new(rom: rom || ROM.load("dos1571.rom", 0x8000), via1: @via1, via2: @via2, cia: @cia, fdc: @fdc)
         @cpu = CPU.new(@bus, debug:)
+        @cpu.power_on!
         @fdc.cpu = @cpu
         @idle_loop = IDLE_LOOP
         @host_clock_hz = host_clock_hz

data/lib/badline/drives/model1581.rb

@@ -87,6 +87,7 @@ module Badline
         @cia = Chips::CIA.new(start: 0x4000, peripheral: @serial_port, tod_hz: 0)
         @bus = Bus.new(rom: rom || ROM.load("dos1581.rom", 0x8000), cia: @cia, fdc: @fdc, drive: self)
         @cpu = CPU.new(@bus, debug:)
+        @cpu.power_on!
         @idle_loop = IDLE_LOOP
         @host_clock_hz = host_clock_hz
         @phase = 0

data/lib/badline/drives/model2031.rb

@@ -52,6 +52,7 @@ module Badline
         @via2 = Model1541::DiskVIA.new(start: 0x1c00, mechanism: @mechanism)
         @bus = Bus.new(rom: rom || ROM.load("dos2031.rom", 0xc000), via1: @via1, via2: @via2)
         @cpu = CPU.new(@bus, debug:)
+        @cpu.power_on!
         @clock_hz = CLOCK_HZ
         @idle_loop = IDLE_LOOP
         @host_clock_hz = host_clock_hz

data/lib/badline/drives/model4040/mechanism.rb

@@ -79,9 +79,10 @@ module Badline
           turn(1, drives.nobits?(0x10), drives & 0x03)
         end
 
-        # Whether a cycle would change nothing: both motors off and no byte
-        # ready under way.
-        def quiet? = !@motors[0] && !@motors[1] && !@ca1_low
+        # Whether a cycle would change nothing: no byte ready under way, and
+        # each drive's motor off or turning with no disk in it, as both turn
+        # from the bump at boot until the run-down.
+        def quiet? = !@ca1_low && still?(0) && still?(1)
 
         # What the drives hold, for comparing them at two points.
         def idle_state = [*@half_tracks, *@phases, *@motors, *@syncs, @data_in]
@@ -98,6 +99,8 @@ module Badline
 
         def selected_drive = @rriot.port_b_output & 0x01
 
+        def still?(drive) = !@motors[drive] || @disks[drive].nil?
+
         def turn(drive, motor, phase)
           step(drive, phase) if phase != @phases[drive]
           motor_off(drive) if @motors[drive] && !motor

data/lib/badline/drives/model4040.rb

@@ -26,7 +26,11 @@ module Badline
     # At reset the controller waits for the common RAM's $0400 to read 0,
     # starts, and writes its timer's period there. The interface processor
     # tests its RAM and ROMs, has the controller reset its drives, and
-    # bumps both heads to track 1.
+    # bumps both heads to track 1. The motors run from then until the
+    # run-down after the first job, about 9.5 million host cycles in for a
+    # directory LOAD, or 8.8 million with no job. A motor turning with no
+    # disk in its drive changes nothing, so a unit with no disks sleeps
+    # from the bump on, and one with a disk only after the run-down.
     class Model4040
       include Model8050::Board
       include Model8050::Idle
@@ -61,7 +65,9 @@ module Badline
         build_ip(dos_rom || ROM.load(dos_file, dos_start))
         build_fdc(fdc_rom || ROM.read(fdc_file))
         @ip_cpu = IPCPU.new(@ip_bus)
+        @ip_cpu.power_on!
         @fdc_cpu = FDCCPU.new(@fdc_bus)
+        @fdc_cpu.power_on!
         init_idle(ip_loop, fdc_loop)
         @ieee_bus.attach(self)
       end
@@ -128,6 +134,16 @@ module Badline
         @fdc_cpu.cycle!
         @cycles += 1
       end
+
+      # One cycle of the FDC's side alone, as step runs it (Model8050::Idle).
+      def fdc_step
+        @mechanism.cycle!
+        @via.cycle!
+        @rriot.cycle!
+        @fdc_cpu.irq = @rriot.irq?
+        @fdc_cpu.cycle!
+        @cycles += 1
+      end
     end
 
     # The 3040: the 4040's board with the first DOS 2.1, as xpet's 3040

data/lib/badline/drives/model8050/board.rb

@@ -68,6 +68,8 @@ module Badline
         private
 
         def run_cycle
+          return fdc_alone_cycle if @fdc_alone
+
           step
           watch_loops if @idle_skip
         end

data/lib/badline/drives/model8050/dos_board.rb

@@ -15,7 +15,9 @@ module Badline
       # Drives::Engine::Core does: each host cycle adds 1 MHz of phase, and
       # every whole host period in it runs a cycle of both processors. While
       # both processors idle, it sleeps instead, and the readers of its
-      # parts catch it up first.
+      # parts catch it up first. Asleep, a host cycle only counts towards
+      # the one planned to wake the unit, which its own doze wakes, and a
+      # line the controller moves wakes it at once (host_written!).
       module DOSBoard
         attr_reader :device, :ieee_bus
 
@@ -51,9 +53,6 @@ module Badline
         # (IEEEPort).
         def ieee_low_lines(atn) = @ieee_port.ieee_low_lines(atn)
 
-        # The controller pushed its lines into the bus.
-        def host_written! = nil
-
         # Which LEDs are lit, as the unit's port drives them. They hold
         # still while the unit sleeps, so reading them leaves it asleep.
         def leds = @ieee_port.leds
@@ -62,16 +61,20 @@ module Badline
 
         # Runs the drive cycles that fall in one host cycle, then takes the
         # controller's lines for the next. Asleep, the unit owes the cycles
-        # instead, and wakes once the controller has moved a line.
+        # instead, and wakes once the controller has moved a line, as it
+        # does with a processor owing cycles (dozing?).
         def host_cycle!
+          return if slept_through?
+
           phase = @phase + CLOCK_HZ
           while phase >= @host_clock_hz
             @asleep ? owe_cycle : run_cycle
             phase -= @host_clock_hz
           end
           @phase = phase
-          settle! if @asleep && @ieee_port.lines_moved?
+          settle! if dozing? && @ieee_port.lines_moved?
           @ieee_port.latch_host
+          plan_sleep if @asleep
         end
 
         def cycle!
@@ -79,12 +82,52 @@ module Badline
           run_cycle
         end
 
+        # The controller pushed its lines into the bus. A line it moved
+        # wakes a unit that owes cycles, which saw the lines as they stood.
+        def host_written!
+          settle! if dozing? && @ieee_port.lines_moved?
+        end
+
         private
 
         def settled(part)
           settle!
           part
         end
+
+        # Asleep, a host cycle only counts towards the one planned to wake
+        # the unit (plan_sleep). Returns whether it did.
+        def slept_through?
+          return false unless @planned
+
+          @slept += 1
+          doze if @slept == @wake_at
+          true
+        end
+
+        # Plans the host cycle that brings the cycles owed up to the budget,
+        # once the unit has fallen asleep and the host cycle it fell asleep
+        # in is over.
+        def plan_sleep
+          return if @planned
+
+          @planned = true
+          @slept = 0
+          needed = ((@budget - @owed) * @host_clock_hz) - @phase
+          @wake_at = needed.positive? ? (needed + CLOCK_HZ - 1) / CLOCK_HZ : 1
+        end
+
+        # Turns the host cycles slept into cycles owed, through the phase
+        # accumulator.
+        def owe_slept
+          return unless @planned
+
+          @planned = false
+          phase = @phase + (@slept * CLOCK_HZ)
+          @owed += phase / @host_clock_hz
+          @phase = phase % @host_clock_hz
+          @slept = 0
+        end
       end
     end
   end

data/lib/badline/drives/model8050/fdc_bus.rb

@@ -31,6 +31,10 @@ module Badline
         # last cleared (Model8050::Idle).
         attr_accessor :volatile
 
+        # The bytes of the 6530's RAM read or written since it was last
+        # cleared, a bit for each pair of them (Model8050::Idle).
+        attr_accessor :ram_touched
+
         def initialize(common:, via:, rriot:)
           addressable_at(0, length: 2**16)
           @common = common
@@ -38,6 +42,7 @@ module Badline
           @rriot = rriot
           @data = 0
           @volatile = false
+          @ram_touched = 0
           @common_changes = 0
         end
 
@@ -78,6 +83,7 @@ module Badline
           end
           return peek_via(addr & 0x0f) if addr.anybits?(0x40)
 
+          @ram_touched |= 1 << ((addr & 0x3f) >> 1)
           @rriot.read_ram(addr)
         end
 
@@ -93,6 +99,7 @@ module Badline
           elsif addr.anybits?(0x40)
             @via.poke(0x40 | (addr & 0x0f), value)
           else
+            @ram_touched |= 1 << ((addr & 0x3f) >> 1)
             @rriot.write_ram(addr, value)
           end
         end