badline 0.15.1 → 0.16.1

data/lib/badline/chips/pia/control_lines.rb

@@ -0,0 +1,138 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class PIA
+      # One side's control register, CRA or CRB, its two control lines, CA1
+      # and CA2 or CB1 and CB2, and their interrupt flags.
+      #
+      #   bit 0    C1 interrupt enable
+      #   bit 1    C1 active edge, rising when set
+      #   bit 2    the port (1) or its direction register (0) at the same address
+      #   bits 5-3 C2:
+      #            0e0  input, e the interrupt enable, falling edge
+      #            1e0  input, rising edge
+      #            100  handshake output
+      #            101  pulse output
+      #            110  low output
+      #            111  high output
+      #   bit 6    C2 flag, read only, held clear while C2 is an output
+      #   bit 7    C1 flag, read only
+      #
+      # A flag is set by its line's active edge whether or not its interrupt
+      # is enabled, and both are cleared by a read of the port. In handshake
+      # mode C2 goes low on the strobing access and back high on the next
+      # active C1 edge; in pulse mode it goes low for the cycle after it.
+      # Side A strobes on a read of the port, side B on a write.
+      class ControlLines
+        attr_reader :c1_high, :c2_high
+
+        # The level driven on C2, high while it is an input.
+        attr_reader :c2_output
+
+        def initialize(strobe_on_read:)
+          @strobe_on_read = strobe_on_read
+          @c1_high = @c2_high = true
+          reset!
+        end
+
+        # Every bit clear: C2 an input, both interrupts off and the
+        # direction register selected. The input levels carry over.
+        def reset!
+          @control = 0
+          @c1_flag = @c2_flag = false
+          @handshake_low = false
+          @pulse = 0
+          drive
+        end
+
+        # The control register as read, the flags in bits 7 and 6.
+        def register
+          value = @control
+          value |= 0x80 if @c1_flag
+          value |= 0x40 if @c2_flag
+          value
+        end
+
+        # Writes bits 0-5; the flags can't be written. A new C2 mode starts
+        # with any handshake or pulse over.
+        def register=(value)
+          mode = c2_mode
+          @control = value & 0x3f
+          @c2_flag = false if c2_output?
+          unless c2_mode == mode
+            @handshake_low = false
+            @pulse = 0
+          end
+          drive
+        end
+
+        def port_selected? = @control.anybits?(0x04)
+
+        def irq? = (@c1_flag && @control.anybits?(0x01)) || (@c2_flag && @control & 0x28 == 0x08)
+
+        # Only the pulse output needs the clock.
+        def pulsing? = @pulse.positive?
+
+        def cycle!
+          @pulse -= 1
+          drive if @pulse.zero?
+        end
+
+        # A new C1 level. An active edge sets the flag and ends a handshake.
+        def c1=(high)
+          return if high == @c1_high
+
+          @c1_high = high
+          return unless high == @control.anybits?(0x02)
+
+          @c1_flag = true
+          @handshake_low = false
+          drive
+        end
+
+        # A new C2 level. An active edge sets the flag while C2 is an input.
+        def c2=(high)
+          return if high == @c2_high
+
+          @c2_high = high
+          @c2_flag = true if !c2_output? && high == @control.anybits?(0x10)
+        end
+
+        # A read of the port, which clears both flags.
+        def port_read!
+          @c1_flag = @c2_flag = false
+          strobe if @strobe_on_read
+        end
+
+        def port_written!
+          strobe unless @strobe_on_read
+        end
+
+        private
+
+        def c2_output? = @control.anybits?(0x20)
+
+        def c2_mode = c2_output? ? @control & 0x38 : 0
+
+        def strobe
+          case @control & 0x38
+          when 0x20 then @handshake_low = true
+          when 0x28 then @pulse = 2
+          else return
+          end
+          drive
+        end
+
+        def drive
+          @c2_output = case @control & 0x38
+                       when 0x20 then !@handshake_low
+                       when 0x28 then @pulse.zero?
+                       when 0x30 then false
+                       else true
+                       end
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/pia/keyed_parts.rb

@@ -0,0 +1,56 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class PIA
+      class ControlLines
+        # A side's control register, its lines' levels, its flags and the
+        # handshake or pulse under way, under `prefix`. The level driven on
+        # C2 follows from them on load.
+        module KeyedState
+          def save_fields(out, prefix)
+            out.int("#{prefix}control", @control).bool("#{prefix}c1_high", @c1_high).bool("#{prefix}c2_high", @c2_high)
+            out.bool("#{prefix}c1_flag", @c1_flag).bool("#{prefix}c2_flag", @c2_flag)
+            out.bool("#{prefix}handshake_low", @handshake_low).int("#{prefix}pulse", @pulse)
+          end
+
+          def load_fields(input, prefix)
+            @control = input.masked("#{prefix}control", @control, 0x3f)
+            @c1_high = input.bool("#{prefix}c1_high", @c1_high)
+            @c2_high = input.bool("#{prefix}c2_high", @c2_high)
+            @c1_flag = input.bool("#{prefix}c1_flag", @c1_flag)
+            @c2_flag = input.bool("#{prefix}c2_flag", @c2_flag)
+            @handshake_low = input.bool("#{prefix}handshake_low", @handshake_low)
+            @pulse = input.masked("#{prefix}pulse", @pulse, 0x03)
+            drive
+          end
+        end
+
+        include KeyedState
+      end
+
+      # The PIA's fields in a keyed snapshot module (Snapshot::Keyed): the
+      # output and direction registers, and each side's control lines under
+      # ca. and cb. The peripheral restores its own state.
+      module KeyedState
+        def save_fields(out)
+          out.int("ora", @ora).int("orb", @orb).int("ddra", @ddra).int("ddrb", @ddrb)
+          @ca.save_fields(out, "ca.")
+          @cb.save_fields(out, "cb.")
+          out
+        end
+
+        def load_fields(input)
+          @ora = input.byte("ora", @ora)
+          @orb = input.byte("orb", @orb)
+          @ddra = input.byte("ddra", @ddra)
+          @ddrb = input.byte("ddrb", @ddrb)
+          @ca.load_fields(input, "ca.")
+          @cb.load_fields(input, "cb.")
+        end
+      end
+
+      include KeyedState
+    end
+  end
+end

data/lib/badline/chips/pia.rb

@@ -0,0 +1,138 @@
+# frozen_string_literal: true
+
+require "badline/chips/pia/control_lines"
+require "badline/chips/pia/keyed_parts"
+
+module Badline
+  module Chips
+    # The MOS 6520 PIA (Peripheral Interface Adapter), the PET's two: two
+    # 8-bit ports, A and B, each with a direction register, a 1 making the
+    # pin an output, and a control register for its pair of control lines
+    # (ControlLines). Each side has its own IRQ output, IRQA and IRQB. There
+    # are no timers.
+    #
+    # Four registers repeat on two address lines: port A or DDRA, CRA, port
+    # B or DDRB and CRB, the port or the direction register picked by bit 2
+    # of its control register.
+    #
+    # Port A reads its pins, whatever drives them. Port B reads its output
+    # bits from its output register and its input bits from the pins. An
+    # input pin floats high, and a peripheral pulls lines low through
+    # read_a and read_b, as a VIA's does. The control lines take levels
+    # from outside through ca1= and friends.
+    class PIA
+      attr_reader :peripheral
+
+      def initialize(peripheral: nil)
+        @peripheral = peripheral
+        @ca = ControlLines.new(strobe_on_read: true)
+        @cb = ControlLines.new(strobe_on_read: false)
+        reset!
+      end
+
+      # The RES line clears every register, which leaves every line an
+      # input and releases both IRQs.
+      def reset!
+        @ora = @orb = @ddra = @ddrb = 0x00
+        @ca.reset!
+        @cb.reset!
+      end
+
+      def irqa? = @ca.irq?
+
+      def irqb? = @cb.irq?
+
+      def irq? = @ca.irq? || @cb.irq?
+
+      def cycle!
+        @ca.cycle! if @ca.pulsing?
+        @cb.cycle! if @cb.pulsing?
+      end
+
+      def cra = @ca.register
+
+      def crb = @cb.register
+
+      # Port A as driven by ORA and DDRA, input lines floating high.
+      def port_a_output = driven_lines(@ora, @ddra)
+
+      def port_b_output = driven_lines(@orb, @ddrb)
+
+      def ca1=(high)
+        @ca.c1 = high
+      end
+
+      def ca2=(high)
+        @ca.c2 = high
+      end
+
+      def cb1=(high)
+        @cb.c1 = high
+      end
+
+      def cb2=(high)
+        @cb.c2 = high
+      end
+
+      def ca2_output = @ca.c2_output
+
+      def cb2_output = @cb.c2_output
+
+      def peek(addr)
+        case addr & 0x03
+        when 0x00 then @ca.port_selected? ? read_port_a : @ddra
+        when 0x01 then @ca.register
+        when 0x02 then @cb.port_selected? ? read_port_b : @ddrb
+        else @cb.register
+        end
+      end
+
+      def poke(addr, value)
+        case addr & 0x03
+        when 0x00 then write_port_a(value)
+        when 0x01 then @ca.register = value
+        when 0x02 then write_port_b(value)
+        else @cb.register = value
+        end
+      end
+
+      private
+
+      def driven_lines(register, direction)
+        (register & direction) | (~direction & 0xff)
+      end
+
+      def read_port_a
+        lines = port_a_output
+        lines &= @peripheral.read_a(lines) if @peripheral
+        @ca.port_read!
+        lines
+      end
+
+      def read_port_b
+        lines = port_b_output
+        lines &= @peripheral.read_b(lines) if @peripheral
+        @cb.port_read!
+        (@orb & @ddrb) | (lines & ~@ddrb & 0xff)
+      end
+
+      def write_port_a(value)
+        if @ca.port_selected?
+          @ora = value
+          @ca.port_written!
+        else
+          @ddra = value
+        end
+      end
+
+      def write_port_b(value)
+        if @cb.port_selected?
+          @orb = value
+          @cb.port_written!
+        else
+          @ddrb = value
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/vic/register_log.rb

@@ -43,10 +43,7 @@ module Badline
         # register back at the value it held when the line started.
         def rewind
           @values.length.times { |reg| @values[reg] = @registers[reg] }
-          @seed.each_index do |reg|
-            value = @seed[reg]
-            @values[reg] = value unless value.nil?
-          end
+          @seed.each_with_index { |value, reg| @values[reg] = value unless value.nil? }
           @cursor = 0
           @next_x = @entries.empty? ? Float::INFINITY : @entries[0][0]
         end

data/lib/badline/core.rb

@@ -18,6 +18,8 @@ require "badline/c64/banked_ram"
 require "badline/status"
 require "badline/input"
 require "badline/chips"
+require "badline/chips/pia"
+require "badline/chips/crtc"
 require "badline/drives"
 require "badline/c64/bus"
 require "badline/c64/reu"
@@ -27,6 +29,7 @@ require "badline/snapshot/storage_setup"
 require "badline/machine"
 require "badline/c64"
 require "badline/vic20"
+require "badline/pet"
 require "badline/storage"
 require "badline/sid_tune"
 require "badline/c64/cartridge"

data/lib/badline/drives/ieee_bus.rb

@@ -0,0 +1,74 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    # The IEEE-488 bus between a PET and its drives: eight data lines, DIO1
+    # to DIO8, and the control lines EOI, DAV, NRFD, NDAC and ATN, each open
+    # collector and active low, so a line is low while anything on the bus
+    # pulls it low. The PET is the controller and always on the bus, and
+    # reads back every line it drives.
+    #
+    # The controller pushes the lines it pulls whenever they may have moved
+    # (host_lines=), and the bus holds them for the drives, which take them
+    # a host cycle late. Each drive on the bus answers the lines it pulls
+    # (ieee_low_lines) while ATN is or isn't low, from its own outputs, which
+    # hold still while it sleeps. With no drive on the bus nobody answers a
+    # handshake, and the KERNAL reports DEVICE NOT PRESENT for every device
+    # the traps don't serve.
+    class IEEEBus
+      # The lines as bits, the data lines in the low byte, DIO1 in bit 0.
+      DIO = 0x00ff
+      EOI = 0x0100
+      DAV = 0x0200
+      NRFD = 0x0400
+      NDAC = 0x0800
+      ATN = 0x1000
+
+      # The lines the controller last pushed.
+      attr_reader :host_lines
+
+      attr_reader :drives
+
+      def initialize
+        @drives = []
+        @host_lines = 0
+      end
+
+      # The controller pushes the lines it pulls, and the drives look at
+      # them again.
+      def host_lines=(lines)
+        @host_lines = lines
+        drives = @drives
+        i = 0
+        while i < drives.length
+          drives[i].host_written!
+          i += 1
+        end
+      end
+
+      def attach(drive)
+        @drives << drive unless @drives.include?(drive)
+      end
+
+      def detach(drive)
+        @drives.delete(drive)
+      end
+
+      # The lines low on the bus while the controller pulls the lines in
+      # +controller+ low.
+      def low_lines(controller)
+        low = controller
+        drives = @drives
+        return low if drives.empty?
+
+        atn = controller.anybits?(ATN)
+        i = 0
+        while i < drives.length
+          low |= drives[i].ieee_low_lines(atn)
+          i += 1
+        end
+        low
+      end
+    end
+  end
+end

data/lib/badline/drives/model1551/cable.rb

@@ -10,7 +10,8 @@ module Badline
       # - the eight data lines join the two port As;
       # - the drive's STATUS0 and STATUS1 (PC0-1) reach the computer's PB0-1;
       # - the drive's ACK (PC3) reaches the computer's PC7;
-      # - the computer's DAV (PC6) reaches the drive's PC7.
+      # - the computer's DAV (PC6) reaches the drive's PC7;
+      # - the drive's DEV (PC2) picks the interface's address (Model1551).
       #
       # The drive pulls every line up, so a line neither side drives low
       # reads 1. The computer's other port B and C pins read 0.
@@ -23,13 +24,14 @@ module Badline
       # wakes a drive asleep in its idle loop (atn_moved?).
       class Cable
         STATUS = 0x03
+        DEV = 0x04
         ACK = 0x08
         DAV = 0x40
 
         attr_reader :host, :drive
 
         # Plugs the cable into +host+, the computer's Chips::TIA, and
-        # +drive+, the drive's (Model1551::TIA#chip), for +unit+, the drive.
+        # +drive+, the drive's (Model1551::TIA), for +unit+, the drive.
         def initialize(host, drive, unit)
           @host = host
           @drive = drive
@@ -93,6 +95,7 @@ module Badline
           drive_inputs = drive.inputs
           drive_inputs[0] = @data & drive_data
           drive_inputs[2] = (drive_inputs[2] & 0x7f) | (@dav << 1)
+          @unit.dev_line(drive_lines.anybits?(DEV))
           return if @moved || (host_data == @data && (host_lines & DAV) == @dav)
 
           @moved = true

data/lib/badline/drives/model1551/tia.rb

@@ -4,8 +4,7 @@ module Badline
   module Drives
     class Model1551
       # The drive's 6523 TIA at $4000-$7FFF, its eight registers mirrored
-      # (zimmers.net's 1551 memory map, schematic 251860), a Chips::TIA
-      # with what the drive's side wires to it:
+      # (zimmers.net's 1551 memory map, schematic 251860):
       #
       # - Port A carries the cable's eight data lines, pulled up.
       # - Port B reads the GCR byte the gate array latched at BYTE READY
@@ -19,72 +18,52 @@ module Badline
       # pulled up, so an input nothing drives reads 1.
       #
       # Any access to the TIA clears BYTE LATCHED.
-      class TIA
+      class TIA < Chips::TIA
         DAV = 0x80
         SYNC = 0x40
         JUMPER = 0x20
         MODE = 0x10
 
-        # The chip, whose inputs the drive's side sets before each read.
-        attr_reader :chip
-
         def initialize(mechanism, device:)
           @mechanism = mechanism
           @jumper = device == 9 ? JUMPER : 0
-          @chip = Chips::TIA.new
-          inputs = @chip.inputs
-          inputs[0] = 0xff
-          inputs[1] = 0xff
-          inputs[2] = 0xff
           mechanism.tia = self
-          mode_written
+          super()
+          @inputs[0] = 0xff
+          @inputs[1] = 0xff
+          @inputs[2] = 0xff
         end
 
-        def ports = @chip.ports
-
-        def directions = @chip.directions
-
-        def inputs = @chip.inputs
-
         def reset!
-          @chip.reset!
+          super
           mode_written
         end
 
         def peek(addr)
           mechanism = @mechanism
           mechanism.release_byte_latch
-          chip = @chip
-          inputs = chip.inputs
           case addr & 0x07
-          when 1 then inputs[1] = mechanism.latched_byte
-          when 2 then inputs[2] = (inputs[2] & DAV) | (mechanism.sync? ? 0 : SYNC) | @jumper | 0x1f
+          when 1 then @inputs[1] = mechanism.latched_byte
+          when 2 then @inputs[2] = (@inputs[2] & DAV) | (mechanism.sync? ? 0 : SYNC) | @jumper | 0x1f
           end
-          chip.peek(addr)
+          super
         end
 
         def poke(addr, value)
           @mechanism.release_byte_latch
-          @chip.poke(addr, value)
+          super
           register = addr & 0x07
           mode_written if [2, 5].include?(register)
         end
 
         # What port B drives onto the head's write shift register.
-        def port_b_output = @chip.output(1)
-
-        # The chip's registers, in a keyed snapshot module (BL-D8-TIA).
-        def save_fields(out) = @chip.save_fields(out)
-
-        def load_fields(input)
-          @chip.load_fields(input)
-        end
+        def port_b_output = output(1)
 
         private
 
         # MODE selects reading while high, as the 1541's CB2 does.
         def mode_written
-          @mechanism.cb2_written(@chip.output(2).anybits?(MODE))
+          @mechanism.cb2_written(output(2).anybits?(MODE))
         end
       end
     end

data/lib/badline/drives/model1551.rb

@@ -26,7 +26,10 @@ module Badline
     # The drive comes with its interface for the computer's expansion port,
     # a second 6523 (#host_tia), which the cable joins to the drive's
     # (Cable). The computer puts it at $FEE0 for device 8 and at $FEC0 for
-    # device 9.
+    # device 9, as the drive's DEV line (PC2) says: high for device 8 and
+    # low for device 9. The DOS sets DEV from the jumper at reset, and again
+    # when a command renumbers the drive. The device number follows each
+    # change on the line (#device).
     #
     # A 555 timer pulls IRQ low for about 7 µs every 8.3 ms, its R1 120K,
     # R2 100R and C1 0.1 µF, which runs the DOS's job loop. Nothing
@@ -101,10 +104,29 @@ module Badline
         @irq_timer = IRQ_PERIOD
         init_idle(debug)
         @pass_counter = PASS_COUNTER
-        @cable = Cable.new(@host_tia, @tia.chip, self)
+        @dev_high = true
+        @on_renumber = nil
+        @cable = Cable.new(@host_tia, @tia, self)
         @serial_port = @cable
       end
 
+      # Calls the block with the old device number each time the DEV line
+      # moves the drive to the other one.
+      def on_renumber(&block)
+        @on_renumber = block
+      end
+
+      # The cable's DEV line, high or not. A change moves the drive to
+      # device 8 while it's high, and to device 9 while it's low.
+      def dev_line(high)
+        return if high == @dev_high
+
+        @dev_high = high
+        old = @device
+        @device = high ? 8 : 9
+        @on_renumber&.call(old) unless @device == old
+      end
+
       # Puts in a Disk from the .d64 or .g64 image at +path+, write-protected
       # with `read_only`.
       def insert_image(path, read_only: false)
@@ -148,8 +170,8 @@ module Badline
       end
 
       def idle_state
-        chip = @tia.chip
-        [*@cpu.counting_state, @bus.data, *@mechanism.idle_state, *chip.ports, *chip.directions, *chip.inputs,
+        tia = @tia
+        [*@cpu.counting_state, @bus.data, *@mechanism.idle_state, *tia.ports, *tia.directions, *tia.inputs,
          @port.ddr, @port.data]
       end