badline 0.15.1 → 0.16.1

data/lib/badline/snapshot/vice/pet_mem.rb

@@ -0,0 +1,93 @@
+# frozen_string_literal: true
+
+module Badline
+  module Snapshot
+    module Vice
+      module PET
+        # PETMEM 1.3: the board, the RAM below $8000 in K and the 8096's
+        # control register at $FFF0, then the RAM, the screen RAM, 1K or 2K
+        # as the board has, or on the 8296 its 32K from $8000, an 8096's or
+        # 8296's 64K board, and 24 bytes of xpet's own settings, which name
+        # the 2001.
+        #
+        # The board is 0 for the discrete video, 1 for a 40-column CRTC, 2
+        # for an 80-column one, 3 for the SuperPET, 4 for the 8096 and 5 for
+        # the 8296. xpet's ROMs aren't in the snapshot.
+        module PETMem
+          NAME = "PETMEM"
+          MAJOR = 1
+          MINOR = 3
+          DISCRETE = 0
+          CRTC40 = 1
+          CRTC80 = 2
+          SUPERPET = 3
+          CBM8096 = 4
+          CBM8296 = 5
+          # The byte after the header's control register, as xpet writes it.
+          HEADER_END = 0x05
+          # xpet's settings at the end, but for the second byte, which is
+          # SETTINGS_2001 on a 2001.
+          SETTINGS = [0x00, 0x00, 0x00, 0x00, 0xd6, 0x01, 0x00, 0x20, 0x00, 0x04, 0x00, 0x40, 0x00, 0x00, 0x00,
+                      0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x02, 0x00, 0x00].freeze
+          SETTINGS_2001 = 0x03
+          EXPANSION = 0x10000
+
+          module_function
+
+          def reads?(section) = section.major == MAJOR && section.minor == MINOR
+
+          def board(model)
+            return CBM8296 if model.cbm8296?
+            return CBM8096 if model.expansion
+
+            case model.video
+            when :crtc40 then CRTC40
+            when :crtc80 then CRTC80
+            else DISCRETE
+            end
+          end
+
+          def export(machine)
+            bus = machine.bus
+            expansion = bus.expansion
+            fields = FieldWriter.new.byte(board(machine.model)).byte(0).byte(machine.ram_kb)
+            fields.byte(expansion ? expansion.control : 0).byte(HEADER_END)
+            fields.bytes(machine.ram.snapshot).bytes(bus.screen.cells)
+            fields.bytes(expansion.cells) if expansion
+            settings = SETTINGS.dup
+            settings[1] = SETTINGS_2001 if machine.model.basic1?
+            fields.bytes(settings).section(NAME, MAJOR, MINOR)
+          end
+
+          # The board's number in the header.
+          def board_of(section) = FieldReader.new(section).byte
+
+          def ram_kb(section) = FieldReader.new(section).skip(2).byte
+
+          # Whether xpet's settings at the end name a 2001.
+          def pet2001?(section)
+            data = section.data
+            data.bytesize >= SETTINGS.length && data.getbyte(data.bytesize - SETTINGS.length + 1).to_i.anybits?(0x01)
+          end
+
+          # The RAM, the screen RAM and an 8096's or 8296's board and control
+          # register
+          # by their BL-RAM keys, in a keyed module's writer, for a machine
+          # with `screen_bytes` of screen RAM.
+          def import(section, out, screen_bytes)
+            fields = FieldReader.new(section)
+            board = fields.byte
+            fields.skip(1)
+            ram_kb = fields.byte
+            control = fields.byte
+            fields.skip(1)
+            out.bytes("ram", fields.string(ram_kb * 1024)).bytes("screen", fields.string(screen_bytes))
+            return unless [CBM8096, CBM8296].include?(board)
+
+            out.int("expansion.control", control).bytes("expansion.ram", fields.string(EXPANSION))
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/snapshot/vice/pet_pias.rb

@@ -0,0 +1,56 @@
+# frozen_string_literal: true
+
+module Badline
+  module Snapshot
+    module Vice
+      module PET
+        # PIA1 and PIA2 1.0: port A's output and direction registers and
+        # its control register as read, with the CA1 and CA2 flags in bits 7
+        # and 6, the same for port B, and the levels on CA2 and CB2 in bits
+        # 7 and 6 of the last byte, high while a line is an input.
+        #
+        # Read: each side's flags come from its control register, and a
+        # handshake under way from the level its C2 output is at. The levels
+        # outside on CA1 and CB1 aren't saved: they stay as the machine has
+        # them, with PIA 1's CB1 on the vertical drive line.
+        module PIAs
+          NAMES = %w[PIA1 PIA2].freeze
+          MAJOR = 1
+          MINOR = 0
+          CA2_HIGH = 0x80
+          CB2_HIGH = 0x40
+          HANDSHAKE = 0x20
+
+          module_function
+
+          def reads?(section) = section.major == MAJOR && section.minor == MINOR
+
+          # The PIA's module, from its BL-PIA1 or BL-PIA2 fields in `input`.
+          def export(name, pia, input)
+            fields = FieldWriter.new.byte(input.int("ora", 0)).byte(input.int("ddra", 0)).byte(pia.cra)
+            fields.byte(input.int("orb", 0)).byte(input.int("ddrb", 0)).byte(pia.crb)
+            fields.byte((pia.ca2_output ? CA2_HIGH : 0) | (pia.cb2_output ? CB2_HIGH : 0))
+            fields.section(name, MAJOR, MINOR)
+          end
+
+          # The registers and the control lines by their BL-PIA keys, in a
+          # keyed module's writer.
+          def import(section, out)
+            ora, ddra, cra, orb, ddrb, crb, lines = FieldReader.new(section).bytes(7)
+            out.int("ora", ora).int("ddra", ddra).int("orb", orb).int("ddrb", ddrb)
+            control_lines(out, "ca.", cra, lines.anybits?(CA2_HIGH))
+            control_lines(out, "cb.", crb, lines.anybits?(CB2_HIGH))
+          end
+
+          def control_lines(out, prefix, register, c2_high)
+            control = register & 0x3f
+            out.int("#{prefix}control", control).bool("#{prefix}c1_flag", register.anybits?(0x80))
+            out.bool("#{prefix}c2_flag", register.anybits?(0x40)).int("#{prefix}pulse", 0)
+            out.bool("#{prefix}handshake_low", control & 0x38 == HANDSHAKE && !c2_high)
+            out.bool("#{prefix}c2_high", c2_high) if control.nobits?(0x20)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/snapshot/vice/pet_restore.rb

@@ -0,0 +1,150 @@
+# frozen_string_literal: true
+
+module Badline
+  module Snapshot
+    module Vice
+      module PET
+        # Restores a PET from a snapshot xpet wrote. The modules badline
+        # reads become the PET's own keyed modules (Keyed), which it loads
+        # as it loads its own snapshot. Whatever they don't set stays as the
+        # machine has it at power-on, and the datasettes' tapes and the
+        # disk device 8 serves stay as they are.
+        module Restore
+          # MAINCPU and PETMEM hold the machine itself, so a version badline
+          # doesn't read fails the restore. The others are left out and
+          # reported.
+          READ = [MainCPU::NAME, PETMem::NAME, CRTC::NAME, "PIA1", "PIA2", VIA::NAME].freeze
+          # The host's media, which a restore keeps.
+          KEPT = %w[BL-TAPE1 BL-TAPE2 BL-TRAPDOS].freeze
+
+          module_function
+
+          # Applies the modules badline reads to `computer`, and returns a
+          # Report. The snapshot goes into a new machine first, so one that
+          # fails leaves `computer` as it was, and one of a machine built
+          # another way fails too.
+          def import(container, computer)
+            unless computer.family == :pet
+              raise FormatError, "the snapshot is of a PET, not a #{Image::FAMILIES.fetch(computer.family.to_s)}"
+            end
+
+            setup = PET.setup(container)
+            ours = PETSetup.of(computer)
+            raise FormatError, "the snapshot is of a #{setup}, not a #{ours}" unless setup == ours
+
+            apply(container, setup.build)
+            computer.power_cycle!
+            report = apply(container, computer)
+            kept = computer.mounted? ? ["the disk mounted in device 8 stays mounted"] : []
+            Report.new(applied: report.applied, ignored: report.ignored + kept)
+          end
+
+          # Applies the modules badline reads to `computer`, a machine built
+          # as the snapshot's was, and returns the Report.
+          def apply(container, computer)
+            applied = []
+            ignored = []
+            sections = []
+            READ.each do |name|
+              section = container[name]
+              next if section.nil?
+
+              if reads?(section)
+                applied << name
+              else
+                raise FormatError, "#{section}: badline doesn't read this version" if required?(name)
+
+                ignored << "#{section}: badline doesn't read this version, left out"
+              end
+            end
+            computer.save_modules.each { |section| sections << section if KEPT.include?(section.name) }
+            computer.load_modules(Keyed::Modules.new(modules(container, computer, applied) + sections))
+            Report.new(applied:, ignored: ignored + left_out(container))
+          end
+
+          def required?(name) = [MainCPU::NAME, PETMem::NAME].include?(name)
+
+          def reads?(section)
+            case section.name
+            when MainCPU::NAME then MainCPU.reads?(section)
+            when PETMem::NAME then PETMem.reads?(section)
+            when CRTC::NAME then CRTC.reads?(section)
+            when VIA::NAME then VIA.reads?(section)
+            else PIAs.reads?(section)
+            end
+          end
+
+          # The PET's keyed modules from the ones `applied` names.
+          def modules(container, computer, applied)
+            model = computer.model
+            crtc = applied.include?(CRTC::NAME) ? container[CRTC::NAME] : nil
+            video = video(crtc, computer)
+            drive = driving?(crtc, video, model)
+            sections = [Keyed.section("BL-MACHINE") { |out| machine(out, container, computer, drive) },
+                        Keyed.section("BL-RAM") do |out|
+                          PETMem.import(container[PETMem::NAME], out, model.screen_bytes)
+                        end]
+            sections << Keyed.section("BL-CPU") { |out| MainCPU.import(container[MainCPU::NAME], out) }
+            %w[PIA1 PIA2].each do |name|
+              next unless applied.include?(name)
+
+              sections << Keyed.section("BL-#{name}") do |out|
+                PIAs.import(container[name], out)
+                out.bool("cb.c1_high", drive) if name == "PIA1"
+              end
+            end
+            if applied.include?(VIA::NAME)
+              sections << Keyed.section("BL-VIA") { |out| VIA.import(container[VIA::NAME], out) }
+            end
+            sections + video
+          end
+
+          def machine(out, container, computer, drive)
+            out.text("family", "pet")
+            PETSetup.of(computer).write_fields(out)
+            out.int("cycles", FieldReader.new(container[MainCPU::NAME]).qword).bool("vertical_drive", drive)
+          end
+
+          # The vertical drive line, low in the CRTC's vertical sync or past
+          # the discrete video's rows, as the video's module, `video`, has it.
+          def driving?(crtc, video, model)
+            return true if crtc.nil?
+
+            fields = Keyed::Reader.parse(video.first)
+            if model.video == :discrete
+              fields.int("line", 0) < Badline::PET::DiscreteVideo::DISPLAYED_LINES
+            else
+              fields.int("vsync_lines", 0).zero?
+            end
+          end
+
+          # The discrete video's module, or the CRTC's, run on from xpet's
+          # counters to where badline's drops the vertical drive line on the
+          # cycle xpet's does (CRTC::CRTC_LEAD). The CRTC runs on from the
+          # start of the beam's line, or for a beam in the first cycles of
+          # its line, a frame less those cycles on, which lands on the same
+          # counters while the registers stood through the frame as they
+          # stand.
+          def video(crtc, computer)
+            return [] if crtc.nil?
+
+            model = computer.model
+            return [Keyed.section("BL-VIDEO") { |out| CRTC.import_discrete(crtc, out) }] if model.video == :discrete
+
+            counters = Keyed.section("BL-CRTC") do |out|
+              CRTC.import(crtc, out, CRTC.columns(model), CRTC.attributes(model))
+            end
+            cycles = (CRTC::CRTC_LEAD + CRTC.column_of(crtc)) % CRTC.frame_cycles(CRTC.registers(crtc))
+            fields = CRTC.run_on(computer, Keyed::Reader.parse(counters), cycles)
+            [Keyed.section("BL-CRTC") { |out| CRTC.copy(fields, out) }]
+          end
+
+          def left_out(container)
+            container.sections.reject { |section| READ.include?(section.name) }
+                     .map { |section| "#{section}: badline doesn't read this module, left out" }
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/snapshot/vice/pet_via.rb

@@ -0,0 +1,164 @@
+# frozen_string_literal: true
+
+module Badline
+  module Snapshot
+    module Vice
+      module PET
+        # VIA 2.2, the 6522 at $E840: port A's and port B's output and
+        # direction registers, timer 1's latch and counter, timer 2's low
+        # and high latch, the value it was last loaded with and its counter,
+        # which timers will set their interrupt flag (timer 1 in bit 7,
+        # timer 2 in bit 6 while it counts cycles), the shift register, the
+        # ACR, the PCR, the interrupt flags and enable mask, timer 1's level
+        # on PB7 in bit 7, the shift register's clock ticks into its byte,
+        # CA2's level in bit 7, and whether timer 2's next underflow sets
+        # its flag. xpet saves each counter as a read on the next cycle
+        # finds it, where badline's holds it before that cycle counts.
+        #
+        # Written: timer 2's high latch and the value it was loaded with,
+        # which badline doesn't keep, as xpet has them before a program
+        # loads it, or while the shift register clocks off it, as its low
+        # byte reloads. Free-running, the shift register's ticks are only
+        # whether CB1 is low.
+        #
+        # Read: the registers and both timers with their latches, as they
+        # count from the next cycle, and the shift register where its clock
+        # ticks are. A load or reload under way, a shift clock tick due off
+        # timer 2 and the latched ports start afresh, and CB2's level
+        # follows from the PCR.
+        module VIA
+          NAME = "VIA"
+          MAJOR = 2
+          MINOR = 2
+          T1_ARMED = 0x80
+          T2_TIMED = 0x40
+          LEVELS = 0x60
+          # The shift register's clock ticks a byte takes, which an idle
+          # register's count stands at.
+          TICKS = 16
+          SIZE = 28
+          # The shift register's modes that clock off timer 2.
+          T2_SHIFTS = [1, 4, 5].freeze
+
+          module_function
+
+          def reads?(section) = section.major == MAJOR && section.minor == MINOR
+
+          # The VIA's module, from its BL-VIA fields in `input`.
+          def export(input)
+            fields = FieldWriter.new
+            %w[ora ddra orb ddrb].each { |key| fields.byte(input.int(key, 0)) }
+            fields.word(input.int("t1.latch", 0xffff)).word(timer1(input))
+            t2 = timer2(input)
+            latch_low = input.int("t2.latch_low", 0xff)
+            fields.byte(latch_low).byte(0xff).word(shifting?(input) ? (t2 & 0xff00) | latch_low : 0xffff).word(t2)
+            fields.byte(armed(input)).byte(input.int("sr.data", 0))
+            fields.byte(input.int("acr", 0)).byte(input.int("pcr", 0))
+            fields.byte(input.int("ifr.flags", 0)).byte(input.int("ifr.enable", 0))
+            fields.byte(input.bool("t1.pb7", true) ? 0x80 : 0)
+            fields.byte(ticks(input))
+            fields.byte(LEVELS | (input.bool("ca.c2_output", true) ? 0x80 : 0)).zeros(2)
+            fields.byte(input.bool("t2.armed", false) ? 1 : 0).zeros(2).section(NAME, MAJOR, MINOR)
+          end
+
+          # Timer 1's counter as a read on the next cycle finds it: as it
+          # stands while a load holds it, the latch while it reloads, and one
+          # less otherwise.
+          def timer1(input)
+            counter = input.int("t1.counter", 0xffff)
+            return counter if input.bool("t1.hold", false)
+            return input.int("t1.latch", 0xffff) if input.bool("t1.reload", false)
+
+            (counter - 1) & 0xffff
+          end
+
+          # Timer 2's counter as a read on the next cycle finds it: as it
+          # stands while it counts pulses or a load holds it, and one less
+          # otherwise.
+          def timer2(input)
+            counter = input.int("t2.counter", 0xffff)
+            return counter if input.bool("t2.hold", false) || input.bool("t2.counting_pulses", false)
+
+            (counter - 1) & 0xffff
+          end
+
+          # The shift register's clock ticks into its byte: two a bit, the
+          # first one dropping CB1, TICKS when idle. Free-running, its bits
+          # never run out, and only whether CB1 is low counts.
+          def ticks(input)
+            bits = input.int("sr.bits", 0)
+            return TICKS if bits.zero?
+
+            low = input.bool("sr.clock", true) ? 0 : 1
+            return low if input.int("sr.mode", 0) == 4
+
+            ((8 - bits) * 2) + low
+          end
+
+          # The shift register from its mode, data and the ticks into its
+          # byte (#ticks), with the last bit put out on CB2.
+          def shift_register(out, mode, data, ticks)
+            ticks = [ticks, TICKS].min
+            bits = ticks == TICKS ? 0 : 8 - (ticks / 2)
+            bits = 8 if mode == 4 && ticks < TICKS
+            out.int("sr.mode", mode).int("sr.data", data).int("sr.bits", bits).int("sr.delay", 0)
+            out.bool("sr.clock", ticks.even?).bool("sr.cb2", ticks.zero? || data.anybits?(0x01))
+          end
+
+          # Whether the shift register clocks off timer 2.
+          def shifting?(input) = T2_SHIFTS.include?((input.int("acr", 0) >> 2) & 0x07)
+
+          # Timer 2 sets its flag, or clocks the shift register, while it
+          # counts cycles.
+          def armed(input)
+            pulses = input.bool("t2.count_pulses", false)
+            timed = !pulses && (input.bool("t2.armed", false) || shifting?(input))
+            (input.bool("t1.armed", false) ? T1_ARMED : 0) | (timed ? T2_TIMED : 0)
+          end
+
+          # The registers, the timers and the control lines by their BL-VIA
+          # keys, in a keyed module's writer.
+          def import(section, out)
+            bytes = FieldReader.new(section).bytes(SIZE)
+            acr = bytes[0x10]
+            pcr = bytes[0x11]
+            out.int("ora", bytes[0]).int("ddra", bytes[1]).int("orb", bytes[2]).int("ddrb", bytes[3])
+            out.int("acr", acr).int("pcr", pcr)
+            timers(out, bytes, acr)
+            shift_register(out, (acr >> 2) & 0x07, bytes[0x0f], bytes[0x15])
+            out.int("ifr.flags", bytes[0x12] & 0x7f).int("ifr.enable", bytes[0x13] & 0x7f)
+            control_lines(out, "ca.", pcr & 0x0f, bytes[0x16].anybits?(0x80))
+            control_lines(out, "cb.", pcr >> 4, true)
+          end
+
+          def timers(out, bytes, acr)
+            out.int("t1.latch", bytes[4] | (bytes[5] << 8)).int("t1.counter",
+                                                                ((bytes[6] | (bytes[7] << 8)) + 1) & 0xffff)
+            out.bool("t1.hold", false)
+            out.bool("t1.reload", false).bool("t1.armed", bytes[0x0e].anybits?(T1_ARMED))
+            out.bool("t1.pb7", bytes[0x14].anybits?(0x80))
+            pulses = acr.anybits?(0x20)
+            t2 = bytes[0x0c] | (bytes[0x0d] << 8)
+            out.int("t2.latch_low", bytes[8]).int("t2.counter", pulses ? t2 : (t2 + 1) & 0xffff).bool("t2.hold", false)
+            out.bool("t2.low_reload", false).bool("t2.low_underflowed", false)
+            out.bool("t2.armed", bytes[0x19].anybits?(0x01))
+            out.bool("t2.count_pulses", pulses).bool("t2.counting_pulses", pulses)
+          end
+
+          # A handshake under way holds C2 low.
+          def control_lines(out, prefix, control, c2_high)
+            mode = control >> 1
+            handshake_low = mode == 4 && !c2_high
+            output = case mode
+                     when 4 then !handshake_low
+                     when 6 then false
+                     else true
+                     end
+            out.int("#{prefix}control", control).bool("#{prefix}handshake_low", handshake_low)
+            out.int("#{prefix}pulse", 0).bool("#{prefix}c2_output", output)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/snapshot/vice.rb

@@ -13,6 +13,7 @@ require "badline/snapshot/vice/peripherals"
 require "badline/snapshot/vice/vicii"
 require "badline/snapshot/vice/vicii_import"
 require "badline/snapshot/vice/restore"
+require "badline/snapshot/vice/pet"
 
 module Badline
   module Snapshot

data/lib/badline/snapshot.rb

@@ -35,9 +35,9 @@ module Badline
     # The machine's snapshot file. Saving first runs the machine on to the
     # end of the instruction its CPU is in, and of an REU transfer under
     # way (Machine::Settling), so a save advances it by a few cycles, and a
-    # second save straight after runs none. A VIC-20's, a C128's or a
-    # Plus/4's snapshot is in a container named as xvic, x128 or xplus4
-    # names its machine.
+    # second save straight after runs none. A VIC-20's, a C128's, a
+    # Plus/4's or a PET's snapshot is in a container named as xvic, x128,
+    # xplus4 or xpet names its machine.
     def dump(computer) = Image.of(computer).to_s
 
     def read(path) = Image.new(Container.parse(File.binread(path)), name: File.basename(path))
@@ -51,8 +51,8 @@ module Badline
     # snapshot that fails leaves the machine as it was.
     def restore(computer, path, &) = read(path).restore(computer, &)
 
-    # A machine's snapshots, as .vsf files and in memory. C64, Vic20, C128
-    # and Plus4 each include it.
+    # A machine's snapshots, as .vsf files and in memory. C64, Vic20, C128,
+    # Plus4 and PET each include it.
     module Files
       def save_snapshot(path) = Snapshot.save(self, path)
 
@@ -95,4 +95,8 @@ module Badline
   class Plus4
     include Snapshot::Files
   end
+
+  class PET
+    include Snapshot::Files
+  end
 end

data/lib/badline/storage/d80_image.rb

@@ -0,0 +1,48 @@
+# frozen_string_literal: true
+
+module Badline
+  module Storage
+    # An 8050 disk: 77 tracks on one side, in four speed zones.
+    class D80Image < DiskImage
+      ERROR_TABLES = { 535_331 => 2083 }.freeze
+
+      # The last track of each zone but the innermost, from the outermost
+      # in: tracks 1-39, 40-53 and 54-64, and the last zone from 65 on.
+      ZONE_LAST_TRACKS = [39, 53, 64].freeze
+
+      # The sectors a track holds in each zone, from the outermost in.
+      ZONE_SECTORS = [29, 27, 25, 23].freeze
+
+      # The tracks a side holds.
+      SIDE_TRACKS = 77
+
+      def sectors_in(track)
+        zone = ZONE_LAST_TRACKS.count { |last| track > last }
+        ZONE_SECTORS[zone]
+      end
+
+      private
+
+      def error_tables = ERROR_TABLES
+
+      # The header block holds the disk name at $06 and the ID at $18,
+      # after the link to the BAM's first block and the format, "C".
+      def header_name = 0x06
+      def directory_track = 39
+      def directory_sector = 1
+      def directory_interleave = 3
+      def interleave = 6
+
+      # Only the directory track is kept from files. The BAM's blocks on
+      # track 38 are marked in use, and the rest of that track holds files.
+      def reserved_tracks = [39]
+
+      # The BAM takes blocks 0, 3, 6 and 9 of track 38 as it needs them,
+      # each covering 50 tracks with a free count and a four-byte bitmap
+      # each from offset 6.
+      def bam_tracks = 1..SIDE_TRACKS
+      def bam_count(track) = [38, 3 * ((track - 1) / 50), 6 + (5 * ((track - 1) % 50))]
+      def bam_bitmap(track) = [38, 3 * ((track - 1) / 50), 7 + (5 * ((track - 1) % 50))]
+    end
+  end
+end

data/lib/badline/storage/d82_image.rb

@@ -0,0 +1,21 @@
+# frozen_string_literal: true
+
+module Badline
+  module Storage
+    # An 8250 disk: an 8050's 77 tracks on each side, tracks 78-154 on the
+    # second, one directory and one BAM for both.
+    class D82Image < D80Image
+      ERROR_TABLES = { 1_070_662 => 4166 }.freeze
+
+      def sectors_in(track)
+        track > SIDE_TRACKS ? super(track - SIDE_TRACKS) : super
+      end
+
+      private
+
+      def error_tables = ERROR_TABLES
+
+      def bam_tracks = 1..(2 * SIDE_TRACKS)
+    end
+  end
+end

data/lib/badline/storage/tap.rb

@@ -3,7 +3,7 @@
 module Badline
   module Storage
     # Raw datasette pulse stream. The header holds the signature, the
-    # version at $0c, the platform at $0d (0 C64, 1 VIC-20, 2 C16) and the
+    # version at $0c, the platform at $0d (0 C64, 1 VIC-20, 2 C16, 3 PET) and the
     # data size at $10; the data runs from $14, every byte the time to the
     # next falling edge on the tape read line, in units of 8 cycles. A
     # version 2 tape, the C16's and the Plus/4's, times half waves instead,
@@ -16,18 +16,31 @@ module Badline
       HEADER_SIZE = 0x14
       OVERFLOW = 0x100 * 8
 
+      # The platform byte of a PET tape, a version 1 tape timed in PET
+      # cycles.
+      PET_PLATFORM = 3
+
       # The file it was read from, expanded, and the file's bytes.
       attr_reader :version, :platform, :path, :bytes
 
       # A blank tape for `platform` at `path`, written to the host file: a
-      # version 1 tape for the C64 (0) or the VIC-20 (1), and a version 2
-      # C16 tape for the 264 series (2).
+      # version 1 tape for the C64 (0), the VIC-20 (1) or the PET (3), and
+      # a version 2 C16 tape for the 264 series (2).
       def self.create(path, platform:)
         header = platform == 2 ? C16_SIGNATURE + [2] : SIGNATURE + [1]
         File.binwrite(path, (header + [platform, 0, 0, 0, 0, 0, 0]).pack("C*"))
         new(path)
       end
 
+      # The platform byte of the tape at `path`, or nil when it isn't a
+      # TAP file, read from its header alone.
+      def self.platform_of(path)
+        header = File.binread(path, HEADER_SIZE)&.bytes || []
+        return unless [SIGNATURE, C16_SIGNATURE].include?(header[0, SIGNATURE.length]) && header.length > 0x0d
+
+        header[0x0d]
+      end
+
       # `bytes` stands in for the host file's contents, as a snapshot
       # restores the tape it holds.
       def initialize(path, bytes: nil)

data/lib/badline/storage.rb

@@ -7,6 +7,8 @@ require "badline/storage/disk_image"
 require "badline/storage/d64_image"
 require "badline/storage/d71_image"
 require "badline/storage/d81_image"
+require "badline/storage/d80_image"
+require "badline/storage/d82_image"
 require "badline/storage/g64_image"
 require "badline/storage/t64"
 require "badline/storage/tap"

data/lib/badline/support/pet_checkpoint.rb

@@ -0,0 +1,38 @@
+# frozen_string_literal: true
+
+module Badline
+  module Support
+    # A Checkpoint of a PET: its CPU, the RAM below $8000, the screen RAM,
+    # the picture the video paints, both PIAs, the VIA, the CRTC's
+    # registers and counters, and the 8096's control register and 64K
+    # board, or nothing on another model.
+    module PETCheckpoint
+      COMPONENTS = %w[cpu ram screen display pia1 pia2 via crtc expansion].freeze
+
+      def self.take(machine)
+        ram = machine.ram
+        Checkpoint.new(machine.cycles, [
+                         Checkpoint.fnv1a(Checkpoint.cpu_state(machine.cpu)),
+                         Checkpoint.fnv1a(Checkpoint.ram(ram, ram.length)),
+                         Checkpoint.fnv1a(machine.bus.screen.cells),
+                         Checkpoint.fnv1a(machine.video.display),
+                         Checkpoint.fnv1a(pia_state(machine.pia1)),
+                         Checkpoint.fnv1a(pia_state(machine.pia2)),
+                         Checkpoint.fnv1a(Vic20Checkpoint.via_state(machine.via)),
+                         Checkpoint.fnv1a(crtc_state(machine.crtc)),
+                         Checkpoint.fnv1a(expansion_state(machine.bus.expansion))
+                       ], COMPONENTS)
+      end
+
+      def self.parse(line) = Checkpoint.parse(line, COMPONENTS)
+
+      def self.pia_state(pia) = [pia.port_a_output, pia.port_b_output, pia.cra, pia.crb]
+
+      def self.crtc_state(crtc) = crtc.registers + [crtc.column, crtc.line, crtc.row]
+
+      def self.expansion_state(expansion)
+        expansion ? [expansion.control, *expansion.cells] : []
+      end
+    end
+  end
+end