badline 0.15.0 → 0.16.0

data/lib/badline/drives/engine/idle.rb

@@ -47,6 +47,14 @@ module Badline
       #
       # The timer's interrupts come round too, and once they do, the drive
       # sleeps on through them (see Orbit).
+      #
+      # A model whose loop counts its passes in a byte of RAM, as the 1551's
+      # increments $61, names it in @pass_counter. A pass may then leave
+      # that byte one higher than it found it, and the drive sleeps only
+      # until the count would wrap, where the loop goes another way. The
+      # model compares the CPU without the increment's working registers
+      # (IdleCPU#counting_state), which skipping the passes sets as the
+      # last one would have left them (IdleCPU#counted).
       module Idle
         # Whether the drive may sleep through its idle loop. On by default,
         # but for a drive whose CPU logs each instruction.
@@ -64,6 +72,7 @@ module Badline
           @recording = false
           @pass_cycles = 0
           @pass_instructions = 0
+          @pass_counter = -1
           init_sleep
           init_orbits
         end
@@ -104,22 +113,51 @@ module Badline
         end
 
         # Whether the counters leave room for a whole pass.
-        def room_for_pass? = quiet_cycles >= @cycles - @record_cycles
+        def room_for_pass? = quiet_cycles >= @cycles - @record_cycles && passes_to_count.positive?
 
         # Sleeps through the pass just recorded, over and over.
         def fall_asleep
-          @pass_cycles = @cycles - @record_cycles
+          pass_cycles = @cycles - @record_cycles
+          @pass_cycles = pass_cycles
           @pass_instructions = @cpu.instructions - @record_instructions
           @asleep = true
           @host_still = false
           @owed = 0
-          @budget = quiet_cycles
+          budget = quiet_cycles
+          unless @pass_counter.negative?
+            counted = passes_to_count * pass_cycles
+            budget = counted if counted < budget
+          end
+          @budget = budget
           anchor
         end
 
+        # The RAM the pass read or wrote as it found it, but for the pass
+        # counter, one higher.
         def ram_as_found?
           ram = @bus.ram
-          @bus.touched.all? { |addr, value| ram.peek(addr) == value }
+          counter = @pass_counter
+          @bus.touched.all? do |addr, value|
+            ram.peek(addr) == (addr == counter ? value + 1 : value)
+          end
+        end
+
+        # How many more passes the pass counter can count before it wraps,
+        # and 1 without a pass counter.
+        def passes_to_count
+          counter = @pass_counter
+          counter.negative? ? 1 : 0xff - @bus.ram.peek(counter)
+        end
+
+        # Counts +passes+ more passes in the pass counter.
+        def count_passes(passes)
+          counter = @pass_counter
+          return if counter.negative?
+
+          ram = @bus.ram
+          count = ram.peek(counter) + passes
+          ram.poke(counter, count)
+          @cpu.counted(count)
         end
       end
     end

data/lib/badline/drives/engine/idle_cpu.rb

@@ -18,6 +18,24 @@ module Badline
            @address, @pointer, @dummy_address, @value, @rmw_result]
         end
 
+        # idle_state but for the byte a read-modify-write read and the one
+        # it wrote, which a pass that counts in RAM leaves one higher each
+        # time (Drives::Engine::Idle's pass counter).
+        def counting_state
+          [@program_counter, @stack_pointer, @a, @x, @y, @status.value,
+           @irq, @nmi, @irq_sample, @irq_pending, @nmi_sample, @nmi_pending, @skip_poll,
+           @boundary_irq, @boundary_nmi, @so_high, @interrupt, @brk, @pending_write, @stalled_at, @traps,
+           @operation, @optional_dummy, @boundary_crossed, @branch_taken,
+           @address, @pointer, @dummy_address]
+        end
+
+        # The working registers as the increment that brought a counter to
+        # +count+ left them.
+        def counted(count)
+          @value = (count - 1) & 0xff
+          @rmw_result = count
+        end
+
         # Counts +cycles+ cycles and +instructions+ instructions that ran
         # without changing anything idle_state holds.
         def fast_forward(cycles, instructions)

data/lib/badline/drives/engine/serial_connection.rb

@@ -0,0 +1,25 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    module Engine
+      # A drive on the serial bus, beside Core: the 1541, the 1571 and the
+      # 1581. It hears ATN on connecting (hear_atn) and drives the bus
+      # (serial_output).
+      module SerialConnection
+        attr_reader :serial_bus
+
+        # Plugs the drive into a serial bus, leaving the one it was on. A drive
+        # starts out on a bus of its own, with nothing else on it.
+        def connect(serial_bus)
+          settle!
+          @serial_bus&.detach(self)
+          @serial_bus = serial_bus
+          @serial_port.bus = serial_bus
+          serial_bus.attach(self)
+          hear_atn
+        end
+      end
+    end
+  end
+end

data/lib/badline/drives/engine/sleep.rb

@@ -104,6 +104,7 @@ module Badline
           cycles = passes * @pass_cycles
           @cpu.fast_forward(cycles, passes * @pass_instructions)
           fast_forward_chips(cycles)
+          count_passes(passes)
           @cycles += cycles
           @budget -= cycles
           cycles

data/lib/badline/drives/engine.rb

@@ -4,6 +4,7 @@ require "badline/drives/engine/sleep"
 require "badline/drives/engine/idle"
 require "badline/drives/engine/orbit"
 require "badline/drives/engine/core"
+require "badline/drives/engine/serial_connection"
 require "badline/drives/engine/vias"
 require "badline/drives/engine/fast_serial"
 require "badline/drives/engine/idle_cpu"

data/lib/badline/drives/ieee_bus.rb

@@ -0,0 +1,28 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    # The IEEE-488 bus between a PET and its drives: eight data lines, DIO1
+    # to DIO8, and the control lines EOI, DAV, NRFD, NDAC and ATN, each open
+    # collector and active low, so a line is low while anything on the bus
+    # pulls it low. The PET is the controller and always on the bus, and
+    # reads back every line it drives.
+    #
+    # No device plugs in yet, so the lines carry the controller's levels
+    # alone: nobody answers a handshake, and the KERNAL reports DEVICE NOT
+    # PRESENT for every device the traps don't serve.
+    class IEEEBus
+      # The lines as bits, the data lines in the low byte, DIO1 in bit 0.
+      DIO = 0x00ff
+      EOI = 0x0100
+      DAV = 0x0200
+      NRFD = 0x0400
+      NDAC = 0x0800
+      ATN = 0x1000
+
+      # The lines low on the bus while the controller pulls the lines in
+      # +controller+ low.
+      def low_lines(controller) = controller
+    end
+  end
+end

data/lib/badline/drives/model1541/byte_ready.rb

@@ -9,6 +9,14 @@ module Badline
         # VIA 2, which DiskVIA plugs in.
         attr_writer :via
 
+        # The 1551's TIA, whose port B drives the byte to write
+        # (Drives::Model1551::TIA), where there is no VIA 2.
+        attr_writer :tia
+
+        # The byte the last BYTE READY read, which a 1551's gate array
+        # latches.
+        attr_accessor :latched_byte
+
         # Whether BYTE READY reached SO for the CPU to sample on the drive's
         # next cycle.
         attr_accessor :so_pending
@@ -25,15 +33,23 @@ module Badline
         # on, latches port A. It reaches the CPU's SO pin while VIA 2's CA2
         # (SOE) is high, which lets the DOS spin on BVC for each byte. The CPU
         # samples SO on the next cycle.
+        #
+        # A 1551 has no VIA there: its gate array latches the byte read for
+        # its TIA's port B (latched_byte), and BYTE LATCHED reaches its
+        # CPU's port.
         def byte_ready!
           @byte_latched = true
-          @via.ca1 = false
-          @so_pending = true if @via.ca2_output
+          @latched_byte = @shift & 0xff
+          via = @via
+          return unless via
+
+          via.ca1 = false
+          @so_pending = true if via.ca2_output
         end
 
         # BYTE READY lets go of CA1 with the next bit.
         def byte_ready_ended!
-          @via.ca1 = true
+          @via&.ca1 = true
         end
 
         # Whether BYTE READY has come since the CPU last read VIA 2, as the

data/lib/badline/drives/model1541/mechanism.rb

@@ -90,6 +90,8 @@ module Badline
         # on phase 0.
         def initialize(slip: 0)
           @via = nil
+          @tia = nil
+          @latched_byte = 0
           @so_pending = false
           @disk = nil
           @half_track = START_HALF_TRACK
@@ -275,11 +277,18 @@ module Badline
           return unless @bits == 8
 
           @bits = 0
-          @write_shift = @writing ? @via.port_a_output : @shift & 0xff
+          @write_shift = @writing ? write_byte : @shift & 0xff
           @byte_ready = true
           byte_ready!
         end
 
+        # The byte the write shift register loads in write mode: what VIA 2
+        # drives on port A, or on a 1551 what its TIA drives on port B.
+        def write_byte
+          via = @via
+          via ? via.port_a_output : @tia.port_b_output
+        end
+
         # The stepper's rotor turns with the head, a phase to each half
         # track, so the energized phase pulls the head to the neighbouring
         # half track it belongs to. A phase two away pulls both ways, and the

data/lib/badline/drives/model1541.rb

@@ -18,6 +18,7 @@ module Badline
     # clocks it against the host and sleeps through the DOS's idle loop.
     class Model1541
       include Engine::Core
+      include Engine::SerialConnection
       include Engine::VIAs
 
       CLOCK_HZ = 1_000_000

data/lib/badline/drives/model1551/bus.rb

@@ -0,0 +1,138 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model1551
+      # The drive CPU's bus, as the gate array decodes it (schematic 251860):
+      #
+      # $0000-$0001 - the 6510T's port (Port)
+      # $0002-$07FF - 2 KB of RAM
+      # $4000-$7FFF - the TIA, its eight registers mirrored
+      # $C000-$FFFF - the DOS ROM
+      #
+      # Writes to the ROM and to the rest go nowhere, and a read from the
+      # rest finds the last byte on the data bus.
+      #
+      # While Engine::Idle records a pass of the DOS's idle loop, the bus
+      # watches it (watch!): the RAM it reads and writes, and whether it
+      # reached the port or the TIA, which makes the pass volatile, but for
+      # reads of the TIA's port A, the cable's data lines, which hold still
+      # until the computer moves them. While Engine::Orbit looks for an
+      # orbit, the bus guards the drive (guard!), and any access to the
+      # port or the TIA taints it.
+      class Bus
+        include Addressable
+
+        attr_reader :ram, :rom, :port, :tia, :data, :volatile, :touched, :tainted, :touched_timers
+
+        def initialize(rom:, port:, tia:)
+          addressable_at(0, length: 2**16)
+          @ram = Memory.new([], length: 0x0800, start: 0)
+          @rom = rom
+          @port = port
+          @tia = tia
+          @data = 0
+          @recording = @guarding = @watching = false
+          @volatile = @tainted = false
+          @touched = {}
+          @touched_timers = 0
+        end
+
+        def peek(addr)
+          return @data = @rom.peek(addr) if addr >= 0xc000
+
+          if addr < 0x0800
+            return @data = port_peek(addr) if addr < 2
+
+            touch(addr) if @recording
+            return @data = @ram.peek(addr)
+          end
+          return @data unless addr.between?(0x4000, 0x7fff)
+
+          watch_chip(addr.nobits?(0x07)) if @watching
+          @data = @tia.peek(addr)
+        end
+
+        def poke(addr, value)
+          @data = value
+          if addr < 0x0800
+            return port_poke(addr, value) if addr < 2
+
+            touch(addr) if @recording
+            @ram.poke(addr, value)
+          elsif addr.between?(0x4000, 0x7fff)
+            watch_chip(false) if @watching
+            @tia.poke(addr, value)
+          end
+        end
+
+        # Starts watching: see volatile and touched.
+        def watch!
+          @recording = true
+          @volatile = false
+          @touched = {}
+          watching!
+        end
+
+        def unwatch!
+          @recording = false
+          watching!
+        end
+
+        # Starts guarding: see tainted.
+        def guard!
+          @guarding = true
+          @tainted = false
+          watching!
+        end
+
+        # The drive's RAM and the byte last on its data bus, in a keyed
+        # snapshot module (BL-D8-RAM).
+        def save_fields(out)
+          out.int("data", @data).bytes("ram", @ram.read(0, @ram.length))
+        end
+
+        def load_fields(input)
+          @data = input.byte("data", @data)
+          ram = @ram.read(0, @ram.length)
+          @ram.write(0, input.bytes_into("ram", ram))
+          @watching = false
+        end
+
+        private
+
+        def port_peek(addr)
+          watch_chip(false) if @watching
+          @port.peek(addr)
+        end
+
+        def port_poke(addr, value)
+          watch_chip(false) if @watching
+          @port.poke(addr, value)
+        end
+
+        def touch(addr)
+          @touched[addr] = @ram.peek(addr) unless @touched.key?(addr)
+        end
+
+        def watching!
+          @watching = @recording || @guarding
+        end
+
+        # The CPU reached the port or the TIA: +steady+ for a read of the
+        # TIA's port A.
+        def watch_chip(steady)
+          if @recording && !steady
+            @volatile = true
+            @recording = false
+          end
+          if @guarding
+            @tainted = true
+            @guarding = false
+          end
+          watching!
+        end
+      end
+    end
+  end
+end

data/lib/badline/drives/model1551/cable.rb

@@ -0,0 +1,107 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model1551
+      # TCBM, the cable between the 1551's TIA and the 6523 TIA in its
+      # interface in the computer's expansion port (zimmers.net's 1551
+      # memory map, schematic 251860):
+      #
+      # - the eight data lines join the two port As;
+      # - the drive's STATUS0 and STATUS1 (PC0-1) reach the computer's PB0-1;
+      # - the drive's ACK (PC3) reaches the computer's PC7;
+      # - the computer's DAV (PC6) reaches the drive's PC7;
+      # - the drive's DEV (PC2) picks the interface's address (Model1551).
+      #
+      # The drive pulls every line up, so a line neither side drives low
+      # reads 1. The computer's other port B and C pins read 0.
+      #
+      # The computer sees the drive's lines as soon as the drive writes
+      # them. The drive sees the computer's a host cycle late, as the
+      # cable latched them at the end of the last (latch_host), as a drive
+      # on the serial bus sees ATN: the cable is the 1551's serial port to
+      # Drives::Engine::Core, and a write that moves the computer's lines
+      # wakes a drive asleep in its idle loop (atn_moved?).
+      class Cable
+        STATUS = 0x03
+        DEV = 0x04
+        ACK = 0x08
+        DAV = 0x40
+
+        attr_reader :host, :drive
+
+        # Plugs the cable into +host+, the computer's Chips::TIA, and
+        # +drive+, the drive's (Model1551::TIA), for +unit+, the drive.
+        def initialize(host, drive, unit)
+          @host = host
+          @drive = drive
+          @unit = unit
+          @data = 0xff
+          @dav = DAV
+          @moved = false
+          host.cable = self
+          drive.cable = self
+          relatch
+        end
+
+        # Pulls the cable out: the computer's TIA reads 0 on every input and
+        # the drive's lines float high.
+        def unplug
+          @host.cable = nil
+          @drive.cable = nil
+          host_inputs = @host.inputs
+          drive_inputs = @drive.inputs
+          3.times do |port|
+            host_inputs[port] = 0
+            drive_inputs[port] = 0xff
+          end
+        end
+
+        # Whether the computer moved its lines since latch_host.
+        def atn_moved? = @moved
+
+        # Takes the computer's lines for the drive's cycles in the next host
+        # cycle.
+        def latch_host
+          return unless @moved
+
+          @moved = false
+          relatch
+        end
+
+        # Takes the computer's lines as they stand, as a snapshot leaves
+        # them.
+        def relatch
+          host = @host
+          @data = host.output(0)
+          @dav = host.output(2) & DAV
+          @moved = false
+          moved
+        end
+
+        # Either side wrote its TIA: the computer's inputs follow the drive
+        # at once, and the drive's follow the lines last latched.
+        def moved
+          host = @host
+          drive = @drive
+          drive_data = drive.output(0)
+          drive_lines = drive.output(2)
+          host_lines = host.output(2)
+          host_data = host.output(0)
+          host_inputs = host.inputs
+          host_inputs[0] = host_data & drive_data
+          host_inputs[1] = drive_lines & STATUS
+          host_inputs[2] = ((drive_lines & ACK) << 4) | (host_lines & DAV)
+          drive_inputs = drive.inputs
+          drive_inputs[0] = @data & drive_data
+          drive_inputs[2] = (drive_inputs[2] & 0x7f) | (@dav << 1)
+          @unit.dev_line(drive_lines.anybits?(DEV))
+          return if @moved || (host_data == @data && (host_lines & DAV) == @dav)
+
+          @moved = true
+          @unit.host_written!
+        end
+      end
+    end
+  end
+end

data/lib/badline/drives/model1551/cpu.rb

@@ -0,0 +1,14 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model1551
+      # The drive's 6510T, a 6510 with an 8-bit port (Port), on the drive's
+      # Bus.
+      class CPU
+        include Badline::Chips::CPU::Core
+        include Engine::IdleCPU
+      end
+    end
+  end
+end

data/lib/badline/drives/model1551/keyed_state.rb

@@ -0,0 +1,65 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model1551
+      # The drive's own fields in a keyed snapshot module (BL-D8): its
+      # model, its clock phase, its cycle count, the 555's count to its
+      # next pulse and the byte the gate array latched. A save settles the
+      # drive first, so it is awake; a load forgets its orbits.
+      module KeyedState
+        def save_fields(out)
+          settle!
+          out.text("model", model_name).int("phase", @phase).int("cycles", @cycles).int("irq_timer", @irq_timer)
+          out.int("latched_byte", @mechanism.latched_byte)
+        end
+
+        def load_fields(input)
+          settle!
+          input.choice("model", [model_name], model_name)
+          @phase = input.int("phase", @phase)
+          @cycles = input.int("cycles", @cycles)
+          @irq_timer = input.int("irq_timer", @irq_timer).clamp(1, IRQ_PERIOD)
+          @mechanism.latched_byte = input.byte("latched_byte", @mechanism.latched_byte)
+        end
+
+        # The drive as modules of its own, named from `name` (BL-D8 for
+        # device 8): its own fields, its RAM, the CPU's port, the drive's
+        # TIA, its interface's TIA in the computer, the CPU, the mechanism
+        # and the disk, when one is in.
+        def save_modules(sections, name)
+          sections << Snapshot::Keyed.section(name) { |out| save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-RAM") { |out| @bus.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-PORT") { |out| @port.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-TIA") { |out| @tia.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-HOSTTIA") { |out| @host_tia.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-CPU") { |out| @cpu.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-MECH") { |out| @mechanism.save_fields(out) }
+          disk = @mechanism.disk
+          sections << Snapshot::Keyed.section("#{name}-DISK") { |out| disk.save_fields(out) } if disk
+          sections
+        end
+
+        # The drive from its modules, `input` being its own. No disk module
+        # means no disk in the drive. The cable's lines and the mechanism's
+        # mode follow the TIAs once both are loaded.
+        def load_modules(modules, input, name)
+          load_fields(input)
+          @bus.load_fields(modules.required("#{name}-RAM"))
+          @port.load_fields(modules.required("#{name}-PORT"))
+          @tia.load_fields(modules.required("#{name}-TIA"))
+          @host_tia.load_fields(modules.required("#{name}-HOSTTIA"))
+          @cpu.load_fields(modules.required("#{name}-CPU"))
+          disk_input = modules.optional("#{name}-DISK")
+          disk = disk_input.nil? ? nil : Model1541::Disk.from_fields(disk_input, detached: modules.detached?)
+          @mechanism.load_fields(modules.required("#{name}-MECH"), disk)
+          @cable.relatch
+          @cpu.restored!
+          forget_orbits
+        end
+      end
+
+      include KeyedState
+    end
+  end
+end

data/lib/badline/drives/model1551/port.rb

@@ -0,0 +1,74 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model1551
+      # The 6510T's port at $00 (direction) and $01 (data), wired to the
+      # mechanism in the bits of the 1541's VIA 2 port B (zimmers.net's 1551
+      # memory map, schematic 251860):
+      #
+      #   P0-1  stepper phase (out)       P4    write protect (in, 1 = writable)
+      #   P2    motor on (out)            P5-6  bit rate, speed zone 0-3 (out)
+      #   P3    activity LED (out)        P7    BYTE LATCHED (in)
+      #
+      # An output pin reads back what it drives, and a pin left as an input
+      # drives nothing into the mechanism.
+      class Port
+        WRITE_PROTECT = 0x10
+        BYTE_LATCHED = 0x80
+
+        attr_reader :ddr, :data
+
+        def initialize(mechanism)
+          @mechanism = mechanism
+          @ddr = 0
+          @data = 0
+        end
+
+        def reset!
+          @ddr = 0
+          @data = 0
+          changed
+        end
+
+        def peek(addr)
+          return @ddr if addr.zero?
+
+          ddr = @ddr
+          (@data & ddr) | (inputs & ~ddr & 0xff)
+        end
+
+        def poke(addr, value)
+          if addr.zero?
+            @ddr = value
+          else
+            @data = value
+          end
+          changed
+        end
+
+        # The registers, in a keyed snapshot module (BL-D8-PORT).
+        def save_fields(out)
+          out.int("ddr", @ddr).int("data", @data)
+        end
+
+        def load_fields(input)
+          @ddr = input.byte("ddr", @ddr)
+          @data = input.byte("data", @data)
+        end
+
+        private
+
+        def inputs
+          mechanism = @mechanism
+          value = (mechanism.read_b(0xff) & WRITE_PROTECT) | (0xff & ~(WRITE_PROTECT | BYTE_LATCHED))
+          mechanism.byte_latched? ? value | BYTE_LATCHED : value
+        end
+
+        def changed
+          @mechanism.port_b_written(@data & @ddr)
+        end
+      end
+    end
+  end
+end