badline 0.15.0 → 0.16.0

data/lib/badline/chips/crtc.rb

@@ -0,0 +1,163 @@
+# frozen_string_literal: true
+
+require "badline/chips/crtc/keyed_state"
+
+module Badline
+  module Chips
+    # The MOS 6545 CRTC, as the later PETs drive their screens with: an
+    # address register at even addresses selects one of eighteen registers,
+    # which the odd addresses write. Of them only the light pen's, R16 and
+    # R17, and the cursor address, R14 and R15, read back; every other read
+    # finds 0.
+    #
+    # Its counters run one character a cycle, and compare with the
+    # registers as they stand that cycle, so a write lands from the next
+    # character on:
+    #
+    # - The character counter runs from 0 to R0, then a line ends. The
+    #   display shows from character 0 until the counter equals R1, and
+    #   horizontal sync starts where it equals R2. A compare the counter has
+    #   already passed doesn't happen that line: the display then runs on
+    #   to the line's end.
+    # - The line counter (RA, five bits) counts a character row's lines. A
+    #   row ends after the line where it equals R9; past R9 it runs on to
+    #   31 and wraps.
+    # - The row counter (seven bits) counts rows to R4. R5 more lines of
+    #   vertical adjust follow, then the frame starts again. The display
+    #   stops at the start of the row the counter equals R6, and comes back
+    #   at the next frame; vertical sync starts with row R7 and lasts
+    #   VSYNC_LINES lines.
+    # - The memory address (MA, fourteen bits) starts each frame at
+    #   R12:R13 and counts one a character. Each line starts again from its
+    #   row's start, which the last line of a row moves on to the address
+    #   where the counter equals R1.
+    #
+    # Each displayed character goes to the output's #character with MA, RA
+    # and the characters since horizontal sync last started; the output
+    # also hears of each #hsync as it starts, each #line_end, the
+    # #rows_end where the display stops for the rest of the frame, and each
+    # #frame_start.
+    class CRTC
+      # The bits each register keeps.
+      MASKS = [0xff, 0xff, 0xff, 0xff, 0x7f, 0x1f, 0x7f, 0x7f, 0xff, 0x1f, 0x7f, 0x1f,
+               0x3f, 0xff, 0x3f, 0xff, 0x3f, 0xff].freeze
+
+      VSYNC_LINES = 16
+
+      attr_reader :registers, :column, :line, :row, :address
+
+      # The characters since horizontal sync last started.
+      attr_reader :since_hsync
+
+      # +registers+ is the register file, which the output may read too.
+      def initialize(output, registers: Array.new(MASKS.length, 0))
+        @output = output
+        @registers = registers
+        reset!
+      end
+
+      # The RES pin stops the counters at the start of a frame. The
+      # registers keep their values.
+      def reset!
+        @selected = 0
+        @column = 0
+        @since_hsync = 0
+        @vsync_lines = 0
+        start_frame
+      end
+
+      # Whether vertical sync is on.
+      def vsync? = @vsync_lines.positive?
+
+      # Whether the display shows the character the counters are at.
+      def display? = @row_display && @column_display
+
+      def peek(addr)
+        return 0 if addr.nobits?(0x01) || @selected < 14 || @selected >= MASKS.length
+
+        @registers[@selected]
+      end
+
+      def poke(addr, value)
+        if addr.nobits?(0x01)
+          @selected = value & 0x1f
+        elsif @selected < MASKS.length
+          @registers[@selected] = value & MASKS[@selected]
+        end
+      end
+
+      def cycle!
+        regs = @registers
+        column = @column
+        if column == regs[1]
+          @column_display = false
+          @row_start = @address if @line == regs[9]
+        end
+        @output.character(@address, @line, @since_hsync) if @column_display && @row_display
+        if column == regs[2]
+          @since_hsync = 1
+          @output.hsync
+        else
+          @since_hsync += 1
+        end
+        @address = (@address + 1) & 0x3fff
+        if column == regs[0]
+          @column = 0
+          end_line
+        else
+          @column = (column + 1) & 0xff
+        end
+      end
+
+      private
+
+      def end_line
+        @output.line_end
+        @vsync_lines -= 1 if @vsync_lines.positive?
+        @column_display = true
+        if @adjusting
+          @line += 1
+          @line >= @registers[5] ? start_frame : @address = @row_start
+        elsif @line == @registers[9]
+          end_row
+        else
+          @line = (@line + 1) & 0x1f
+          @address = @row_start
+        end
+      end
+
+      def end_row
+        @line = 0
+        if @row == @registers[4]
+          return start_frame if @registers[5].zero?
+
+          @adjusting = true
+        else
+          @row = (@row + 1) & 0x7f
+          start_row
+        end
+        @address = @row_start
+      end
+
+      def start_frame
+        @line = 0
+        @row = 0
+        @adjusting = false
+        @row_display = true
+        @column_display = true
+        @row_start = ((@registers[12] << 8) | @registers[13]) & 0x3fff
+        @address = @row_start
+        start_row
+        @output.frame_start
+      end
+
+      def start_row
+        if @row == @registers[6] && @row_display
+          @row_display = false
+          @output.rows_end
+        end
+        @vsync_lines = VSYNC_LINES if @row == @registers[7]
+      end
+    end
+  end
+end

data/lib/badline/chips/pia/control_lines.rb

@@ -0,0 +1,138 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class PIA
+      # One side's control register, CRA or CRB, its two control lines, CA1
+      # and CA2 or CB1 and CB2, and their interrupt flags.
+      #
+      #   bit 0    C1 interrupt enable
+      #   bit 1    C1 active edge, rising when set
+      #   bit 2    the port (1) or its direction register (0) at the same address
+      #   bits 5-3 C2:
+      #            0e0  input, e the interrupt enable, falling edge
+      #            1e0  input, rising edge
+      #            100  handshake output
+      #            101  pulse output
+      #            110  low output
+      #            111  high output
+      #   bit 6    C2 flag, read only, held clear while C2 is an output
+      #   bit 7    C1 flag, read only
+      #
+      # A flag is set by its line's active edge whether or not its interrupt
+      # is enabled, and both are cleared by a read of the port. In handshake
+      # mode C2 goes low on the strobing access and back high on the next
+      # active C1 edge; in pulse mode it goes low for the cycle after it.
+      # Side A strobes on a read of the port, side B on a write.
+      class ControlLines
+        attr_reader :c1_high, :c2_high
+
+        # The level driven on C2, high while it is an input.
+        attr_reader :c2_output
+
+        def initialize(strobe_on_read:)
+          @strobe_on_read = strobe_on_read
+          @c1_high = @c2_high = true
+          reset!
+        end
+
+        # Every bit clear: C2 an input, both interrupts off and the
+        # direction register selected. The input levels carry over.
+        def reset!
+          @control = 0
+          @c1_flag = @c2_flag = false
+          @handshake_low = false
+          @pulse = 0
+          drive
+        end
+
+        # The control register as read, the flags in bits 7 and 6.
+        def register
+          value = @control
+          value |= 0x80 if @c1_flag
+          value |= 0x40 if @c2_flag
+          value
+        end
+
+        # Writes bits 0-5; the flags can't be written. A new C2 mode starts
+        # with any handshake or pulse over.
+        def register=(value)
+          mode = c2_mode
+          @control = value & 0x3f
+          @c2_flag = false if c2_output?
+          unless c2_mode == mode
+            @handshake_low = false
+            @pulse = 0
+          end
+          drive
+        end
+
+        def port_selected? = @control.anybits?(0x04)
+
+        def irq? = (@c1_flag && @control.anybits?(0x01)) || (@c2_flag && @control & 0x28 == 0x08)
+
+        # Only the pulse output needs the clock.
+        def pulsing? = @pulse.positive?
+
+        def cycle!
+          @pulse -= 1
+          drive if @pulse.zero?
+        end
+
+        # A new C1 level. An active edge sets the flag and ends a handshake.
+        def c1=(high)
+          return if high == @c1_high
+
+          @c1_high = high
+          return unless high == @control.anybits?(0x02)
+
+          @c1_flag = true
+          @handshake_low = false
+          drive
+        end
+
+        # A new C2 level. An active edge sets the flag while C2 is an input.
+        def c2=(high)
+          return if high == @c2_high
+
+          @c2_high = high
+          @c2_flag = true if !c2_output? && high == @control.anybits?(0x10)
+        end
+
+        # A read of the port, which clears both flags.
+        def port_read!
+          @c1_flag = @c2_flag = false
+          strobe if @strobe_on_read
+        end
+
+        def port_written!
+          strobe unless @strobe_on_read
+        end
+
+        private
+
+        def c2_output? = @control.anybits?(0x20)
+
+        def c2_mode = c2_output? ? @control & 0x38 : 0
+
+        def strobe
+          case @control & 0x38
+          when 0x20 then @handshake_low = true
+          when 0x28 then @pulse = 2
+          else return
+          end
+          drive
+        end
+
+        def drive
+          @c2_output = case @control & 0x38
+                       when 0x20 then !@handshake_low
+                       when 0x28 then @pulse.zero?
+                       when 0x30 then false
+                       else true
+                       end
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/pia/keyed_parts.rb

@@ -0,0 +1,56 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class PIA
+      class ControlLines
+        # A side's control register, its lines' levels, its flags and the
+        # handshake or pulse under way, under `prefix`. The level driven on
+        # C2 follows from them on load.
+        module KeyedState
+          def save_fields(out, prefix)
+            out.int("#{prefix}control", @control).bool("#{prefix}c1_high", @c1_high).bool("#{prefix}c2_high", @c2_high)
+            out.bool("#{prefix}c1_flag", @c1_flag).bool("#{prefix}c2_flag", @c2_flag)
+            out.bool("#{prefix}handshake_low", @handshake_low).int("#{prefix}pulse", @pulse)
+          end
+
+          def load_fields(input, prefix)
+            @control = input.masked("#{prefix}control", @control, 0x3f)
+            @c1_high = input.bool("#{prefix}c1_high", @c1_high)
+            @c2_high = input.bool("#{prefix}c2_high", @c2_high)
+            @c1_flag = input.bool("#{prefix}c1_flag", @c1_flag)
+            @c2_flag = input.bool("#{prefix}c2_flag", @c2_flag)
+            @handshake_low = input.bool("#{prefix}handshake_low", @handshake_low)
+            @pulse = input.masked("#{prefix}pulse", @pulse, 0x03)
+            drive
+          end
+        end
+
+        include KeyedState
+      end
+
+      # The PIA's fields in a keyed snapshot module (Snapshot::Keyed): the
+      # output and direction registers, and each side's control lines under
+      # ca. and cb. The peripheral restores its own state.
+      module KeyedState
+        def save_fields(out)
+          out.int("ora", @ora).int("orb", @orb).int("ddra", @ddra).int("ddrb", @ddrb)
+          @ca.save_fields(out, "ca.")
+          @cb.save_fields(out, "cb.")
+          out
+        end
+
+        def load_fields(input)
+          @ora = input.byte("ora", @ora)
+          @orb = input.byte("orb", @orb)
+          @ddra = input.byte("ddra", @ddra)
+          @ddrb = input.byte("ddrb", @ddrb)
+          @ca.load_fields(input, "ca.")
+          @cb.load_fields(input, "cb.")
+        end
+      end
+
+      include KeyedState
+    end
+  end
+end

data/lib/badline/chips/pia.rb

@@ -0,0 +1,138 @@
+# frozen_string_literal: true
+
+require "badline/chips/pia/control_lines"
+require "badline/chips/pia/keyed_parts"
+
+module Badline
+  module Chips
+    # The MOS 6520 PIA (Peripheral Interface Adapter), the PET's two: two
+    # 8-bit ports, A and B, each with a direction register, a 1 making the
+    # pin an output, and a control register for its pair of control lines
+    # (ControlLines). Each side has its own IRQ output, IRQA and IRQB. There
+    # are no timers.
+    #
+    # Four registers repeat on two address lines: port A or DDRA, CRA, port
+    # B or DDRB and CRB, the port or the direction register picked by bit 2
+    # of its control register.
+    #
+    # Port A reads its pins, whatever drives them. Port B reads its output
+    # bits from its output register and its input bits from the pins. An
+    # input pin floats high, and a peripheral pulls lines low through
+    # read_a and read_b, as a VIA's does. The control lines take levels
+    # from outside through ca1= and friends.
+    class PIA
+      attr_reader :peripheral
+
+      def initialize(peripheral: nil)
+        @peripheral = peripheral
+        @ca = ControlLines.new(strobe_on_read: true)
+        @cb = ControlLines.new(strobe_on_read: false)
+        reset!
+      end
+
+      # The RES line clears every register, which leaves every line an
+      # input and releases both IRQs.
+      def reset!
+        @ora = @orb = @ddra = @ddrb = 0x00
+        @ca.reset!
+        @cb.reset!
+      end
+
+      def irqa? = @ca.irq?
+
+      def irqb? = @cb.irq?
+
+      def irq? = @ca.irq? || @cb.irq?
+
+      def cycle!
+        @ca.cycle! if @ca.pulsing?
+        @cb.cycle! if @cb.pulsing?
+      end
+
+      def cra = @ca.register
+
+      def crb = @cb.register
+
+      # Port A as driven by ORA and DDRA, input lines floating high.
+      def port_a_output = driven_lines(@ora, @ddra)
+
+      def port_b_output = driven_lines(@orb, @ddrb)
+
+      def ca1=(high)
+        @ca.c1 = high
+      end
+
+      def ca2=(high)
+        @ca.c2 = high
+      end
+
+      def cb1=(high)
+        @cb.c1 = high
+      end
+
+      def cb2=(high)
+        @cb.c2 = high
+      end
+
+      def ca2_output = @ca.c2_output
+
+      def cb2_output = @cb.c2_output
+
+      def peek(addr)
+        case addr & 0x03
+        when 0x00 then @ca.port_selected? ? read_port_a : @ddra
+        when 0x01 then @ca.register
+        when 0x02 then @cb.port_selected? ? read_port_b : @ddrb
+        else @cb.register
+        end
+      end
+
+      def poke(addr, value)
+        case addr & 0x03
+        when 0x00 then write_port_a(value)
+        when 0x01 then @ca.register = value
+        when 0x02 then write_port_b(value)
+        else @cb.register = value
+        end
+      end
+
+      private
+
+      def driven_lines(register, direction)
+        (register & direction) | (~direction & 0xff)
+      end
+
+      def read_port_a
+        lines = port_a_output
+        lines &= @peripheral.read_a(lines) if @peripheral
+        @ca.port_read!
+        lines
+      end
+
+      def read_port_b
+        lines = port_b_output
+        lines &= @peripheral.read_b(lines) if @peripheral
+        @cb.port_read!
+        (@orb & @ddrb) | (lines & ~@ddrb & 0xff)
+      end
+
+      def write_port_a(value)
+        if @ca.port_selected?
+          @ora = value
+          @ca.port_written!
+        else
+          @ddra = value
+        end
+      end
+
+      def write_port_b(value)
+        if @cb.port_selected?
+          @orb = value
+          @cb.port_written!
+        else
+          @ddrb = value
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/tia.rb

@@ -9,20 +9,28 @@ module Badline
     #
     # A pin read as an output returns what the port drives, and one read as
     # an input returns what the other side drives, #inputs, per port.
+    #
+    # A cable plugged in (Drives::Model1551::Cable) hears every write and
+    # reset, which can move the pins it carries.
     class TIA
       attr_reader :ports, :directions
 
       # What the other side drives onto each port's pins.
       attr_reader :inputs
 
+      # The cable to the other side, or nil.
+      attr_accessor :cable
+
       def initialize
         @inputs = [0, 0, 0]
+        @cable = nil
         reset!
       end
 
       def reset!
         @ports = [0, 0, 0]
         @directions = [0, 0, 0]
+        @cable&.moved
       end
 
       def peek(addr)
@@ -43,6 +51,14 @@ module Badline
         else
           @ports[register] = value
         end
+        @cable&.moved
+      end
+
+      # The levels on +port+'s pins as the chip leaves them: an output's
+      # level, and 1 for an input, which the chip doesn't drive.
+      def output(port)
+        direction = @directions[port]
+        (@ports[port] & direction) | (~direction & 0xff)
       end
 
       # The ports, their directions and what the other side drives, in a

data/lib/badline/core.rb

@@ -18,6 +18,8 @@ require "badline/c64/banked_ram"
 require "badline/status"
 require "badline/input"
 require "badline/chips"
+require "badline/chips/pia"
+require "badline/chips/crtc"
 require "badline/drives"
 require "badline/c64/bus"
 require "badline/c64/reu"
@@ -27,6 +29,7 @@ require "badline/snapshot/storage_setup"
 require "badline/machine"
 require "badline/c64"
 require "badline/vic20"
+require "badline/pet"
 require "badline/storage"
 require "badline/sid_tune"
 require "badline/c64/cartridge"

data/lib/badline/drives/datasette/keyed_state.rb

@@ -4,15 +4,17 @@ module Badline
   module Drives
     class Datasette
       # The datasette's fields in a keyed snapshot module (Snapshot::Keyed,
-      # BL-TAPE): the keys, the motor, the countdown to the next pulse, and
-      # a tape in it under tape.*: its path, its bytes and how far it has
-      # played. A tape that isn't in leaves tape.* out. A datasette that
+      # BL-TAPE): the keys, the motor, the countdown to the next pulse,
+      # whether it records, the cycles since the write line's last edge and
+      # that line's level, and a tape in it under tape.*: its path, its
+      # bytes and how far it has played. A tape that isn't in leaves tape.* out. A datasette that
       # times the read line's level adds when in the countdown the line
       # rises, and whether a recording's low half wave is on the tape. The
       # sense and flag handlers don't fire on load.
       module KeyedState
         def save_fields(out)
           out.bool("playing", @playing).bool("motor", @motor).int("countdown", @countdown)
+          out.bool("recording", @recording).int("since", @since).bool("write_high", @write_high)
           out.int("rise_at", @rise_at).bool("low_recorded", @low_recorded) if @level
           tape = @tape
           return out unless tape
@@ -26,6 +28,9 @@ module Badline
           @playing = input.bool("playing", @playing)
           @motor = input.bool("motor", @motor)
           @countdown = input.int("countdown", @countdown)
+          @recording = input.bool("recording", @recording)
+          @since = input.int("since", @since)
+          @write_high = input.bool("write_high", @write_high)
           @rise_at = input.int("rise_at", @rise_at)
           @low_recorded = input.bool("low_recorded", @low_recorded)
           bytes = input.bytes("tape.bytes", "".b).bytes

data/lib/badline/drives/engine/core.rb

@@ -24,8 +24,11 @@ module Badline
       # sleeps through them too (see Orbit).
       #
       # A model includes Core and builds its parts, sets @clock_hz and
-      # @idle_loop, and runs one drive cycle in step. It hears ATN on
-      # connecting (hear_atn), drives the serial bus (serial_output), and
+      # @idle_loop, and runs one drive cycle in step. Its @serial_port faces
+      # the host: it says whether the host moved the lines the drive
+      # listens to (atn_moved?) and takes them for the next host cycle
+      # (latch_host), as the serial port does for ATN on the serial bus
+      # (SerialConnection) and the TCBM cable does on the 1551. The model
       # answers Idle's and Orbit's questions about its chips, as VIAs does
       # for the 1541 and the 1571.
       module Core
@@ -33,7 +36,7 @@ module Badline
         include Idle
         include Orbit
 
-        attr_reader :device, :serial_bus
+        attr_reader :device
 
         def cpu
           settle!
@@ -62,17 +65,6 @@ module Badline
           @host_clock_hz = clock_hz
         end
 
-        # Plugs the drive into a serial bus, leaving the one it was on. A drive
-        # starts out on a bus of its own, with nothing else on it.
-        def connect(serial_bus)
-          settle!
-          @serial_bus&.detach(self)
-          @serial_bus = serial_bus
-          @serial_port.bus = serial_bus
-          serial_bus.attach(self)
-          hear_atn
-        end
-
         # Puts a Disk in the drive (Disk.from_d64 makes one from an image).
         # Nil takes the disk out.
         def insert(disk)