badline 0.11.0 → 0.11.1

data/lib/badline/z80/interrupt_acceptance.rb

@@ -0,0 +1,46 @@
+# frozen_string_literal: true
+
+module Badline
+  class Z80
+    # Taking NMI and INT between instructions. Either wakes a halted CPU,
+    # whose program counter already points past the HALT.
+    module InterruptAcceptance
+      private
+
+      # An opcode fetch whose byte is ignored, a T-state more, and a call
+      # to $0066. IFF2 keeps what IFF1 held, for RETN to restore.
+      def take_nmi
+        @nmi_pending = false
+        @halted = false
+        @iff1 = false
+        @bus.fetch(@pc)
+        refresh
+        @cycles += 5
+        push(@pc)
+        @pc = 0x66
+        @wz = 0x66
+      end
+
+      # The acknowledge cycle, an M1 with two wait states, reads a byte
+      # from the device. Mode 0 runs it as an opcode, which is a RST in
+      # practice, mode 1 calls $0038, and mode 2 calls through the vector
+      # at I and that byte.
+      def take_int
+        @halted = false
+        @f &= ~PF if @after_ld_a_ir
+        @iff1 = @iff2 = false
+        @after_ld_a_ir = false
+        @prefix = 0
+        data = @bus.acknowledge
+        refresh
+        @cycles += 6
+        return execute(data) if @im.zero?
+
+        @cycles += 1
+        push(@pc)
+        @pc = @im == 1 ? 0x38 : read_word((@i << 8) | data)
+        @wz = @pc
+      end
+    end
+  end
+end

data/lib/badline/z80/jumps.rb

@@ -0,0 +1,82 @@
+# frozen_string_literal: true
+
+module Badline
+  class Z80
+    # Jumps, calls and returns. Each leaves its target in WZ, and JP cc and
+    # CALL cc do whether they jump or not.
+    module Jumps
+      private
+
+      # The conditions bits 5-3 pick: NZ Z NC C PO PE P M.
+      def condition?(index)
+        case index
+        when 0 then @f.nobits?(ZF)
+        when 1 then @f.anybits?(ZF)
+        when 2 then @f.nobits?(CF)
+        when 3 then @f.anybits?(CF)
+        when 4 then @f.nobits?(PF)
+        when 5 then @f.anybits?(PF)
+        when 6 then @f.nobits?(SF)
+        else @f.anybits?(SF)
+        end
+      end
+
+      # NOP, EX AF,AF', DJNZ, JR and JR cc.
+      def relative_jump(row)
+        case row
+        when 0 then nil
+        when 1 then exchange_af
+        when 2 then decrement_and_jump
+        when 3 then jump_relative(fetch_byte)
+        else
+          offset = fetch_byte
+          jump_relative(offset) if condition?(row - 4)
+        end
+      end
+
+      def decrement_and_jump
+        @cycles += 1
+        offset = fetch_byte
+        @b = (@b - 1) & 0xff
+        jump_relative(offset) unless @b.zero?
+      end
+
+      def jump_relative(offset)
+        @cycles += 5
+        @pc = (@pc + offset - (offset > 127 ? 256 : 0)) & 0xffff
+        @wz = @pc
+      end
+
+      def jump(taken)
+        @wz = fetch_word
+        @pc = @wz if taken
+      end
+
+      def call(taken)
+        @wz = fetch_word
+        return unless taken
+
+        @cycles += 1
+        push(@pc)
+        @pc = @wz
+      end
+
+      def conditional_return(index)
+        @cycles += 1
+        return_from_call if condition?(index)
+      end
+
+      def return_from_call
+        @pc = pop
+        @wz = @pc
+      end
+
+      def restart(address)
+        @cycles += 1
+        push(@pc)
+        @pc = address
+        @wz = address
+      end
+    end
+  end
+end

data/lib/badline/z80/loads.rb

@@ -0,0 +1,98 @@
+# frozen_string_literal: true
+
+module Badline
+  class Z80
+    # Loads, PUSH, and IN and OUT through a port A and n address. The loads
+    # through a pointer leave the address after it in WZ, or for a store of
+    # A, A and the low byte of that address.
+    module Loads
+      private
+
+      # LD r,r' with (HL) as index 6.
+      def load_register(target, source)
+        if source == 6
+          set_plain_register(target, read_byte(operand_address))
+        elsif target == 6
+          write_byte(operand_address, plain_register(source))
+        else
+          set_register(target, register(source))
+        end
+      end
+
+      # LD r,n, and LD (IX+d),n, which reads n while it adds d.
+      def load_immediate(index)
+        return set_register(index, fetch_byte) unless index == 6
+        return write_byte(hl, fetch_byte) if @prefix.zero?
+
+        displaced
+        value = fetch_byte
+        @cycles += 2
+        write_byte(@wz, value)
+      end
+
+      def indirect_load(row)
+        case row
+        when 0 then store_a(bc)
+        when 1 then load_a(bc)
+        when 2 then store_a(de)
+        when 3 then load_a(de)
+        when 4 then store_word(hl_or_index)
+        when 5 then self.hl_or_index = load_word
+        when 6 then store_a(fetch_word)
+        else load_a(fetch_word)
+        end
+      end
+
+      def load_a(address)
+        @a = read_byte(address)
+        @wz = (address + 1) & 0xffff
+      end
+
+      def store_a(address)
+        write_byte(address, @a)
+        @wz = (@a << 8) | ((address + 1) & 0xff)
+      end
+
+      def store_word(value)
+        address = fetch_word
+        write_word(address, value)
+        @wz = (address + 1) & 0xffff
+      end
+
+      def load_word
+        address = fetch_word
+        @wz = (address + 1) & 0xffff
+        read_word(address)
+      end
+
+      def push_pair(index)
+        @cycles += 1
+        push(stack_pair(index))
+      end
+
+      # RET, EXX, JP (HL) and LD SP,HL.
+      def stack_and_exchange(index)
+        case index
+        when 0 then return_from_call
+        when 1 then exchange_alternates
+        when 2 then @pc = hl_or_index
+        else
+          @cycles += 2
+          @sp = hl_or_index
+        end
+      end
+
+      def output_immediate
+        port = (@a << 8) | fetch_byte
+        output(port, @a)
+        @wz = (port & 0xff00) | ((port + 1) & 0xff)
+      end
+
+      def input_immediate
+        port = (@a << 8) | fetch_byte
+        @wz = (port + 1) & 0xffff
+        @a = input(port)
+      end
+    end
+  end
+end

data/lib/badline/z80/main_page.rb

@@ -0,0 +1,134 @@
+# frozen_string_literal: true
+
+module Badline
+  class Z80
+    # The unprefixed opcodes, which DD and FD reuse with IX or IY for HL.
+    # An opcode splits into its quarter (bits 7-6), its row (5-3) and its
+    # column (2-0), and each quarter of the page is regular in rows and
+    # columns.
+    module MainPage
+      private
+
+      def execute(opcode)
+        case opcode >> 6
+        when 0 then execute_low(opcode)
+        when 1 then opcode == 0x76 ? @halted = true : load_register((opcode >> 3) & 7, opcode & 7)
+        when 2 then alu((opcode >> 3) & 7, operand(opcode & 7))
+        else execute_high(opcode)
+        end
+      end
+
+      def execute_low(opcode)
+        row = (opcode >> 3) & 7
+        case opcode & 7
+        when 0 then relative_jump(row)
+        when 1 then opcode.nobits?(8) ? set_pair(row >> 1, fetch_word) : add_pair(row >> 1)
+        when 2 then indirect_load(row)
+        when 3 then step_pair(row)
+        when 4 then modify(row, true)
+        when 5 then modify(row, false)
+        when 6 then load_immediate(row)
+        else accumulator_operation(row)
+        end
+      end
+
+      def execute_high(opcode)
+        row = (opcode >> 3) & 7
+        case opcode & 7
+        when 0 then conditional_return(row)
+        when 1 then opcode.nobits?(8) ? set_stack_pair(row >> 1, pop) : stack_and_exchange(row >> 1)
+        when 2 then jump(condition?(row))
+        when 3 then miscellaneous(row)
+        when 4 then call(condition?(row))
+        when 5 then opcode.nobits?(8) ? push_pair(row >> 1) : call_or_prefix(row >> 1)
+        when 6 then alu(row, fetch_byte)
+        else restart(row << 3)
+        end
+      end
+
+      # The operand of the 8-bit ALU opcodes: a register or (HL).
+      def operand(index)
+        index == 6 ? read_byte(operand_address) : register(index)
+      end
+
+      # INC and DEC on a register or (HL).
+      def modify(index, increase)
+        if index == 6
+          address = operand_address
+          value = read_byte(address)
+          @cycles += 1
+          write_byte(address, increase ? increment(value) : decrement(value))
+        else
+          set_register(index, increase ? increment(register(index)) : decrement(register(index)))
+        end
+      end
+
+      # INC and DEC on a pair, which touch no flags.
+      def step_pair(row)
+        @cycles += 2
+        index = row >> 1
+        set_pair(index, (pair(index) + (row.nobits?(1) ? 1 : -1)) & 0xffff)
+      end
+
+      def add_pair(index)
+        self.hl_or_index = add16(hl_or_index, pair(index))
+        @cycles += 7
+      end
+
+      def accumulator_operation(row)
+        case row
+        when 0, 1, 2, 3 then rotate_a(row)
+        when 4 then daa
+        when 5 then complement
+        when 6 then assign_flags((@f & (SF | ZF | PF)) | CF | (((@last_q ^ @f) | @a) & XYF))
+        else assign_flags((@f & (SF | ZF | PF)) | ((@f & CF) << 4) | ((@f & CF) ^ CF) | (((@last_q ^ @f) | @a) & XYF))
+        end
+      end
+
+      def complement
+        @a ^= 0xff
+        assign_flags((@f & (SF | ZF | PF | CF)) | HF | NF | (@a & XYF))
+      end
+
+      def miscellaneous(row)
+        case row
+        when 0 then jump(true)
+        when 1 then @prefix.zero? ? execute_bits(fetch_opcode) : execute_index_bits
+        when 2 then output_immediate
+        when 3 then input_immediate
+        when 4 then exchange_stack_top
+        when 5 then exchange_de_hl
+        when 6 then @iff1 = @iff2 = false
+        else enable_interrupts
+        end
+      end
+
+      def call_or_prefix(index)
+        case index
+        when 0 then call(true)
+        when 1 then index_prefix(1)
+        when 2 then extended_prefix
+        else index_prefix(2)
+        end
+      end
+
+      # DD and FD: the next opcode runs with IX or IY for HL. A prefix
+      # after a prefix replaces it.
+      def index_prefix(prefix)
+        @prefix = prefix
+        @last_q = 0
+        execute(fetch_opcode)
+      end
+
+      def extended_prefix
+        @prefix = 0
+        execute_extended(fetch_opcode)
+      end
+
+      def enable_interrupts
+        @iff1 = @iff2 = true
+        @after_ei = true
+      end
+    end
+  end
+end

data/lib/badline/z80/registers.rb

@@ -0,0 +1,120 @@
+# frozen_string_literal: true
+
+module Badline
+  class Z80
+    # The register file. Opcodes name 8-bit registers by a 3-bit index,
+    # B C D E H L (HL) A, and pairs by a 2-bit one, BC DE HL SP, or BC DE
+    # HL AF for PUSH and POP. After a DD or FD prefix, HL means IX or IY
+    # and H and L their halves, except beside an (IX+d) operand.
+    module Registers
+      attr_accessor :a, :f, :b, :c, :d, :e, :h, :l, :i, :r, :pc, :sp, :ix, :iy, :wz, :im, :q,
+                    :af_alt, :bc_alt, :de_alt, :hl_alt, :iff1, :iff2, :halted, :after_ei, :after_ld_a_ir
+
+      def af = (@a << 8) | @f
+      def bc = (@b << 8) | @c
+      def de = (@d << 8) | @e
+      def hl = (@h << 8) | @l
+
+      def af=(value)
+        @a = value >> 8
+        @f = value & 0xff
+      end
+
+      def bc=(value)
+        @b = value >> 8
+        @c = value & 0xff
+      end
+
+      def de=(value)
+        @d = value >> 8
+        @e = value & 0xff
+      end
+
+      def hl=(value)
+        @h = value >> 8
+        @l = value & 0xff
+      end
+
+      private
+
+      def register(index)
+        case index
+        when 0 then @b
+        when 1 then @c
+        when 2 then @d
+        when 3 then @e
+        when 4 then @prefix.zero? ? @h : index_register >> 8
+        when 5 then @prefix.zero? ? @l : index_register & 0xff
+        else @a
+        end
+      end
+
+      def set_register(index, value)
+        case index
+        when 0 then @b = value
+        when 1 then @c = value
+        when 2 then @d = value
+        when 3 then @e = value
+        when 4 then @prefix.zero? ? @h = value : self.index_register = (index_register & 0xff) | (value << 8)
+        when 5 then @prefix.zero? ? @l = value : self.index_register = (index_register & 0xff00) | value
+        else @a = value
+        end
+      end
+
+      # The register an (HL) or (IX+d) operand sits beside: H and L are
+      # always themselves.
+      def plain_register(index)
+        case index
+        when 4 then @h
+        when 5 then @l
+        else register(index)
+        end
+      end
+
+      def set_plain_register(index, value)
+        case index
+        when 4 then @h = value
+        when 5 then @l = value
+        else set_register(index, value)
+        end
+      end
+
+      def pair(index)
+        case index
+        when 0 then bc
+        when 1 then de
+        when 2 then hl_or_index
+        else @sp
+        end
+      end
+
+      def set_pair(index, value)
+        case index
+        when 0 then self.bc = value
+        when 1 then self.de = value
+        when 2 then self.hl_or_index = value
+        else @sp = value
+        end
+      end
+
+      # The pairs PUSH and POP name, with AF in place of SP.
+      def stack_pair(index) = index == 3 ? af : pair(index)
+
+      def set_stack_pair(index, value)
+        index == 3 ? self.af = value : set_pair(index, value)
+      end
+
+      def hl_or_index = @prefix.zero? ? hl : index_register
+
+      def hl_or_index=(value)
+        @prefix.zero? ? self.hl = value : self.index_register = value
+      end
+
+      def index_register = @prefix == 1 ? @ix : @iy
+
+      def index_register=(value)
+        @prefix == 1 ? @ix = value : @iy = value
+      end
+    end
+  end
+end

data/lib/badline/z80/shifts.rb

@@ -0,0 +1,64 @@
+# frozen_string_literal: true
+
+module Badline
+  class Z80
+    # Rotates, shifts and the bit operations.
+    module Shifts
+      private
+
+      # RLCA RRCA RLA RRA, which leave S, Z and P/V alone.
+      def rotate_a(operation)
+        carry = operation.even? ? @a >> 7 : @a & 1
+        @a = shifted(operation, @a, carry)
+        assign_flags((@f & (SF | ZF | PF)) | (@a & XYF) | carry)
+      end
+
+      # The CB page's rotates and shifts by bits 5-3: RLC RRC RL RR SLA SRA
+      # SLL SRL. SLL shifts a 1 in.
+      def shift(operation, value)
+        carry = operation.even? ? value >> 7 : value & 1
+        result = shifted(operation, value, carry)
+        assign_flags(SZ53P[result] | carry)
+        result
+      end
+
+      def shifted(operation, value, carry)
+        case operation
+        when 0 then ((value << 1) | carry) & 0xff
+        when 1 then (value >> 1) | (carry << 7)
+        when 2 then ((value << 1) | (@f & CF)) & 0xff
+        when 3 then (value >> 1) | ((@f & CF) << 7)
+        when 4 then (value << 1) & 0xff
+        when 5 then (value >> 1) | (value & 0x80)
+        when 6 then ((value << 1) | 1) & 0xff
+        else value >> 1
+        end
+      end
+
+      # BIT n tests a bit of +value+ and copies bits 5 and 3 from +source+:
+      # the operand for a register, WZ's high byte for a memory operand.
+      def bit(number, value, source)
+        tested = value & (1 << number)
+        flags = (@f & CF) | HF | (source & XYF) | (tested & SF)
+        flags |= ZF | PF if tested.zero?
+        assign_flags(flags)
+      end
+
+      # RRD and RLD rotate a digit through A and (HL).
+      def rotate_digits(left)
+        address = hl
+        value = read_byte(address)
+        @cycles += 4
+        if left
+          write_byte(address, ((value << 4) | (@a & 0x0f)) & 0xff)
+          @a = (@a & 0xf0) | (value >> 4)
+        else
+          write_byte(address, ((@a << 4) | (value >> 4)) & 0xff)
+          @a = (@a & 0xf0) | (value & 0x0f)
+        end
+        @wz = (address + 1) & 0xffff
+        assign_flags((@f & CF) | SZ53P[@a])
+      end
+    end
+  end
+end

data/lib/badline/z80.rb

@@ -0,0 +1,11 @@
+# frozen_string_literal: true
+
+require "badline/z80/core"
+
+module Badline
+  # The Zilog Z80 (NMOS), which the C128 has beside its 8502. It is not
+  # part of badline/core, so a machine that has one requires it.
+  class Z80
+    include Core
+  end
+end

metadata

@@ -1,7 +1,7 @@
 --- !ruby/object:Gem::Specification
 name: badline
 version: !ruby/object:Gem::Version
-  version: 0.11.0
+  version: 0.11.1
 platform: ruby
 authors:
 - Inge Jørgensen
@@ -77,6 +77,8 @@ files:
 - lib/badline/c128/bus_state.rb
 - lib/badline/c128/color_lines.rb
 - lib/badline/c128/cpu.rb
+- lib/badline/c128/drives.rb
+- lib/badline/c128/fast_serial.rb
 - lib/badline/c128/keys.rb
 - lib/badline/c128/mmu.rb
 - lib/badline/c128/mmu_pages.rb
@@ -119,6 +121,7 @@ files:
 - lib/badline/checkpoint.rb
 - lib/badline/chrout_trap.rb
 - lib/badline/cia.rb
+- lib/badline/cia/fast_forward.rb
 - lib/badline/cia/interrupt_register.rb
 - lib/badline/cia/serial.rb
 - lib/badline/cia/state.rb
@@ -142,22 +145,34 @@ files:
 - lib/badline/data_path.rb
 - lib/badline/datasette.rb
 - lib/badline/debug_register.rb
+- lib/badline/drive.rb
+- lib/badline/drive/core.rb
+- lib/badline/drive/idle.rb
+- lib/badline/drive/idle_cpu.rb
+- lib/badline/drive/orbit.rb
+- lib/badline/drive/serial_lines.rb
+- lib/badline/drive/sleep.rb
+- lib/badline/drive/watch.rb
 - lib/badline/drive1541.rb
 - lib/badline/drive1541/bus.rb
+- lib/badline/drive1541/byte_ready.rb
 - lib/badline/drive1541/cpu.rb
 - lib/badline/drive1541/disk.rb
 - lib/badline/drive1541/disk_state.rb
 - lib/badline/drive1541/disk_via.rb
 - lib/badline/drive1541/gcr.rb
-- lib/badline/drive1541/idle.rb
 - lib/badline/drive1541/mechanism.rb
 - lib/badline/drive1541/mechanism_state.rb
-- lib/badline/drive1541/orbit.rb
 - lib/badline/drive1541/rotation.rb
 - lib/badline/drive1541/sector_reader.rb
 - lib/badline/drive1541/serial_port.rb
-- lib/badline/drive1541/sleep.rb
 - lib/badline/drive1541/track.rb
+- lib/badline/drive1571.rb
+- lib/badline/drive1571/bus.rb
+- lib/badline/drive1571/cpu.rb
+- lib/badline/drive1571/serial_port.rb
+- lib/badline/drive1571/serial_via.rb
+- lib/badline/drive1571/wd1770.rb
 - lib/badline/ffi.rb
 - lib/badline/frontend.rb
 - lib/badline/frontend/app.rb
@@ -274,6 +289,7 @@ files:
 - lib/badline/roms/c64gs.rom
 - lib/badline/roms/character.rom
 - lib/badline/roms/dos1541.rom
+- lib/badline/roms/dos1571.rom
 - lib/badline/roms/eapi/LICENSE.md
 - lib/badline/roms/eapi/README
 - lib/badline/roms/eapi/eapi-am29f040-14
@@ -385,6 +401,22 @@ files:
 - lib/badline/vic20/vic/painter.rb
 - lib/badline/vic20/vic/saved_state.rb
 - lib/badline/vic20/vic/text_window.rb
+- lib/badline/z80.rb
+- lib/badline/z80/arithmetic.rb
+- lib/badline/z80/bit_page.rb
+- lib/badline/z80/block_io.rb
+- lib/badline/z80/block_transfers.rb
+- lib/badline/z80/bus_cycles.rb
+- lib/badline/z80/core.rb
+- lib/badline/z80/exchanges.rb
+- lib/badline/z80/extended_page.rb
+- lib/badline/z80/flags.rb
+- lib/badline/z80/interrupt_acceptance.rb
+- lib/badline/z80/jumps.rb
+- lib/badline/z80/loads.rb
+- lib/badline/z80/main_page.rb
+- lib/badline/z80/registers.rb
+- lib/badline/z80/shifts.rb
 - packaging/homebrew/badline.rb
 homepage: https://github.com/elektronaut/badline
 licenses: